[PATCH] Add '-mhle' option and pre-defined macros for HLE

[darkbuck]

  Hi All

  The patch is rebased against clang trunk and there's no significant change.

  Thanks
  - Michael

Hi hfinkel, eli.friedman, chandlerc, jfifield,

http://llvm-reviews.chandlerc.com/D441

CHANGE SINCE LAST DIFF
  http://llvm-reviews.chandlerc.com/D441?vs=1146&id=1325#toc

Files:
  include/clang/Driver/Options.td
  lib/Basic/Targets.cpp
  test/Preprocessor/predefined-arch-macros.c

Index: include/clang/Driver/Options.td
===================================================================
--- include/clang/Driver/Options.td
+++ include/clang/Driver/Options.td
@@ -889,6 +889,7 @@
 def mno_xop : Flag<["-"], "mno-xop">, Group<m_x86_Features_Group>;
 def mno_f16c : Flag<["-"], "mno-f16c">, Group<m_x86_Features_Group>;
 def mno_rtm : Flag<["-"], "mno-rtm">, Group<m_x86_Features_Group>;
+def mno_hle : Flag<["-"], "mno-hle">, Group<m_x86_Features_Group>;
 
 def mno_thumb : Flag<["-"], "mno-thumb">, Group<m_Group>;
 def marm : Flag<["-"], "marm">, Alias<mno_thumb>;
@@ -932,6 +933,7 @@
 def mxop : Flag<["-"], "mxop">, Group<m_x86_Features_Group>;
 def mf16c : Flag<["-"], "mf16c">, Group<m_x86_Features_Group>;
 def mrtm : Flag<["-"], "mrtm">, Group<m_x86_Features_Group>;
+def mhle : Flag<["-"], "mhle">, Group<m_x86_Features_Group>;
 def mips16 : Flag<["-"], "mips16">, Group<m_Group>;
 def mno_mips16 : Flag<["-"], "mno-mips16">, Group<m_Group>;
 def mxgot : Flag<["-"], "mxgot">, Group<m_Group>;
Index: lib/Basic/Targets.cpp
===================================================================
--- lib/Basic/Targets.cpp
+++ lib/Basic/Targets.cpp
@@ -1701,6 +1701,7 @@
   bool HasBMI2;
   bool HasPOPCNT;
   bool HasRTM;
+  bool HasHLE;
   bool HasSSE4a;
   bool HasFMA4;
   bool HasFMA;
@@ -1852,8 +1853,8 @@
     : TargetInfo(triple), SSELevel(NoSSE), MMX3DNowLevel(NoMMX3DNow),
       HasAES(false), HasPCLMUL(false), HasLZCNT(false), HasRDRND(false),
       HasBMI(false), HasBMI2(false), HasPOPCNT(false), HasRTM(false),
-      HasSSE4a(false), HasFMA4(false), HasFMA(false), HasXOP(false),
-      HasF16C(false), CPU(CK_Generic) {
+      HasHLE(false), HasSSE4a(false), HasFMA4(false), HasFMA(false),
+      HasXOP(false), HasF16C(false), CPU(CK_Generic) {
     BigEndian = false;
     LongDoubleFormat = &llvm::APFloat::x87DoubleExtended;
   }
@@ -2059,6 +2060,7 @@
   Features["bmi2"] = false;
   Features["popcnt"] = false;
   Features["rtm"] = false;
+  Features["hle"] = false;
   Features["fma4"] = false;
   Features["fma"] = false;
   Features["xop"] = false;
@@ -2132,6 +2134,7 @@
     setFeatureEnabled(Features, "bmi", true);
     setFeatureEnabled(Features, "bmi2", true);
     setFeatureEnabled(Features, "rtm", true);
+    setFeatureEnabled(Features, "hle", true);
     setFeatureEnabled(Features, "fma", true);
     break;
   case CK_K6:
@@ -2281,6 +2284,8 @@
       Features["f16c"] = true;
     else if (Name == "rtm")
       Features["rtm"] = true;
+    else if (Name == "hle")
+      Features["hle"] = true;
   } else {
     if (Name == "mmx")
       Features["mmx"] = Features["3dnow"] = Features["3dnowa"] = false;
@@ -2345,6 +2350,8 @@
       Features["f16c"] = false;
     else if (Name == "rtm")
       Features["rtm"] = false;
+    else if (Name == "hle")
+      Features["hle"] = false;
   }
 
   return true;
@@ -2401,6 +2408,11 @@
       continue;
     }
 
+    if (Feature == "hle") {
+      HasHLE = true;
+      continue;
+    }
+
     if (Feature == "sse4a") {
       HasSSE4a = true;
       continue;
@@ -2625,6 +2637,12 @@
   if (HasRTM)
     Builder.defineMacro("__RTM__");
 
+  if (HasHLE) {
+    Builder.defineMacro("__HLE__");
+    Builder.defineMacro("__ATOMIC_HLE_ACQUIRE", Twine(1U << 16));
+    Builder.defineMacro("__ATOMIC_HLE_RELEASE", Twine(2U << 16));
+  }
+
   if (HasSSE4a)
     Builder.defineMacro("__SSE4A__");
 
@@ -2713,6 +2731,7 @@
       .Case("pclmul", HasPCLMUL)
       .Case("popcnt", HasPOPCNT)
       .Case("rtm", HasRTM)
+      .Case("hle", HasHLE)
       .Case("sse", SSELevel >= SSE1)
       .Case("sse2", SSELevel >= SSE2)
       .Case("sse3", SSELevel >= SSE3)
Index: test/Preprocessor/predefined-arch-macros.c
===================================================================
--- test/Preprocessor/predefined-arch-macros.c
+++ test/Preprocessor/predefined-arch-macros.c
@@ -509,11 +509,14 @@
 // RUN:     -target i386-unknown-linux \
 // RUN:   | FileCheck %s -check-prefix=CHECK_CORE_AVX2_M32
 // CHECK_CORE_AVX2_M32: #define __AES__ 1
+// CHECK_CORE_AVX2_M32: #define __ATOMIC_HLE_ACQUIRE 65536
+// CHECK_CORE_AVX2_M32: #define __ATOMIC_HLE_RELEASE 131072
 // CHECK_CORE_AVX2_M32: #define __AVX__ 1
 // CHECK_CORE_AVX2_M32: #define __BMI2__ 1
 // CHECK_CORE_AVX2_M32: #define __BMI__ 1
 // CHECK_CORE_AVX2_M32: #define __F16C__ 1
 // CHECK_CORE_AVX2_M32: #define __FMA__ 1
+// CHECK_CORE_AVX2_M32: #define __HLE__ 1
 // CHECK_CORE_AVX2_M32: #define __LZCNT__ 1
 // CHECK_CORE_AVX2_M32: #define __MMX__ 1
 // CHECK_CORE_AVX2_M32: #define __PCLMUL__ 1
@@ -536,11 +539,14 @@
 // RUN:     -target i386-unknown-linux \
 // RUN:   | FileCheck %s -check-prefix=CHECK_CORE_AVX2_M64
 // CHECK_CORE_AVX2_M64: #define __AES__ 1
+// CHECK_CORE_AVX2_M64: #define __ATOMIC_HLE_ACQUIRE 65536
+// CHECK_CORE_AVX2_M64: #define __ATOMIC_HLE_RELEASE 131072
 // CHECK_CORE_AVX2_M64: #define __AVX__ 1
 // CHECK_CORE_AVX2_M64: #define __BMI2__ 1
 // CHECK_CORE_AVX2_M64: #define __BMI__ 1
 // CHECK_CORE_AVX2_M64: #define __F16C__ 1
 // CHECK_CORE_AVX2_M64: #define __FMA__ 1
+// CHECK_CORE_AVX2_M64: #define __HLE__ 1
 // CHECK_CORE_AVX2_M64: #define __LZCNT__ 1
 // CHECK_CORE_AVX2_M64: #define __MMX__ 1
 // CHECK_CORE_AVX2_M64: #define __PCLMUL__ 1
-------------- next part --------------
A non-text attachment was scrubbed...
Name: D441.3.patch
Type: text/x-patch
Size: 5230 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/cfe-commits/attachments/20130319/ccd2663a/attachment.bin>