[PATCH] Fix host processor identification for Sandy Bridge

[Benjamin Kramer]

On 11.03.2013, at 15:55, Aaron Ballman <aaron at aaronballman.com> wrote:

> This patch addresses PR15351 by explicitly checking for AVX support
> when getting the host processor information.  Not all Sandy Bridge
> processors support AVX (such as the Pentium-based ones), so I am
> checking explicitly for AVX support when deciding which processor to
> report.

Do newer CPUs have the same issue. It's certainly an issue if you have e.g. an Ivy Bridge on SP1-less Windows 7.

> I'm not entirely certain of how to make a lit test for this though, so
> suggestions are welcome.

Sadly, there isn't really a way to fake a CPU in lit.

> Index: lib/Support/Host.cpp
> ===================================================================
> --- lib/Support/Host.cpp	(revision 176803)
> +++ lib/Support/Host.cpp	(working copy)
> @@ -112,6 +112,16 @@
>  #endif
>  }
>  
> +static bool OSHasAVXSupport() {
> +#if defined(__GNUC__)
> +  int rEAX, rEDX;
> +  __asm__ ("xgetbv" : "=a" (rEAX), "=d" (rEDX) : "c" (0)); 
> +#elif defined(_MSC_VER)
> +  unsigned long long rEAX = _xgetbv(_XCR_XFEATURE_ENABLED_MASK);
> +#endif
> +  return (rEAX & 6) == 6;

What should happen if neither __GNUC__ nor _MSC_VER is set? return false?

- Ben

> +}
> +
>  static void DetectX86FamilyModel(unsigned EAX, unsigned &Family,
>                                   unsigned &Model) {
>    Family = (EAX >> 8) & 0xf; // Bits 8 - 11
> @@ -134,6 +144,10 @@
>    DetectX86FamilyModel(EAX, Family, Model);
>  
>    bool HasSSE3 = (ECX & 0x1);
> +  // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV 
> +  // indicates that the AVX registers will be saved and restored on context
> +  // switch, when we have full AVX support.
> +  bool HasAVX = (ECX & ((1 << 28) | (1 << 27))) != 0 && OSHasAVXSupport();
>    GetX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
>    bool Em64T = (EDX >> 29) & 0x1;
>  
> @@ -243,7 +257,9 @@
>        case 42: // Intel Core i7 processor. All processors are manufactured
>                 // using the 32 nm process.
>        case 45:
> -        return "corei7-avx";
> +        // Not all Sandy Bridge processors support AVX (such as the Pentium
> +        // versions instead of the i7 versions).
> +        return HasAVX ? "corei7-avx" : "corei7";
>  
>        // Ivy Bridge:
>        case 58: