[cfe-commits] [PATCH] Clean up and fix X86 features

[Eli Friedman]

On Thu, Nov 15, 2012 at 10:41 AM, Jung-uk Kim <jkim at freebsd.org> wrote:
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> [This is actually PR14344 but I was told to submit the patch here.
> Please see the PR14344 for the PR history.]
>
> I have an AMD Family 10h processor and I realized that LZCNT and
> POPCNT are not enabled by default.  Then, I looked at
> lib/Basic/Targets.cpp and found it needs some love (e.g., sync. with
> LLVM's X86.td). :-)
>
> Please see the attached patch.
>
> - - AMD Barcelona("amdfam10") and later processors have LZCNT and POPCNT
> instructions.
> - - AMD Piledriver("bdver2") and later processors have BMI, FMA, and
> F16C instructions.
> - - Intel Ivy Bridge("core-avx-i") and later processors have F16C
> instructions.
> - - Do not set SIMD sets (i.e., MMX, SSE3, and AVX) when they are
> implicitly set via higher instruction sets.
> - - Do not enable POPCNT instruction with SSE4* instruction sets as they
> are not part of the specifications nor uses SIMD registers. [1]
>
> Jung-uk Kim
>
> [1] It has little bit of history behind it.  AMD called them ABM and
> they added "-mabm" option to GCC, which enabled both LZCNT and POPCNT
> instructions.  OTOH, Intel implemented POPCNT first (Arrandale), then
> LZCNT later (upcoming Haswell).  Therefore, GCC had to separate the
> flag and added "-mpopcnt" and "-mlzcnt" (but kept "-mabm" for backward
> compatibility).

Tests are important here; please include the relevant changes for
clang/test/Preprocessor/predefined-arch-macros.c .

-Eli