[cfe-commits] r161333 - in /cfe/trunk: include/clang/Basic/BuiltinsMips.def test/CodeGen/builtins-mips.c
Simon Atanasyan
satanasyan at mips.com
Mon Aug 6 12:48:16 PDT 2012
Author: atanasyan
Date: Mon Aug 6 14:48:16 2012
New Revision: 161333
URL: http://llvm.org/viewvc/llvm-project?rev=161333&view=rev
Log:
Fix MIPS DSP Rev1 intrinsics memory properties.
The patch reviewed by Akira Hatanaka.
Modified:
cfe/trunk/include/clang/Basic/BuiltinsMips.def
cfe/trunk/test/CodeGen/builtins-mips.c
Modified: cfe/trunk/include/clang/Basic/BuiltinsMips.def
URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/Basic/BuiltinsMips.def?rev=161333&r1=161332&r2=161333&view=diff
==============================================================================
--- cfe/trunk/include/clang/Basic/BuiltinsMips.def (original)
+++ cfe/trunk/include/clang/Basic/BuiltinsMips.def Mon Aug 6 14:48:16 2012
@@ -15,38 +15,38 @@
// The format of this database matches clang/Basic/Builtins.def.
// Add/subtract with optional saturation
-BUILTIN(__builtin_mips_addu_qb, "V4ScV4ScV4Sc", "nc")
-BUILTIN(__builtin_mips_addu_s_qb, "V4ScV4ScV4Sc", "nc")
-BUILTIN(__builtin_mips_subu_qb, "V4ScV4ScV4Sc", "nc")
-BUILTIN(__builtin_mips_subu_s_qb, "V4ScV4ScV4Sc", "nc")
-
-BUILTIN(__builtin_mips_addq_ph, "V2sV2sV2s", "nc")
-BUILTIN(__builtin_mips_addq_s_ph, "V2sV2sV2s", "nc")
-BUILTIN(__builtin_mips_subq_ph, "V2sV2sV2s", "nc")
-BUILTIN(__builtin_mips_subq_s_ph, "V2sV2sV2s", "nc")
+BUILTIN(__builtin_mips_addu_qb, "V4ScV4ScV4Sc", "n")
+BUILTIN(__builtin_mips_addu_s_qb, "V4ScV4ScV4Sc", "n")
+BUILTIN(__builtin_mips_subu_qb, "V4ScV4ScV4Sc", "n")
+BUILTIN(__builtin_mips_subu_s_qb, "V4ScV4ScV4Sc", "n")
+
+BUILTIN(__builtin_mips_addq_ph, "V2sV2sV2s", "n")
+BUILTIN(__builtin_mips_addq_s_ph, "V2sV2sV2s", "n")
+BUILTIN(__builtin_mips_subq_ph, "V2sV2sV2s", "n")
+BUILTIN(__builtin_mips_subq_s_ph, "V2sV2sV2s", "n")
BUILTIN(__builtin_mips_madd, "LLiLLiii", "nc")
BUILTIN(__builtin_mips_maddu, "LLiLLiUiUi", "nc")
BUILTIN(__builtin_mips_msub, "LLiLLiii", "nc")
BUILTIN(__builtin_mips_msubu, "LLiLLiUiUi", "nc")
-BUILTIN(__builtin_mips_addq_s_w, "iii", "nc")
-BUILTIN(__builtin_mips_subq_s_w, "iii", "nc")
+BUILTIN(__builtin_mips_addq_s_w, "iii", "n")
+BUILTIN(__builtin_mips_subq_s_w, "iii", "n")
-BUILTIN(__builtin_mips_addsc, "iii", "nc")
-BUILTIN(__builtin_mips_addwc, "iii", "nc")
+BUILTIN(__builtin_mips_addsc, "iii", "n")
+BUILTIN(__builtin_mips_addwc, "iii", "n")
BUILTIN(__builtin_mips_modsub, "iii", "nc")
BUILTIN(__builtin_mips_raddu_w_qb, "iV4Sc", "nc")
-BUILTIN(__builtin_mips_absq_s_ph, "V2sV2s", "nc")
-BUILTIN(__builtin_mips_absq_s_w, "ii", "nc")
+BUILTIN(__builtin_mips_absq_s_ph, "V2sV2s", "n")
+BUILTIN(__builtin_mips_absq_s_w, "ii", "n")
BUILTIN(__builtin_mips_precrq_qb_ph, "V4ScV2sV2s", "nc")
-BUILTIN(__builtin_mips_precrqu_s_qb_ph, "V4ScV2sV2s", "nc")
+BUILTIN(__builtin_mips_precrqu_s_qb_ph, "V4ScV2sV2s", "n")
BUILTIN(__builtin_mips_precrq_ph_w, "V2sii", "nc")
-BUILTIN(__builtin_mips_precrq_rs_ph_w, "V2sii", "nc")
+BUILTIN(__builtin_mips_precrq_rs_ph_w, "V2sii", "n")
BUILTIN(__builtin_mips_preceq_w_phl, "iV2s", "nc")
BUILTIN(__builtin_mips_preceq_w_phr, "iV2s", "nc")
BUILTIN(__builtin_mips_precequ_ph_qbl, "V2sV4Sc", "nc")
@@ -58,26 +58,26 @@
BUILTIN(__builtin_mips_preceu_ph_qbla, "V2sV4Sc", "nc")
BUILTIN(__builtin_mips_preceu_ph_qbra, "V2sV4Sc", "nc")
-BUILTIN(__builtin_mips_shll_qb, "V4ScV4Sci", "nc")
+BUILTIN(__builtin_mips_shll_qb, "V4ScV4Sci", "n")
BUILTIN(__builtin_mips_shrl_qb, "V4ScV4Sci", "nc")
-BUILTIN(__builtin_mips_shll_ph, "V2sV2si", "nc")
-BUILTIN(__builtin_mips_shll_s_ph, "V2sV2si", "nc")
+BUILTIN(__builtin_mips_shll_ph, "V2sV2si", "n")
+BUILTIN(__builtin_mips_shll_s_ph, "V2sV2si", "n")
BUILTIN(__builtin_mips_shra_ph, "V2sV2si", "nc")
BUILTIN(__builtin_mips_shra_r_ph, "V2sV2si", "nc")
-BUILTIN(__builtin_mips_shll_s_w, "iii", "nc")
+BUILTIN(__builtin_mips_shll_s_w, "iii", "n")
BUILTIN(__builtin_mips_shra_r_w, "iii", "nc")
BUILTIN(__builtin_mips_shilo, "LLiLLii", "nc")
-BUILTIN(__builtin_mips_muleu_s_ph_qbl, "V2sV4ScV2s", "nc")
-BUILTIN(__builtin_mips_muleu_s_ph_qbr, "V2sV4ScV2s", "nc")
-BUILTIN(__builtin_mips_mulq_rs_ph, "V2sV2sV2s", "nc")
-BUILTIN(__builtin_mips_muleq_s_w_phl, "iV2sV2s", "nc")
-BUILTIN(__builtin_mips_muleq_s_w_phr, "iV2sV2s", "nc")
-BUILTIN(__builtin_mips_mulsaq_s_w_ph, "LLiLLiV2sV2s", "nc")
-BUILTIN(__builtin_mips_maq_s_w_phl, "LLiLLiV2sV2s", "nc")
-BUILTIN(__builtin_mips_maq_s_w_phr, "LLiLLiV2sV2s", "nc")
-BUILTIN(__builtin_mips_maq_sa_w_phl, "LLiLLiV2sV2s", "nc")
-BUILTIN(__builtin_mips_maq_sa_w_phr, "LLiLLiV2sV2s", "nc")
+BUILTIN(__builtin_mips_muleu_s_ph_qbl, "V2sV4ScV2s", "n")
+BUILTIN(__builtin_mips_muleu_s_ph_qbr, "V2sV4ScV2s", "n")
+BUILTIN(__builtin_mips_mulq_rs_ph, "V2sV2sV2s", "n")
+BUILTIN(__builtin_mips_muleq_s_w_phl, "iV2sV2s", "n")
+BUILTIN(__builtin_mips_muleq_s_w_phr, "iV2sV2s", "n")
+BUILTIN(__builtin_mips_mulsaq_s_w_ph, "LLiLLiV2sV2s", "n")
+BUILTIN(__builtin_mips_maq_s_w_phl, "LLiLLiV2sV2s", "n")
+BUILTIN(__builtin_mips_maq_s_w_phr, "LLiLLiV2sV2s", "n")
+BUILTIN(__builtin_mips_maq_sa_w_phl, "LLiLLiV2sV2s", "n")
+BUILTIN(__builtin_mips_maq_sa_w_phr, "LLiLLiV2sV2s", "n")
BUILTIN(__builtin_mips_mult, "LLiii", "nc")
BUILTIN(__builtin_mips_multu, "LLiUiUi", "nc")
@@ -85,39 +85,39 @@
BUILTIN(__builtin_mips_dpau_h_qbr, "LLiLLiV4ScV4Sc", "nc")
BUILTIN(__builtin_mips_dpsu_h_qbl, "LLiLLiV4ScV4Sc", "nc")
BUILTIN(__builtin_mips_dpsu_h_qbr, "LLiLLiV4ScV4Sc", "nc")
-BUILTIN(__builtin_mips_dpaq_s_w_ph, "LLiLLiV2sV2s", "nc")
-BUILTIN(__builtin_mips_dpsq_s_w_ph, "LLiLLiV2sV2s", "nc")
-BUILTIN(__builtin_mips_dpaq_sa_l_w, "LLiLLiii", "nc")
-BUILTIN(__builtin_mips_dpsq_sa_l_w, "LLiLLiii", "nc")
-
-BUILTIN(__builtin_mips_cmpu_eq_qb, "vV4ScV4Sc", "nc")
-BUILTIN(__builtin_mips_cmpu_lt_qb, "vV4ScV4Sc", "nc")
-BUILTIN(__builtin_mips_cmpu_le_qb, "vV4ScV4Sc", "nc")
-BUILTIN(__builtin_mips_cmpgu_eq_qb, "iV4ScV4Sc", "nc")
-BUILTIN(__builtin_mips_cmpgu_lt_qb, "iV4ScV4Sc", "nc")
-BUILTIN(__builtin_mips_cmpgu_le_qb, "iV4ScV4Sc", "nc")
-BUILTIN(__builtin_mips_cmp_eq_ph, "vV2sV2s", "nc")
-BUILTIN(__builtin_mips_cmp_lt_ph, "vV2sV2s", "nc")
-BUILTIN(__builtin_mips_cmp_le_ph, "vV2sV2s", "nc")
-
-BUILTIN(__builtin_mips_extr_s_h, "iLLii", "nc")
-BUILTIN(__builtin_mips_extr_w, "iLLii", "nc")
-BUILTIN(__builtin_mips_extr_rs_w, "iLLii", "nc")
-BUILTIN(__builtin_mips_extr_r_w, "iLLii", "nc")
-BUILTIN(__builtin_mips_extp, "iLLii", "nc")
-BUILTIN(__builtin_mips_extpdp, "iLLii", "nc")
-
-BUILTIN(__builtin_mips_wrdsp, "viIi", "nc")
-BUILTIN(__builtin_mips_rddsp, "iIi", "nc")
-BUILTIN(__builtin_mips_insv, "iii", "nc")
+BUILTIN(__builtin_mips_dpaq_s_w_ph, "LLiLLiV2sV2s", "n")
+BUILTIN(__builtin_mips_dpsq_s_w_ph, "LLiLLiV2sV2s", "n")
+BUILTIN(__builtin_mips_dpaq_sa_l_w, "LLiLLiii", "n")
+BUILTIN(__builtin_mips_dpsq_sa_l_w, "LLiLLiii", "n")
+
+BUILTIN(__builtin_mips_cmpu_eq_qb, "vV4ScV4Sc", "n")
+BUILTIN(__builtin_mips_cmpu_lt_qb, "vV4ScV4Sc", "n")
+BUILTIN(__builtin_mips_cmpu_le_qb, "vV4ScV4Sc", "n")
+BUILTIN(__builtin_mips_cmpgu_eq_qb, "iV4ScV4Sc", "n")
+BUILTIN(__builtin_mips_cmpgu_lt_qb, "iV4ScV4Sc", "n")
+BUILTIN(__builtin_mips_cmpgu_le_qb, "iV4ScV4Sc", "n")
+BUILTIN(__builtin_mips_cmp_eq_ph, "vV2sV2s", "n")
+BUILTIN(__builtin_mips_cmp_lt_ph, "vV2sV2s", "n")
+BUILTIN(__builtin_mips_cmp_le_ph, "vV2sV2s", "n")
+
+BUILTIN(__builtin_mips_extr_s_h, "iLLii", "n")
+BUILTIN(__builtin_mips_extr_w, "iLLii", "n")
+BUILTIN(__builtin_mips_extr_rs_w, "iLLii", "n")
+BUILTIN(__builtin_mips_extr_r_w, "iLLii", "n")
+BUILTIN(__builtin_mips_extp, "iLLii", "n")
+BUILTIN(__builtin_mips_extpdp, "iLLii", "n")
+
+BUILTIN(__builtin_mips_wrdsp, "viIi", "n")
+BUILTIN(__builtin_mips_rddsp, "iIi", "n")
+BUILTIN(__builtin_mips_insv, "iii", "n")
BUILTIN(__builtin_mips_bitrev, "ii", "nc")
BUILTIN(__builtin_mips_packrl_ph, "V2sV2sV2s", "nc")
BUILTIN(__builtin_mips_repl_qb, "V4Sci", "nc")
BUILTIN(__builtin_mips_repl_ph, "V2si", "nc")
-BUILTIN(__builtin_mips_pick_qb, "V4ScV4ScV4Sc", "nc")
-BUILTIN(__builtin_mips_pick_ph, "V2sV2sV2s", "nc")
-BUILTIN(__builtin_mips_mthlip, "LLiLLii", "nc")
-BUILTIN(__builtin_mips_bposge32, "i", "nc")
+BUILTIN(__builtin_mips_pick_qb, "V4ScV4ScV4Sc", "n")
+BUILTIN(__builtin_mips_pick_ph, "V2sV2sV2s", "n")
+BUILTIN(__builtin_mips_mthlip, "LLiLLii", "n")
+BUILTIN(__builtin_mips_bposge32, "i", "n")
BUILTIN(__builtin_mips_lbux, "iv*i", "n")
BUILTIN(__builtin_mips_lhx, "iv*i", "n")
BUILTIN(__builtin_mips_lwx, "iv*i", "n")
Modified: cfe/trunk/test/CodeGen/builtins-mips.c
URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/builtins-mips.c?rev=161333&r1=161332&r2=161333&view=diff
==============================================================================
--- cfe/trunk/test/CodeGen/builtins-mips.c (original)
+++ cfe/trunk/test/CodeGen/builtins-mips.c Mon Aug 6 14:48:16 2012
@@ -1,6 +1,6 @@
// REQUIRES: mips-registered-target
-// RUN: %clang_cc1 -triple mips-unknown-linux-gnu -emit-llvm -o %t %s
-// RUN: not grep __builtin %t
+// RUN: %clang_cc1 -triple mips-unknown-linux-gnu -emit-llvm %s -o - \
+// RUN: | FileCheck %s
typedef int q31;
typedef int i32;
@@ -23,206 +23,302 @@
v4i8_a = (v4i8) {1, 2, 3, 0xFF};
v4i8_b = (v4i8) {2, 4, 6, 8};
v4i8_r = __builtin_mips_addu_qb(v4i8_a, v4i8_b);
+// CHECK: call <4 x i8> @llvm.mips.addu.qb
v4i8_r = __builtin_mips_addu_s_qb(v4i8_a, v4i8_b);
+// CHECK: call <4 x i8> @llvm.mips.addu.s.qb
v4i8_r = __builtin_mips_subu_qb(v4i8_a, v4i8_b);
+// CHECK: call <4 x i8> @llvm.mips.subu.qb
v4i8_r = __builtin_mips_subu_s_qb(v4i8_a, v4i8_b);
+// CHECK: call <4 x i8> @llvm.mips.subu.s.qb
v2q15_a = (v2q15) {0x0000, 0x8000};
v2q15_b = (v2q15) {0x8000, 0x8000};
v2q15_r = __builtin_mips_addq_ph(v2q15_a, v2q15_b);
+// CHECK: call <2 x i16> @llvm.mips.addq.ph
v2q15_r = __builtin_mips_addq_s_ph(v2q15_a, v2q15_b);
+// CHECK: call <2 x i16> @llvm.mips.addq.s.ph
v2q15_r = __builtin_mips_subq_ph(v2q15_a, v2q15_b);
+// CHECK: call <2 x i16> @llvm.mips.subq.ph
v2q15_r = __builtin_mips_subq_s_ph(v2q15_a, v2q15_b);
+// CHECK: call <2 x i16> @llvm.mips.subq.s.ph
a64_a = 0x12345678;
i32_b = 0x80000000;
i32_c = 0x11112222;
a64_r = __builtin_mips_madd(a64_a, i32_b, i32_c);
+// CHECK: call i64 @llvm.mips.madd
a64_a = 0x12345678;
ui32_b = 0x80000000;
ui32_c = 0x11112222;
a64_r = __builtin_mips_maddu(a64_a, ui32_b, ui32_c);
+// CHECK: call i64 @llvm.mips.maddu
a64_a = 0x12345678;
i32_b = 0x80000000;
i32_c = 0x11112222;
a64_r = __builtin_mips_msub(a64_a, i32_b, i32_c);
+// CHECK: call i64 @llvm.mips.msub
a64_a = 0x12345678;
ui32_b = 0x80000000;
ui32_c = 0x11112222;
a64_r = __builtin_mips_msubu(a64_a, ui32_b, ui32_c);
+// CHECK: call i64 @llvm.mips.msubu
q31_a = 0x12345678;
q31_b = 0x7FFFFFFF;
q31_r = __builtin_mips_addq_s_w(q31_a, q31_b);
+// CHECK: call i32 @llvm.mips.addq.s.w
q31_r = __builtin_mips_subq_s_w(q31_a, q31_b);
+// CHECK: call i32 @llvm.mips.subq.s.w
i32_a = 0xFFFFFFFF;
i32_b = 1;
i32_r = __builtin_mips_addsc(i32_a, i32_b);
+// CHECK: call i32 @llvm.mips.addsc
i32_a = 0;
i32_b = 1;
i32_r = __builtin_mips_addwc(i32_a, i32_b);
+// CHECK: call i32 @llvm.mips.addwc
i32_a = 20;
i32_b = 0x1402;
i32_r = __builtin_mips_modsub(i32_a, i32_b);
+// CHECK: call i32 @llvm.mips.modsub
v4i8_a = (v4i8) {1, 2, 3, 4};
i32_r = __builtin_mips_raddu_w_qb(v4i8_a);
+// CHECK: call i32 @llvm.mips.raddu.w.qb
v2q15_a = (v2q15) {0xFFFF, 0x8000};
v2q15_r = __builtin_mips_absq_s_ph(v2q15_a);
+// CHECK: call <2 x i16> @llvm.mips.absq.s.ph
q31_a = 0x80000000;
q31_r = __builtin_mips_absq_s_w(q31_a);
+// CHECK: call i32 @llvm.mips.absq.s.w
v2q15_a = (v2q15) {0x1234, 0x5678};
v2q15_b = (v2q15) {0x1111, 0x2222};
v4i8_r = __builtin_mips_precrq_qb_ph(v2q15_a, v2q15_b);
+// CHECK: call <4 x i8> @llvm.mips.precrq.qb.ph
v2q15_a = (v2q15) {0x7F79, 0xFFFF};
v2q15_b = (v2q15) {0x7F81, 0x2000};
v4i8_r = __builtin_mips_precrqu_s_qb_ph(v2q15_a, v2q15_b);
+// CHECK: call <4 x i8> @llvm.mips.precrqu.s.qb.ph
q31_a = 0x12345678;
q31_b = 0x11112222;
v2q15_r = __builtin_mips_precrq_ph_w(q31_a, q31_b);
+// CHECK: call <2 x i16> @llvm.mips.precrq.ph.w
q31_a = 0x7000FFFF;
q31_b = 0x80000000;
v2q15_r = __builtin_mips_precrq_rs_ph_w(q31_a, q31_b);
+// CHECK: call <2 x i16> @llvm.mips.precrq.rs.ph.w
v2q15_a = (v2q15) {0x1234, 0x5678};
q31_r = __builtin_mips_preceq_w_phl(v2q15_a);
+// CHECK: call i32 @llvm.mips.preceq.w.phl
q31_r = __builtin_mips_preceq_w_phr(v2q15_a);
+// CHECK: call i32 @llvm.mips.preceq.w.phr
v4i8_a = (v4i8) {0x12, 0x34, 0x56, 0x78};
v2q15_r = __builtin_mips_precequ_ph_qbl(v4i8_a);
+// CHECK: call <2 x i16> @llvm.mips.precequ.ph.qbl
v2q15_r = __builtin_mips_precequ_ph_qbr(v4i8_a);
+// CHECK: call <2 x i16> @llvm.mips.precequ.ph.qbr
v2q15_r = __builtin_mips_precequ_ph_qbla(v4i8_a);
+// CHECK: call <2 x i16> @llvm.mips.precequ.ph.qbla
v2q15_r = __builtin_mips_precequ_ph_qbra(v4i8_a);
+// CHECK: call <2 x i16> @llvm.mips.precequ.ph.qbra
v2q15_r = __builtin_mips_preceu_ph_qbl(v4i8_a);
+// CHECK: call <2 x i16> @llvm.mips.preceu.ph.qbl
v2q15_r = __builtin_mips_preceu_ph_qbr(v4i8_a);
+// CHECK: call <2 x i16> @llvm.mips.preceu.ph.qbr
v2q15_r = __builtin_mips_preceu_ph_qbla(v4i8_a);
+// CHECK: call <2 x i16> @llvm.mips.preceu.ph.qbla
v2q15_r = __builtin_mips_preceu_ph_qbra(v4i8_a);
+// CHECK: call <2 x i16> @llvm.mips.preceu.ph.qbra
v4i8_a = (v4i8) {1, 2, 3, 4};
v4i8_r = __builtin_mips_shll_qb(v4i8_a, 2);
+// CHECK: call <4 x i8> @llvm.mips.shll.qb
v4i8_a = (v4i8) {128, 64, 32, 16};
v4i8_r = __builtin_mips_shrl_qb(v4i8_a, 2);
+// CHECK: call <4 x i8> @llvm.mips.shrl.qb
v2q15_a = (v2q15) {0x0001, 0x8000};
v2q15_r = __builtin_mips_shll_ph(v2q15_a, 2);
+// CHECK: call <2 x i16> @llvm.mips.shll.ph
v2q15_r = __builtin_mips_shll_s_ph(v2q15_a, 2);
+// CHECK: call <2 x i16> @llvm.mips.shll.s.ph
v2q15_a = (v2q15) {0x7FFF, 0x8000};
v2q15_r = __builtin_mips_shra_ph(v2q15_a, 2);
+// CHECK: call <2 x i16> @llvm.mips.shra.ph
v2q15_r = __builtin_mips_shra_r_ph(v2q15_a, 2);
+// CHECK: call <2 x i16> @llvm.mips.shra.r.ph
q31_a = 0x70000000;
q31_r = __builtin_mips_shll_s_w(q31_a, 2);
+// CHECK: call i32 @llvm.mips.shll.s.w
q31_a = 0x7FFFFFFF;
q31_r = __builtin_mips_shra_r_w(q31_a, 2);
+// CHECK: call i32 @llvm.mips.shra.r.w
a64_a = 0x1234567887654321LL;
a64_r = __builtin_mips_shilo(a64_a, -8);
+// CHECK: call i64 @llvm.mips.shilo
v4i8_a = (v4i8) {0x1, 0x3, 0x5, 0x7};
v2q15_b = (v2q15) {0x1234, 0x5678};
v2q15_r = __builtin_mips_muleu_s_ph_qbl(v4i8_a, v2q15_b);
+// CHECK: call <2 x i16> @llvm.mips.muleu.s.ph.qbl
v2q15_r = __builtin_mips_muleu_s_ph_qbr(v4i8_a, v2q15_b);
+// CHECK: call <2 x i16> @llvm.mips.muleu.s.ph.qbr
v2q15_a = (v2q15) {0x7FFF, 0x8000};
v2q15_b = (v2q15) {0x7FFF, 0x8000};
v2q15_r = __builtin_mips_mulq_rs_ph(v2q15_a, v2q15_b);
+// CHECK: call <2 x i16> @llvm.mips.mulq.rs.ph
v2q15_a = (v2q15) {0x1234, 0x8000};
v2q15_b = (v2q15) {0x5678, 0x8000};
q31_r = __builtin_mips_muleq_s_w_phl(v2q15_a, v2q15_b);
+// CHECK: call i32 @llvm.mips.muleq.s.w.phl
q31_r = __builtin_mips_muleq_s_w_phr(v2q15_a, v2q15_b);
+// CHECK: call i32 @llvm.mips.muleq.s.w.phr
a64_a = 0;
v2q15_a = (v2q15) {0x0001, 0x8000};
v2q15_b = (v2q15) {0x0002, 0x8000};
a64_r = __builtin_mips_mulsaq_s_w_ph(a64_a, v2q15_b, v2q15_c);
+// CHECK: call i64 @llvm.mips.mulsaq.s.w.ph
a64_a = 0;
v2q15_b = (v2q15) {0x0001, 0x8000};
v2q15_c = (v2q15) {0x0002, 0x8000};
a64_r = __builtin_mips_maq_s_w_phl(a64_a, v2q15_b, v2q15_c);
+// CHECK: call i64 @llvm.mips.maq.s.w.phl
a64_r = __builtin_mips_maq_s_w_phr(a64_a, v2q15_b, v2q15_c);
+// CHECK: call i64 @llvm.mips.maq.s.w.phr
a64_a = 0x7FFFFFF0;
a64_r = __builtin_mips_maq_sa_w_phl(a64_a, v2q15_b, v2q15_c);
+// CHECK: call i64 @llvm.mips.maq.sa.w.phl
a64_r = __builtin_mips_maq_sa_w_phr(a64_a, v2q15_b, v2q15_c);
+// CHECK: call i64 @llvm.mips.maq.sa.w.phr
i32_a = 0x80000000;
i32_b = 0x11112222;
a64_r = __builtin_mips_mult(i32_a, i32_b);
+// CHECK: call i64 @llvm.mips.mult
ui32_a = 0x80000000;
ui32_b = 0x11112222;
a64_r = __builtin_mips_multu(ui32_a, ui32_b);
+// CHECK: call i64 @llvm.mips.multu
a64_a = 0;
v4i8_b = (v4i8) {1, 2, 3, 4};
v4i8_c = (v4i8) {4, 5, 6, 7};
a64_r = __builtin_mips_dpau_h_qbl(a64_a, v4i8_b, v4i8_c);
+// CHECK: call i64 @llvm.mips.dpau.h.qbl
a64_r = __builtin_mips_dpau_h_qbr(a64_a, v4i8_b, v4i8_c);
+// CHECK: call i64 @llvm.mips.dpau.h.qbr
a64_r = __builtin_mips_dpsu_h_qbl(a64_a, v4i8_b, v4i8_c);
+// CHECK: call i64 @llvm.mips.dpsu.h.qbl
a64_r = __builtin_mips_dpsu_h_qbr(a64_a, v4i8_b, v4i8_c);
+// CHECK: call i64 @llvm.mips.dpsu.h.qbr
a64_a = 0;
v2q15_b = (v2q15) {0x0001, 0x8000};
v2q15_c = (v2q15) {0x0002, 0x8000};
a64_r = __builtin_mips_dpaq_s_w_ph(a64_a, v2q15_b, v2q15_c);
+// CHECK: call i64 @llvm.mips.dpaq.s.w.ph
a64_r = __builtin_mips_dpsq_s_w_ph(a64_a, v2q15_b, v2q15_c);
+// CHECK: call i64 @llvm.mips.dpsq.s.w.ph
a64_a = 0;
q31_b = 0x80000000;
q31_c = 0x80000000;
a64_r = __builtin_mips_dpaq_sa_l_w(a64_a, q31_b, q31_c);
+// CHECK: call i64 @llvm.mips.dpaq.sa.l.w
a64_r = __builtin_mips_dpsq_sa_l_w(a64_a, q31_b, q31_c);
+// CHECK: call i64 @llvm.mips.dpsq.sa.l.w
v4i8_a = (v4i8) {1, 4, 10, 8};
v4i8_b = (v4i8) {1, 2, 100, 8};
__builtin_mips_cmpu_eq_qb(v4i8_a, v4i8_b);
+// CHECK: call void @llvm.mips.cmpu.eq.qb
__builtin_mips_cmpu_lt_qb(v4i8_a, v4i8_b);
+// CHECK: call void @llvm.mips.cmpu.lt.qb
__builtin_mips_cmpu_le_qb(v4i8_a, v4i8_b);
+// CHECK: call void @llvm.mips.cmpu.le.qb
i32_r = __builtin_mips_cmpgu_eq_qb(v4i8_a, v4i8_b);
+// CHECK: call i32 @llvm.mips.cmpgu.eq.qb
i32_r = __builtin_mips_cmpgu_lt_qb(v4i8_a, v4i8_b);
+// CHECK: call i32 @llvm.mips.cmpgu.lt.qb
i32_r = __builtin_mips_cmpgu_le_qb(v4i8_a, v4i8_b);
+// CHECK: call i32 @llvm.mips.cmpgu.le.qb
v2q15_a = (v2q15) {0x1111, 0x1234};
v2q15_b = (v2q15) {0x4444, 0x1234};
__builtin_mips_cmp_eq_ph(v2q15_a, v2q15_b);
+// CHECK: call void @llvm.mips.cmp.eq.ph
__builtin_mips_cmp_lt_ph(v2q15_a, v2q15_b);
+// CHECK: call void @llvm.mips.cmp.lt.ph
__builtin_mips_cmp_le_ph(v2q15_a, v2q15_b);
+// CHECK: call void @llvm.mips.cmp.le.ph
a64_a = 0xFFFFF81230000000LL;
i32_r = __builtin_mips_extr_s_h(a64_a, 4);
+// CHECK: call i32 @llvm.mips.extr.s.h
a64_a = 0x8123456712345678LL;
i32_r = __builtin_mips_extr_w(a64_a, 31);
+// CHECK: call i32 @llvm.mips.extr.w
i32_r = __builtin_mips_extr_rs_w(a64_a, 31);
+// CHECK: call i32 @llvm.mips.extr.rs.w
i32_r = __builtin_mips_extr_r_w(a64_a, 31);
+// CHECK: call i32 @llvm.mips.extr.r.w
a64_a = 0x1234567887654321LL;
i32_r = __builtin_mips_extp(a64_a, 3);
+// CHECK: call i32 @llvm.mips.extp
a64_a = 0x123456789ABCDEF0LL;
i32_r = __builtin_mips_extpdp(a64_a, 7);
+// CHECK: call i32 @llvm.mips.extpdp
__builtin_mips_wrdsp(2052, 3);
+// CHECK: call void @llvm.mips.wrdsp
i32_r = __builtin_mips_rddsp(3);
+// CHECK: call i32 @llvm.mips.rddsp
i32_a = 0xFFFFFFFF;
i32_b = 0x12345678;
__builtin_mips_wrdsp((16<<7) + 4, 3);
+// CHECK: call void @llvm.mips.wrdsp
i32_r = __builtin_mips_insv(i32_a, i32_b);
+// CHECK: call i32 @llvm.mips.insv
i32_a = 0x1234;
i32_r = __builtin_mips_bitrev(i32_a);
+// CHECK: call i32 @llvm.mips.bitrev
v2q15_a = (v2q15) {0x1111, 0x2222};
v2q15_b = (v2q15) {0x3333, 0x4444};
v2q15_r = __builtin_mips_packrl_ph(v2q15_a, v2q15_b);
+// CHECK: call <2 x i16> @llvm.mips.packrl.ph
i32_a = 100;
v4i8_r = __builtin_mips_repl_qb(i32_a);
+// CHECK: call <4 x i8> @llvm.mips.repl.qb
i32_a = 0x1234;
v2q15_r = __builtin_mips_repl_ph(i32_a);
+// CHECK: call <2 x i16> @llvm.mips.repl.ph
v4i8_a = (v4i8) {1, 4, 10, 8};
v4i8_b = (v4i8) {1, 2, 100, 8};
__builtin_mips_cmpu_eq_qb(v4i8_a, v4i8_b);
+// CHECK: call void @llvm.mips.cmpu.eq.qb
v4i8_r = __builtin_mips_pick_qb(v4i8_a, v4i8_b);
+// CHECK: call <4 x i8> @llvm.mips.pick.qb
v2q15_a = (v2q15) {0x1111, 0x1234};
v2q15_b = (v2q15) {0x4444, 0x1234};
__builtin_mips_cmp_eq_ph(v2q15_a, v2q15_b);
+// CHECK: call void @llvm.mips.cmp.eq.ph
v2q15_r = __builtin_mips_pick_ph(v2q15_a, v2q15_b);
+// CHECK: call <2 x i16> @llvm.mips.pick.ph
a64_a = 0x1234567887654321LL;
i32_b = 0x11112222;
__builtin_mips_wrdsp(0, 1);
+// CHECK: call void @llvm.mips.wrdsp
a64_r = __builtin_mips_mthlip(a64_a, i32_b);
+// CHECK: call i64 @llvm.mips.mthlip
i32_r = __builtin_mips_bposge32();
+// CHECK: call i32 @llvm.mips.bposge32
char array_a[100];
i32_r = __builtin_mips_lbux(array_a, 20);
+// CHECK: call i32 @llvm.mips.lbux
short array_b[100];
i32_r = __builtin_mips_lhx(array_b, 20);
+// CHECK: call i32 @llvm.mips.lhx
int array_c[100];
i32_r = __builtin_mips_lwx(array_c, 20);
+// CHECK: call i32 @llvm.mips.lwx
}
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