[cfe-commits] r153921 - in /cfe/trunk: lib/Basic/Targets.cpp test/CodeGen/mips-constraint-regs.c

[Eric Christopher]

Author: echristo
Date: Mon Apr  2 20:16:32 2012
New Revision: 153921

URL: http://llvm.org/viewvc/llvm-project?rev=153921&view=rev
Log:
Add more constraint registers for mips.

Patch by Jack Carter. Testcase cleanup by me.

Added:
    cfe/trunk/test/CodeGen/mips-constraint-regs.c
Modified:
    cfe/trunk/lib/Basic/Targets.cpp

Modified: cfe/trunk/lib/Basic/Targets.cpp
URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Basic/Targets.cpp?rev=153921&r1=153920&r2=153921&view=diff
==============================================================================
--- cfe/trunk/lib/Basic/Targets.cpp (original)
+++ cfe/trunk/lib/Basic/Targets.cpp Mon Apr  2 20:16:32 2012
@@ -3522,6 +3522,9 @@
     case 'd': // Equivalent to "r" unless generating MIPS16 code.
     case 'y': // Equivalent to "r", backwards compatibility only.
     case 'f': // floating-point registers.
+    case 'c': // $25 for indirect jumps
+    case 'l': // lo register
+    case 'x': // hilo register pair
       Info.setAllowsRegister();
       return true;
     }

Added: cfe/trunk/test/CodeGen/mips-constraint-regs.c
URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/mips-constraint-regs.c?rev=153921&view=auto
==============================================================================
--- cfe/trunk/test/CodeGen/mips-constraint-regs.c (added)
+++ cfe/trunk/test/CodeGen/mips-constraint-regs.c Mon Apr  2 20:16:32 2012
@@ -0,0 +1,44 @@
+// RUN: %clang -target mipsel-unknown-linux -ccc-clang-archs mipsel -S -o - -emit-llvm %s
+
+// This checks that the frontend will accept inline asm constraints
+// c', 'l' and 'x'. Semantic checking will happen in the
+// llvm backend. Any bad constraint letters will cause the frontend to
+// error out.
+
+int main()
+{
+  // 'c': 16 bit address register for Mips16, GPR for all others
+  // I am using 'c' to constrain both the target and one of the source
+  // registers. We are looking for syntactical correctness.
+  int __s, __v = 17;
+  int __t;
+  __asm__ __volatile__(
+      "addi %0,%1,%2 \n\t\t"
+      : "=c" (__t)
+        : "c" (__s), "I" (__v));
+
+  // 'l': lo register
+  // We are making it clear that destination register is lo with the
+  // use of the 'l' constraint ("=l").
+  int i_temp = 44;
+  int i_result;
+  __asm__ __volatile__(
+      "mtlo %1 \n\t\t"
+      : "=l" (i_result)
+        : "r" (i_temp)
+          : "lo");
+
+  // 'x': Combined lo/hi registers
+  // We are specifying that destination registers are the hi/lo pair with the
+  // use of the 'x' constraint ("=x").
+  int i_hi = 3;
+  int i_lo = 2;
+  long long ll_result = 0;
+  __asm__ __volatile__(
+      "mthi %1 \n\t\t"
+      "mtlo %2 \n\t\t"
+      : "=x" (ll_result)
+        : "r" (i_hi), "r" (i_lo)
+          : );
+  return 0;
+}