[cfe-commits] r146862 - in /cfe/trunk: lib/Headers/avx2intrin.h test/CodeGen/avx2-builtins.c

[Craig Topper]

Author: ctopper
Date: Mon Dec 19 03:03:48 2011
New Revision: 146862

URL: http://llvm.org/viewvc/llvm-project?rev=146862&view=rev
Log:
Add AVX2 intrinsics for and, andn, or, and xor.

Modified:
    cfe/trunk/lib/Headers/avx2intrin.h
    cfe/trunk/test/CodeGen/avx2-builtins.c

Modified: cfe/trunk/lib/Headers/avx2intrin.h
URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Headers/avx2intrin.h?rev=146862&r1=146861&r2=146862&view=diff
==============================================================================
--- cfe/trunk/lib/Headers/avx2intrin.h (original)
+++ cfe/trunk/lib/Headers/avx2intrin.h Mon Dec 19 03:03:48 2011
@@ -124,6 +124,24 @@
   (__m256i)__builtin_ia32_palignr256((__v32qi)__a, (__v32qi)__b, (n)); })
 
 static __inline__ __m256i __attribute__((__always_inline__, __nodebug__))
+_mm256_and_si256(__m256i a, __m256i b)
+{
+  return a & b;
+}
+
+static __inline__ __m256i __attribute__((__always_inline__, __nodebug__))
+_mm256_andnot_si256(__m256i a, __m256i b)
+{
+  return ~a & b;
+}
+
+static __inline__ __m256i __attribute__((__always_inline__, __nodebug__))
+_mm256_or_si256(__m256i a, __m256i b)
+{
+  return a | b;
+}
+
+static __inline__ __m256i __attribute__((__always_inline__, __nodebug__))
 _mm256_sub_epi8(__m256i a, __m256i b)
 {
   return (__m256i)((__v32qi)a - (__v32qi)b);
@@ -171,3 +189,8 @@
   return (__m256i)__builtin_ia32_psubusw256((__v16hi)a, (__v16hi)b);
 }
 
+static __inline__ __m256i __attribute__((__always_inline__, __nodebug__))
+_mm256_xor_si256(__m256i a, __m256i b)
+{
+  return a ^ b;
+}

Modified: cfe/trunk/test/CodeGen/avx2-builtins.c
URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/avx2-builtins.c?rev=146862&r1=146861&r2=146862&view=diff
==============================================================================
--- cfe/trunk/test/CodeGen/avx2-builtins.c (original)
+++ cfe/trunk/test/CodeGen/avx2-builtins.c Mon Dec 19 03:03:48 2011
@@ -134,3 +134,24 @@
   // CHECK: @llvm.x86.avx2.psubus.w
   return _mm256_subs_epu16(a, b);
 }
+
+__m256 test_mm256_and_si256(__m256 a, __m256 b) {
+  // CHECK: and <4 x i64>
+  return _mm256_and_si256(a, b);
+}
+
+__m256 test_mm256_andnot_si256(__m256 a, __m256 b) {
+  // CHECK: xor <4 x i64>
+  // CHECK: and <4 x i64>
+  return _mm256_andnot_si256(a, b);
+}
+
+__m256 test_mm256_or_si256(__m256 a, __m256 b) {
+  // CHECK: or <4 x i64>
+  return _mm256_or_si256(a, b);
+}
+
+__m256 test_mm256_xor_si256(__m256 a, __m256 b) {
+  // CHECK: xor <4 x i64>
+  return _mm256_xor_si256(a, b);
+}