[cfe-commits] r134304 - /cfe/trunk/include/clang/Basic/BuiltinsX86.def

Fri Jul 1 18:53:37 PDT 2011

Author: efriedma
Date: Fri Jul  1 20:53:37 2011
New Revision: 134304

URL: http://llvm.org/viewvc/llvm-project?rev=134304&view=rev
Log:
Reorganize builtins to separate out builtins which require MMX registers.  No functional change.


Modified:
    cfe/trunk/include/clang/Basic/BuiltinsX86.def

Modified: cfe/trunk/include/clang/Basic/BuiltinsX86.def
URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/Basic/BuiltinsX86.def?rev=134304&r1=134303&r2=134304&view=diff
==============================================================================

--- cfe/trunk/include/clang/Basic/BuiltinsX86.def (original)
+++ cfe/trunk/include/clang/Basic/BuiltinsX86.def Fri Jul  1 20:53:37 2011
@@ -26,6 +26,7 @@
 
 // 3DNow!
 //
+BUILTIN(__builtin_ia32_femms, "v", "")
 BUILTIN(__builtin_ia32_pavgusb, "V8cV8cV8c", "nc")
 BUILTIN(__builtin_ia32_pf2id, "V2iV2f", "nc")
 BUILTIN(__builtin_ia32_pfacc, "V2fV2fV2f", "nc")
@@ -47,7 +48,7 @@
 BUILTIN(__builtin_ia32_pfsubr, "V2fV2fV2f", "nc")
 BUILTIN(__builtin_ia32_pi2fd, "V2fV2i", "nc")
 BUILTIN(__builtin_ia32_pmulhrw, "V4sV4sV4s", "nc")
-// 3DNow! Extensions.
+// 3DNow! Extensions (3dnowa).
 BUILTIN(__builtin_ia32_pf2iw, "V2iV2f", "nc")
 BUILTIN(__builtin_ia32_pfnacc, "V2fV2fV2f", "nc")
 BUILTIN(__builtin_ia32_pfpnacc, "V2fV2fV2f", "nc")
@@ -57,15 +58,13 @@
 
 // MMX
 //
-// FIXME: All MMX instructions will be generated via builtins. Any MMX vector
+// All MMX instructions will be generated via builtins. Any MMX vector
 // types (<1 x i64>, <2 x i32>, etc.) that aren't used by these builtins will be
 // expanded by the back-end.
 BUILTIN(__builtin_ia32_emms, "v", "")
-BUILTIN(__builtin_ia32_femms, "v", "")
 BUILTIN(__builtin_ia32_paddb, "V8cV8cV8c", "")
 BUILTIN(__builtin_ia32_paddw, "V4sV4sV4s", "")
 BUILTIN(__builtin_ia32_paddd, "V2iV2iV2i", "")
-BUILTIN(__builtin_ia32_paddq, "V1LLiV1LLiV1LLi", "")
 BUILTIN(__builtin_ia32_paddsb, "V8cV8cV8c", "")
 BUILTIN(__builtin_ia32_paddsw, "V4sV4sV4s", "")
 BUILTIN(__builtin_ia32_paddusb, "V8cV8cV8c", "")
@@ -73,27 +72,17 @@
 BUILTIN(__builtin_ia32_psubb, "V8cV8cV8c", "")
 BUILTIN(__builtin_ia32_psubw, "V4sV4sV4s", "")
 BUILTIN(__builtin_ia32_psubd, "V2iV2iV2i", "")
-BUILTIN(__builtin_ia32_psubq, "V1LLiV1LLiV1LLi", "")
 BUILTIN(__builtin_ia32_psubsb, "V8cV8cV8c", "")
 BUILTIN(__builtin_ia32_psubsw, "V4sV4sV4s", "")
 BUILTIN(__builtin_ia32_psubusb, "V8cV8cV8c", "")
 BUILTIN(__builtin_ia32_psubusw, "V4sV4sV4s", "")
 BUILTIN(__builtin_ia32_pmulhw, "V4sV4sV4s", "")
 BUILTIN(__builtin_ia32_pmullw, "V4sV4sV4s", "")
-BUILTIN(__builtin_ia32_pmulhuw, "V4sV4sV4s", "")
-BUILTIN(__builtin_ia32_pmuludq, "V1LLiV2iV2i", "")
 BUILTIN(__builtin_ia32_pmaddwd, "V2iV4sV4s", "")
 BUILTIN(__builtin_ia32_pand, "V1LLiV1LLiV1LLi", "")
 BUILTIN(__builtin_ia32_pandn, "V1LLiV1LLiV1LLi", "")
 BUILTIN(__builtin_ia32_por, "V1LLiV1LLiV1LLi", "")
 BUILTIN(__builtin_ia32_pxor, "V1LLiV1LLiV1LLi", "")
-BUILTIN(__builtin_ia32_pavgb, "V8cV8cV8c", "")
-BUILTIN(__builtin_ia32_pavgw, "V4sV4sV4s", "")
-BUILTIN(__builtin_ia32_pmaxub, "V8cV8cV8c", "")
-BUILTIN(__builtin_ia32_pmaxsw, "V4sV4sV4s", "")
-BUILTIN(__builtin_ia32_pminub, "V8cV8cV8c", "")
-BUILTIN(__builtin_ia32_pminsw, "V4sV4sV4s", "")
-BUILTIN(__builtin_ia32_psadbw, "V4sV8cV8c", "")
 BUILTIN(__builtin_ia32_psllw, "V4sV4sV1LLi", "")
 BUILTIN(__builtin_ia32_pslld, "V2iV2iV1LLi", "")
 BUILTIN(__builtin_ia32_psllq, "V1LLiV1LLiV1LLi", "")
@@ -113,7 +102,6 @@
 BUILTIN(__builtin_ia32_packsswb, "V8cV4sV4s", "")
 BUILTIN(__builtin_ia32_packssdw, "V4sV2iV2i", "")
 BUILTIN(__builtin_ia32_packuswb, "V8cV4sV4s", "")
-BUILTIN(__builtin_ia32_pshufw, "V4sV4sIc", "")
 BUILTIN(__builtin_ia32_punpckhbw, "V8cV8cV8c", "")
 BUILTIN(__builtin_ia32_punpckhwd, "V4sV4sV4s", "")
 BUILTIN(__builtin_ia32_punpckhdq, "V2iV2iV2i", "")
@@ -127,14 +115,53 @@
 BUILTIN(__builtin_ia32_pcmpgtw, "V4sV4sV4s", "")
 BUILTIN(__builtin_ia32_pcmpgtd, "V2iV2iV2i", "")
 BUILTIN(__builtin_ia32_maskmovq, "vV8cV8cc*", "")
-BUILTIN(__builtin_ia32_pmovmskb, "iV8c", "")
 BUILTIN(__builtin_ia32_movntq, "vV1LLi*V1LLi", "")
-BUILTIN(__builtin_ia32_palignr, "V8cV8cV8cIc", "")
 BUILTIN(__builtin_ia32_vec_init_v2si, "V2iii", "")
 BUILTIN(__builtin_ia32_vec_init_v4hi, "V4sssss", "")
 BUILTIN(__builtin_ia32_vec_init_v8qi, "V8ccccccccc", "")
 BUILTIN(__builtin_ia32_vec_ext_v2si, "iV2ii", "")
 
+// MMX2 (MMX+SSE) intrinsics
+BUILTIN(__builtin_ia32_cvtpi2ps, "V4fV4fV2i", "")
+BUILTIN(__builtin_ia32_cvtps2pi, "V2iV4f", "")
+BUILTIN(__builtin_ia32_cvttps2pi, "V2iV4f", "")
+BUILTIN(__builtin_ia32_pavgb, "V8cV8cV8c", "")
+BUILTIN(__builtin_ia32_pavgw, "V4sV4sV4s", "")
+BUILTIN(__builtin_ia32_pmaxsw, "V4sV4sV4s", "")
+BUILTIN(__builtin_ia32_pmaxub, "V8cV8cV8c", "")
+BUILTIN(__builtin_ia32_pminsw, "V4sV4sV4s", "")
+BUILTIN(__builtin_ia32_pminub, "V8cV8cV8c", "")
+BUILTIN(__builtin_ia32_pmovmskb, "iV8c", "")
+BUILTIN(__builtin_ia32_pmulhuw, "V4sV4sV4s", "")
+BUILTIN(__builtin_ia32_psadbw, "V4sV8cV8c", "")
+BUILTIN(__builtin_ia32_pshufw, "V4sV4sIc", "")
+
+// MMX+SSE2
+BUILTIN(__builtin_ia32_cvtpd2pi, "V2iV2d", "")
+BUILTIN(__builtin_ia32_cvtpi2pd, "V2dV2i", "")
+BUILTIN(__builtin_ia32_cvttpd2pi, "V2iV2d", "")
+BUILTIN(__builtin_ia32_paddq, "V1LLiV1LLiV1LLi", "")
+BUILTIN(__builtin_ia32_pmuludq, "V1LLiV2iV2i", "")
+BUILTIN(__builtin_ia32_psubq, "V1LLiV1LLiV1LLi", "")
+
+// MMX+SSSE3
+BUILTIN(__builtin_ia32_pabsb, "V8cV8c", "")
+BUILTIN(__builtin_ia32_pabsd, "V2iV2i", "")
+BUILTIN(__builtin_ia32_pabsw, "V4sV4s", "")
+BUILTIN(__builtin_ia32_palignr, "V8cV8cV8cIc", "")
+BUILTIN(__builtin_ia32_phaddd, "V2iV2iV2i", "")
+BUILTIN(__builtin_ia32_phaddsw, "V4sV4sV4s", "")
+BUILTIN(__builtin_ia32_phaddw, "V4sV4sV4s", "")
+BUILTIN(__builtin_ia32_phsubd, "V2iV2iV2i", "")
+BUILTIN(__builtin_ia32_phsubsw, "V4sV4sV4s", "")
+BUILTIN(__builtin_ia32_phsubw, "V4sV4sV4s", "")
+BUILTIN(__builtin_ia32_pmaddubsw, "V8cV8cV8c", "")
+BUILTIN(__builtin_ia32_pmulhrsw, "V4sV4sV4s", "")
+BUILTIN(__builtin_ia32_pshufb, "V8cV8cV8c", "")
+BUILTIN(__builtin_ia32_psignw, "V4sV4sV4s", "")
+BUILTIN(__builtin_ia32_psignb, "V8cV8cV8c", "")
+BUILTIN(__builtin_ia32_psignd, "V2iV2iV2i", "")
+
 // SSE intrinsics.
 BUILTIN(__builtin_ia32_comieq, "iV4fV4f", "")
 BUILTIN(__builtin_ia32_comilt, "iV4fV4f", "")
@@ -204,42 +231,24 @@
 BUILTIN(__builtin_ia32_hsubps, "V4fV4fV4f", "")
 BUILTIN(__builtin_ia32_hsubpd, "V2dV2dV2d", "")
 BUILTIN(__builtin_ia32_phaddw128, "V8sV8sV8s", "")
-BUILTIN(__builtin_ia32_phaddw, "V4sV4sV4s", "")
 BUILTIN(__builtin_ia32_phaddd128, "V4iV4iV4i", "")
-BUILTIN(__builtin_ia32_phaddd, "V2iV2iV2i", "")
 BUILTIN(__builtin_ia32_phaddsw128, "V8sV8sV8s", "")
-BUILTIN(__builtin_ia32_phaddsw, "V4sV4sV4s", "")
 BUILTIN(__builtin_ia32_phsubw128, "V8sV8sV8s", "")
-BUILTIN(__builtin_ia32_phsubw, "V4sV4sV4s", "")
 BUILTIN(__builtin_ia32_phsubd128, "V4iV4iV4i", "")
-BUILTIN(__builtin_ia32_phsubd, "V2iV2iV2i", "")
 BUILTIN(__builtin_ia32_phsubsw128, "V8sV8sV8s", "")
-BUILTIN(__builtin_ia32_phsubsw, "V4sV4sV4s", "")
 BUILTIN(__builtin_ia32_pmaddubsw128, "V16cV16cV16c", "")
-BUILTIN(__builtin_ia32_pmaddubsw, "V8cV8cV8c", "")
 BUILTIN(__builtin_ia32_pmulhrsw128, "V8sV8sV8s", "")
-BUILTIN(__builtin_ia32_pmulhrsw, "V4sV4sV4s", "")
 BUILTIN(__builtin_ia32_pshufb128, "V16cV16cV16c", "")
-BUILTIN(__builtin_ia32_pshufb, "V8cV8cV8c", "")
 BUILTIN(__builtin_ia32_psignb128, "V16cV16cV16c", "")
-BUILTIN(__builtin_ia32_psignb, "V8cV8cV8c", "")
 BUILTIN(__builtin_ia32_psignw128, "V8sV8sV8s", "")
-BUILTIN(__builtin_ia32_psignw, "V4sV4sV4s", "")
 BUILTIN(__builtin_ia32_psignd128, "V4iV4iV4i", "")
-BUILTIN(__builtin_ia32_psignd, "V2iV2iV2i", "")
 BUILTIN(__builtin_ia32_pabsb128, "V16cV16c", "")
-BUILTIN(__builtin_ia32_pabsb, "V8cV8c", "")
 BUILTIN(__builtin_ia32_pabsw128, "V8sV8s", "")
-BUILTIN(__builtin_ia32_pabsw, "V4sV4s", "")
 BUILTIN(__builtin_ia32_pabsd128, "V4iV4i", "")
-BUILTIN(__builtin_ia32_pabsd, "V2iV2i", "")
 BUILTIN(__builtin_ia32_ldmxcsr, "vUi", "")
 BUILTIN(__builtin_ia32_stmxcsr, "Ui", "")
-BUILTIN(__builtin_ia32_cvtpi2ps, "V4fV4fV2i", "")
-BUILTIN(__builtin_ia32_cvtps2pi, "V2iV4f", "")
 BUILTIN(__builtin_ia32_cvtss2si, "iV4f", "")
 BUILTIN(__builtin_ia32_cvtss2si64, "LLiV4f", "")
-BUILTIN(__builtin_ia32_cvttps2pi, "V2iV4f", "")
 BUILTIN(__builtin_ia32_storeups, "vf*V4f", "")
 BUILTIN(__builtin_ia32_storehps, "vV2i*V4f", "")
 BUILTIN(__builtin_ia32_storelps, "vV2i*V4f", "")
@@ -265,11 +274,8 @@
 BUILTIN(__builtin_ia32_cvtdq2pd, "V2dV4i", "")
 BUILTIN(__builtin_ia32_cvtdq2ps, "V4fV4i", "")
 BUILTIN(__builtin_ia32_cvtpd2dq, "V2LLiV2d", "")
-BUILTIN(__builtin_ia32_cvtpd2pi, "V2iV2d", "")
 BUILTIN(__builtin_ia32_cvtpd2ps, "V4fV2d", "")
 BUILTIN(__builtin_ia32_cvttpd2dq, "V4iV2d", "")
-BUILTIN(__builtin_ia32_cvttpd2pi, "V2iV2d", "")
-BUILTIN(__builtin_ia32_cvtpi2pd, "V2dV2i", "")
 BUILTIN(__builtin_ia32_cvtsd2si, "iV2d", "")
 BUILTIN(__builtin_ia32_cvtsd2si64, "LLiV2d", "")
 BUILTIN(__builtin_ia32_cvtps2dq, "V4iV4f", "")



