[cfe-commits] r133532 - in /cfe/trunk: include/clang/Driver/CC1Options.td include/clang/Frontend/CodeGenOptions.h lib/CodeGen/CGRecordLayoutBuilder.cpp lib/Frontend/CompilerInvocation.cpp

Daniel Dunbar daniel at zuster.org
Tue Jun 21 11:54:46 PDT 2011 

Author: ddunbar
Date: Tue Jun 21 13:54:46 2011
New Revision: 133532

URL: http://llvm.org/viewvc/llvm-project?rev=133532&view=rev
Log:
IRgen: Add a -fuse-register-sized-bitfield-access option, for testing.
 - Changes bit-field access policy to try to use (aligned) register sized accesses.

The idea here is that by using larger accesses we expose more coalescing
potential to the backend when we have situations like adjacent bit-fields in the
same structure (which is common), and that the backend should be smart enough to
narrow the accesses down when no coalescing is done or when it is shown not to
be profitable.

--
$ clang -m32 -O3 -S -o - t.c
_f0:                                    ## @f0
	pushl	%ebp
	movl	%esp, %ebp
	movl	8(%ebp), %eax
	movb	(%eax), %cl
	andb	$-128, %cl
	orb	$1, %cl
	movb	%cl, (%eax)
	movb	1(%eax), %cl
	andb	$-128, %cl
	orb	$1, %cl
	movb	%cl, 1(%eax)
	movb	2(%eax), %cl
	andb	$-128, %cl
	orb	$1, %cl
	movb	%cl, 2(%eax)
	movb	3(%eax), %cl
	andb	$-128, %cl
	orb	$1, %cl
	movb	%cl, 3(%eax)
	popl	%ebp
	ret

$ clang -m32 -O3 -S -o - t.c -Xclang -fuse-register-sized-bitfield-access
_f0:                                    ## @f0
	pushl	%ebp
	movl	%esp, %ebp
	movl	8(%ebp), %eax
	movl	$-2139062144, %ecx      ## imm = 0xFFFFFFFF80808080
	andl	(%eax), %ecx
	orl	$16843009, %ecx         ## imm = 0x1010101
	movl	%ecx, (%eax)
	popl	%ebp
	ret
--

Modified:
    cfe/trunk/include/clang/Driver/CC1Options.td
    cfe/trunk/include/clang/Frontend/CodeGenOptions.h
    cfe/trunk/lib/CodeGen/CGRecordLayoutBuilder.cpp
    cfe/trunk/lib/Frontend/CompilerInvocation.cpp

Modified: cfe/trunk/include/clang/Driver/CC1Options.td
URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/Driver/CC1Options.td?rev=133532&r1=133531&r2=133532&view=diff
==============================================================================
--- cfe/trunk/include/clang/Driver/CC1Options.td (original)
+++ cfe/trunk/include/clang/Driver/CC1Options.td Tue Jun 21 13:54:46 2011
@@ -143,6 +143,8 @@
 def coverage_file : Separate<"-coverage-file">,
   HelpText<"Emit coverage data to this filename. The extension will be replaced.">;
 def coverage_file_EQ : Joined<"-coverage-file=">, Alias<coverage_file>;
+def fuse_register_sized_bitfield_access: Flag<"-fuse-register-sized-bitfield-access">,
+  HelpText<"Use register sized accesses to bit-fields, when possible.">;
 def relaxed_aliasing : Flag<"-relaxed-aliasing">,
   HelpText<"Turn off Type Based Alias Analysis">;
 def masm_verbose : Flag<"-masm-verbose">,

Modified: cfe/trunk/include/clang/Frontend/CodeGenOptions.h
URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/Frontend/CodeGenOptions.h?rev=133532&r1=133531&r2=133532&view=diff
==============================================================================
--- cfe/trunk/include/clang/Frontend/CodeGenOptions.h (original)
+++ cfe/trunk/include/clang/Frontend/CodeGenOptions.h Tue Jun 21 13:54:46 2011
@@ -91,6 +91,11 @@
   unsigned UnrollLoops       : 1; /// Control whether loops are unrolled.
   unsigned UnsafeFPMath      : 1; /// Allow unsafe floating point optzns.
   unsigned UnwindTables      : 1; /// Emit unwind tables.
+
+  /// Attempt to use register sized accesses to bit-fields in structures, when
+  /// possible.
+  unsigned UseRegisterSizedBitfieldAccess : 1;
+
   unsigned VerifyModule      : 1; /// Control whether the module should be run
                                   /// through the LLVM Verifier.
 
@@ -176,6 +181,7 @@
     UnrollLoops = 0;
     UnsafeFPMath = 0;
     UnwindTables = 0;
+    UseRegisterSizedBitfieldAccess = 0;
     VerifyModule = 1;
 
     Inlining = NoInlining;

Modified: cfe/trunk/lib/CodeGen/CGRecordLayoutBuilder.cpp
URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/CodeGen/CGRecordLayoutBuilder.cpp?rev=133532&r1=133531&r2=133532&view=diff
==============================================================================
--- cfe/trunk/lib/CodeGen/CGRecordLayoutBuilder.cpp (original)
+++ cfe/trunk/lib/CodeGen/CGRecordLayoutBuilder.cpp Tue Jun 21 13:54:46 2011
@@ -18,6 +18,7 @@
 #include "clang/AST/DeclCXX.h"
 #include "clang/AST/Expr.h"
 #include "clang/AST/RecordLayout.h"
+#include "clang/Frontend/CodeGenOptions.h"
 #include "CodeGenTypes.h"
 #include "CGCXXABI.h"
 #include "llvm/DerivedTypes.h"
@@ -268,6 +269,18 @@
   unsigned AccessedTargetBits = 0;       // The number of target bits accessed.
   unsigned AccessWidth = TypeSizeInBits; // The current access width to attempt.
 
+  // If requested, widen the initial bit-field access to be register sized. The
+  // theory is that this is most likely to allow multiple accesses into the same
+  // structure to be coalesced, and that the backend should be smart enough to
+  // narrow the store if no coalescing is ever done.
+  //
+  // The subsequent code will handle align these access to common boundaries and
+  // guaranteeing that we do not access past the end of the structure.
+  if (Types.getCodeGenOpts().UseRegisterSizedBitfieldAccess) {
+    if (AccessWidth < Types.getTarget().getRegisterWidth())
+      AccessWidth = Types.getTarget().getRegisterWidth();
+  }
+
   // Round down from the field offset to find the first access position that is
   // at an aligned offset of the initial access type.
   uint64_t AccessStart = FieldOffset - (FieldOffset % AccessWidth);

Modified: cfe/trunk/lib/Frontend/CompilerInvocation.cpp
URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Frontend/CompilerInvocation.cpp?rev=133532&r1=133531&r2=133532&view=diff
==============================================================================
--- cfe/trunk/lib/Frontend/CompilerInvocation.cpp (original)
+++ cfe/trunk/lib/Frontend/CompilerInvocation.cpp Tue Jun 21 13:54:46 2011
@@ -133,6 +133,8 @@
     Res.push_back("-fno-common");
   if (Opts.ForbidGuardVariables)
     Res.push_back("-fforbid-guard-variables");
+  if (Opts.UseRegisterSizedBitfieldAccess)
+    Res.push_back("-fuse-register-sized-bitfield-access");
   if (Opts.NoImplicitFloat)
     Res.push_back("-no-implicit-float");
   if (Opts.OmitLeafFramePointer)
@@ -956,6 +958,8 @@
   Opts.DisableLLVMOpts = Args.hasArg(OPT_disable_llvm_optzns);
   Opts.DisableRedZone = Args.hasArg(OPT_disable_red_zone);
   Opts.ForbidGuardVariables = Args.hasArg(OPT_fforbid_guard_variables);
+  Opts.UseRegisterSizedBitfieldAccess = Args.hasArg(
+    OPT_fuse_register_sized_bitfield_access);
   Opts.RelaxedAliasing = Args.hasArg(OPT_relaxed_aliasing);
   Opts.DwarfDebugFlags = Args.getLastArgValue(OPT_dwarf_debug_flags);
   Opts.MergeAllConstants = !Args.hasArg(OPT_fno_merge_all_constants);

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