[cfe-commits] r105930 - in /cfe/trunk/lib: CodeGen/CGBuiltin.cpp CodeGen/CodeGenFunction.h Headers/arm_neon.td Sema/SemaChecking.cpp
Nate Begeman
natebegeman at mac.com
Sun Jun 13 22:21:26 PDT 2010
Author: sampo
Date: Mon Jun 14 00:21:25 2010
New Revision: 105930
URL: http://llvm.org/viewvc/llvm-project?rev=105930&view=rev
Log:
Add some missing shifts
Fix multiplies by scalar
Add SemaChecking code for all immediates
Add SemaChecking-gen support to arm_neon.td
Modified:
cfe/trunk/lib/CodeGen/CGBuiltin.cpp
cfe/trunk/lib/CodeGen/CodeGenFunction.h
cfe/trunk/lib/Headers/arm_neon.td
cfe/trunk/lib/Sema/SemaChecking.cpp
Modified: cfe/trunk/lib/CodeGen/CGBuiltin.cpp
URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/CodeGen/CGBuiltin.cpp?rev=105930&r1=105929&r2=105930&view=diff
==============================================================================
--- cfe/trunk/lib/CodeGen/CGBuiltin.cpp (original)
+++ cfe/trunk/lib/CodeGen/CGBuiltin.cpp Mon Jun 14 00:21:25 2010
@@ -902,11 +902,15 @@
}
Value *CodeGenFunction::EmitNeonCall(Function *F, SmallVectorImpl<Value*> &Ops,
- const char *name, bool splat) {
+ const char *name, bool splat,
+ unsigned shift, bool rightshift) {
unsigned j = 0;
for (Function::const_arg_iterator ai = F->arg_begin(), ae = F->arg_end();
ai != ae; ++ai, ++j)
- Ops[j] = Builder.CreateBitCast(Ops[j], ai->getType(), name);
+ if (shift > 0 && shift == j)
+ Ops[j] = EmitNeonShiftVector(Ops[j], ai->getType(), rightshift);
+ else
+ Ops[j] = Builder.CreateBitCast(Ops[j], ai->getType(), name);
if (splat) {
Ops[j-1] = EmitNeonSplat(Ops[j-1], cast<Constant>(Ops[j]));
@@ -1158,24 +1162,24 @@
splat = true;
case ARM::BI__builtin_neon_vqdmlal_v:
return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vqdmlal, &Ty, 1),
- Ops, "vqdmlal");
+ Ops, "vqdmlal", splat);
case ARM::BI__builtin_neon_vqdmlsl_lane_v:
splat = true;
case ARM::BI__builtin_neon_vqdmlsl_v:
return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vqdmlsl, &Ty, 1),
- Ops, "vqdmlsl");
+ Ops, "vqdmlsl", splat);
case ARM::BI__builtin_neon_vqdmulh_lane_v:
case ARM::BI__builtin_neon_vqdmulhq_lane_v:
splat = true;
case ARM::BI__builtin_neon_vqdmulh_v:
case ARM::BI__builtin_neon_vqdmulhq_v:
return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vqdmulh, &Ty, 1),
- Ops, "vqdmulh");
+ Ops, "vqdmulh", splat);
case ARM::BI__builtin_neon_vqdmull_lane_v:
splat = true;
case ARM::BI__builtin_neon_vqdmull_v:
return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vqdmull, &Ty, 1),
- Ops, "vqdmull");
+ Ops, "vqdmull", splat);
case ARM::BI__builtin_neon_vqmovn_v:
Int = usgn ? Intrinsic::arm_neon_vqmovnu : Intrinsic::arm_neon_vqmovns;
return EmitNeonCall(CGM.getIntrinsic(Int, &Ty, 1), Ops, "vqmovn");
@@ -1183,25 +1187,46 @@
return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vqmovnsu, &Ty, 1),
Ops, "vqdmull");
case ARM::BI__builtin_neon_vqneg_v:
- return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vqneg, &Ty, 1),
- Ops, "vqneg");
+ return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vqneg, &Ty, 1),
+ Ops, "vqneg");
case ARM::BI__builtin_neon_vqrdmulh_lane_v:
case ARM::BI__builtin_neon_vqrdmulhq_lane_v:
splat = true;
case ARM::BI__builtin_neon_vqrdmulh_v:
case ARM::BI__builtin_neon_vqrdmulhq_v:
return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vqrdmulh, &Ty, 1),
- Ops, "vqrdmulh");
+ Ops, "vqrdmulh", splat);
case ARM::BI__builtin_neon_vqrshl_v:
case ARM::BI__builtin_neon_vqrshlq_v:
Int = usgn ? Intrinsic::arm_neon_vqrshiftu : Intrinsic::arm_neon_vqrshifts;
return EmitNeonCall(CGM.getIntrinsic(Int, &Ty, 1), Ops, "vqrshl");
case ARM::BI__builtin_neon_vqrshrn_n_v:
Int = usgn ? Intrinsic::arm_neon_vqrshiftnu : Intrinsic::arm_neon_vqrshiftns;
- return EmitNeonCall(CGM.getIntrinsic(Int, &Ty, 1), Ops, "vqrshrn_n");
+ return EmitNeonCall(CGM.getIntrinsic(Int, &Ty, 1), Ops, "vqrshrn_n", false,
+ 1, true);
case ARM::BI__builtin_neon_vqrshrun_n_v:
return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vqrshiftnsu, &Ty, 1),
- Ops, "vqrshrun_n");
+ Ops, "vqrshrun_n", false, 1, true);
+ case ARM::BI__builtin_neon_vqshl_v:
+ case ARM::BI__builtin_neon_vqshlq_v:
+ Int = usgn ? Intrinsic::arm_neon_vqshiftu : Intrinsic::arm_neon_vqshifts;
+ return EmitNeonCall(CGM.getIntrinsic(Int, &Ty, 1), Ops, "vqshl");
+ case ARM::BI__builtin_neon_vqshl_n_v:
+ case ARM::BI__builtin_neon_vqshlq_n_v:
+ Int = usgn ? Intrinsic::arm_neon_vqshiftu : Intrinsic::arm_neon_vqshifts;
+ return EmitNeonCall(CGM.getIntrinsic(Int, &Ty, 1), Ops, "vqshl_n", false,
+ 1, false);
+ case ARM::BI__builtin_neon_vqshlu_n_v:
+ case ARM::BI__builtin_neon_vqshluq_n_v:
+ return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vqshiftsu, &Ty, 1),
+ Ops, "vqshlu", 1, false);
+ case ARM::BI__builtin_neon_vqshrn_n_v:
+ Int = usgn ? Intrinsic::arm_neon_vqshiftnu : Intrinsic::arm_neon_vqshiftns;
+ return EmitNeonCall(CGM.getIntrinsic(Int, &Ty, 1), Ops, "vqshrn_n", false,
+ 1, true);
+ case ARM::BI__builtin_neon_vqshrun_n_v:
+ return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vqshiftnsu, &Ty, 1),
+ Ops, "vqshrun_n", false, 1, true);
case ARM::BI__builtin_neon_vqsub_v:
case ARM::BI__builtin_neon_vqsubq_v:
Int = usgn ? Intrinsic::arm_neon_vqsubu : Intrinsic::arm_neon_vqsubs;
@@ -1226,14 +1251,13 @@
Int = usgn ? Intrinsic::arm_neon_vrshiftu : Intrinsic::arm_neon_vrshifts;
return EmitNeonCall(CGM.getIntrinsic(Int, &Ty, 1), Ops, "vrshl");
case ARM::BI__builtin_neon_vrshrn_n_v:
- Ops[1] = EmitNeonShiftVector(Ops[1], Ty, true);
return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vrshiftn, &Ty, 1),
- Ops, "vrshrn_n");
+ Ops, "vrshrn_n", false, 1, true);
case ARM::BI__builtin_neon_vrshr_n_v:
case ARM::BI__builtin_neon_vrshrq_n_v:
- Ops[1] = EmitNeonShiftVector(Ops[1], Ty, true);
Int = usgn ? Intrinsic::arm_neon_vrshiftu : Intrinsic::arm_neon_vrshifts;
- return EmitNeonCall(CGM.getIntrinsic(Int, &Ty, 1), Ops, "vrshr_n");
+ return EmitNeonCall(CGM.getIntrinsic(Int, &Ty, 1), Ops, "vrshr_n", false,
+ 1, true);
case ARM::BI__builtin_neon_vrsqrte_v:
case ARM::BI__builtin_neon_vrsqrteq_v:
return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vrsqrte, &Ty, 1),
@@ -1270,21 +1294,19 @@
Int = usgn ? Intrinsic::arm_neon_vshiftu : Intrinsic::arm_neon_vshifts;
return EmitNeonCall(CGM.getIntrinsic(Int, &Ty, 1), Ops, "vshl");
case ARM::BI__builtin_neon_vshll_n_v:
- Ops[1] = EmitNeonShiftVector(Ops[1], Ty);
Int = usgn ? Intrinsic::arm_neon_vshiftlu : Intrinsic::arm_neon_vshiftls;
- return EmitNeonCall(CGM.getIntrinsic(Int, &Ty, 1), Ops, "vshll");
+ return EmitNeonCall(CGM.getIntrinsic(Int, &Ty, 1), Ops, "vshll", false, 1);
case ARM::BI__builtin_neon_vshl_n_v:
case ARM::BI__builtin_neon_vshlq_n_v:
- Ops[1] = EmitNeonShiftVector(Ops[1], Ty);
- return Builder.CreateShl(Builder.CreateBitCast(Ops[0],Ty), Ops[1],"vshl_n");
+ Ops[1] = EmitNeonShiftVector(Ops[1], Ty, false);
+ return Builder.CreateShl(Builder.CreateBitCast(Ops[0],Ty), Ops[1], "vshl_n");
case ARM::BI__builtin_neon_vshrn_n_v:
- Ops[1] = EmitNeonShiftVector(Ops[1], Ty, true);
return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vshiftn, &Ty, 1),
- Ops, "vshrn_n");
+ Ops, "vshrn_n", false, 1, true);
case ARM::BI__builtin_neon_vshr_n_v:
case ARM::BI__builtin_neon_vshrq_n_v:
Ops[0] = Builder.CreateBitCast(Ops[0], Ty);
- Ops[1] = EmitNeonShiftVector(Ops[1], Ty);
+ Ops[1] = EmitNeonShiftVector(Ops[1], Ty, false);
if (usgn)
return Builder.CreateLShr(Ops[0], Ops[1], "vshr_n");
else
@@ -1301,7 +1323,7 @@
case ARM::BI__builtin_neon_vsraq_n_v:
Ops[0] = Builder.CreateBitCast(Ops[0], Ty);
Ops[1] = Builder.CreateBitCast(Ops[1], Ty);
- Ops[2] = EmitNeonShiftVector(Ops[2], Ty);
+ Ops[2] = EmitNeonShiftVector(Ops[2], Ty, false);
if (usgn)
Ops[1] = Builder.CreateLShr(Ops[1], Ops[2], "vsra_n");
else
Modified: cfe/trunk/lib/CodeGen/CodeGenFunction.h
URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/CodeGen/CodeGenFunction.h?rev=105930&r1=105929&r2=105930&view=diff
==============================================================================
--- cfe/trunk/lib/CodeGen/CodeGenFunction.h (original)
+++ cfe/trunk/lib/CodeGen/CodeGenFunction.h Mon Jun 14 00:21:25 2010
@@ -1147,10 +1147,11 @@
llvm::Value *EmitARMBuiltinExpr(unsigned BuiltinID, const CallExpr *E);
llvm::Value *EmitNeonCall(llvm::Function *F,
llvm::SmallVectorImpl<llvm::Value*> &O,
- const char *name, bool splat = false);
+ const char *name, bool splat = false,
+ unsigned shift = 0, bool rightshift = false);
llvm::Value *EmitNeonSplat(llvm::Value *V, llvm::Constant *Idx);
llvm::Value *EmitNeonShiftVector(llvm::Value *V, const llvm::Type *Ty,
- bool negateForRightShift = false);
+ bool negateForRightShift);
llvm::Value *EmitX86BuiltinExpr(unsigned BuiltinID, const CallExpr *E);
llvm::Value *EmitPPCBuiltinExpr(unsigned BuiltinID, const CallExpr *E);
Modified: cfe/trunk/lib/Headers/arm_neon.td
URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Headers/arm_neon.td?rev=105930&r1=105929&r2=105930&view=diff
==============================================================================
--- cfe/trunk/lib/Headers/arm_neon.td (original)
+++ cfe/trunk/lib/Headers/arm_neon.td Mon Jun 14 00:21:25 2010
@@ -49,6 +49,7 @@
string Prototype = p;
string Types = t;
Op Operand = o;
+ bit isShift = 0;
}
// Used to generate Builtins.def
@@ -174,6 +175,7 @@
////////////////////////////////////////////////////////////////////////////////
// E.3.12 Shifts by constant
+let isShift = 1 in {
def VSHR_N : SInst<"ddi", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
def VSHL_N : IInst<"ddi", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
def VRSHR_N : SInst<"ddi", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
@@ -181,18 +183,19 @@
def VRSRA_N : SInst<"dddi", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
def VQSHL_N : SInst<"ddi", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
def VQSHLU_N : SInst<"udi", "csilQcQsQiQl">;
-def VSHRN_N : IInst<"dwi", "csiUcUsUi">;
-def VQSHRUN_N : SInst<"uwi", "csi">;
-def VQRSHRUN_N : SInst<"uwi", "csi">;
-def VQSHRN_N : SInst<"dwi", "csiUcUsUi">;
-def VRSHRN_N : IInst<"dwi", "csiUcUsUi">;
-def VQRSHRN_N : SInst<"dwi", "csiUcUsUi">;
+def VSHRN_N : IInst<"hki", "silUsUiUl">;
+def VQSHRUN_N : SInst<"eki", "sil">;
+def VQRSHRUN_N : SInst<"eki", "sil">;
+def VQSHRN_N : SInst<"hki", "silUsUiUl">;
+def VRSHRN_N : IInst<"hki", "silUsUiUl">;
+def VQRSHRN_N : SInst<"hki", "silUsUiUl">;
def VSHLL_N : SInst<"wdi", "csiUcUsUi">;
////////////////////////////////////////////////////////////////////////////////
// E.3.13 Shifts with insert
def VSRI_N : WInst<"dddi", "csilUcUsUiUlPcPsQcQsQiQlQUcQUsQUiQUlQPcQPs">;
def VSLI_N : WInst<"dddi", "csilUcUsUiUlPcPsQcQsQiQlQUcQUsQUiQUlQPcQPs">;
+}
////////////////////////////////////////////////////////////////////////////////
// E.3.14 Loads and stores of a single vector
Modified: cfe/trunk/lib/Sema/SemaChecking.cpp
URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Sema/SemaChecking.cpp?rev=105930&r1=105929&r2=105930&view=diff
==============================================================================
--- cfe/trunk/lib/Sema/SemaChecking.cpp (original)
+++ cfe/trunk/lib/Sema/SemaChecking.cpp Mon Jun 14 00:21:25 2010
@@ -242,10 +242,40 @@
return false;
}
+// Get the valid immediate range for the specified NEON type code.
+static unsigned RFT(unsigned t, bool shift = false) {
+ bool quad = t & 0x10;
+
+ switch (t & 0x7) {
+ case 0: // i8
+ return shift ? 7 : (8 << quad) - 1;
+ case 1: // i16
+ return shift ? 15 : (4 << quad) - 1;
+ case 2: // i32
+ return shift ? 31 : (2 << quad) - 1;
+ case 3: // i64
+ return shift ? 63 : (1 << quad) - 1;
+ case 4: // f32
+ assert(!shift && "cannot shift float types!");
+ return (2 << quad) - 1;
+ case 5: // poly8
+ assert(!shift && "cannot shift polynomial types!");
+ return (8 << quad) - 1;
+ case 6: // poly16
+ assert(!shift && "cannot shift polynomial types!");
+ return (4 << quad) - 1;
+ case 7: // float16
+ assert(!shift && "cannot shift float types!");
+ return (4 << quad) - 1;
+ }
+ return 0;
+}
+
bool Sema::CheckARMBuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall) {
llvm::APSInt Result;
unsigned mask = 0;
+ unsigned TV = 0;
switch (BuiltinID) {
case ARM::BI__builtin_neon_vaba_v: mask = 0x707; break;
case ARM::BI__builtin_neon_vabaq_v: mask = 0x7070000; break;
@@ -449,26 +479,112 @@
if (SemaBuiltinConstantArg(TheCall, ArgNo, Result))
return true;
- unsigned Val = Result.getLimitedValue(32);
- if ((Val > 31) || (mask & (1 << Val)) == 0)
+ TV = Result.getLimitedValue(32);
+ if ((TV > 31) || (mask & (1 << TV)) == 0)
return Diag(TheCall->getLocStart(), diag::err_invalid_neon_type_code)
<< TheCall->getArg(ArgNo)->getSourceRange();
}
// For NEON intrinsics which take an immediate value as part of the
// instruction, range check them here.
- unsigned i = 0, upper = 0;
+ unsigned i = 0, l = 0, u = 0;
switch (BuiltinID) {
default: return false;
+ case ARM::BI__builtin_neon_vcvt_n_f32_v: i = 1; u = RFT(TV); break;
+ case ARM::BI__builtin_neon_vcvtq_n_f32_v: i = 1; u = RFT(TV); break;
+ case ARM::BI__builtin_neon_vcvt_n_s32_v: i = 1; u = RFT(TV); break;
+ case ARM::BI__builtin_neon_vcvtq_n_s32_v: i = 1; u = RFT(TV); break;
+ case ARM::BI__builtin_neon_vcvt_n_u32_v: i = 1; u = RFT(TV); break;
+ case ARM::BI__builtin_neon_vcvtq_n_u32_v: i = 1; u = RFT(TV); break;
+ case ARM::BI__builtin_neon_vext_v: i = 2; u = RFT(TV); break;
+ case ARM::BI__builtin_neon_vextq_v: i = 2; u = RFT(TV); break;
+ case ARM::BI__builtin_neon_vget_lane_i8: i = 1; u = 7; break;
+ case ARM::BI__builtin_neon_vget_lane_i16: i = 1; u = 3; break;
+ case ARM::BI__builtin_neon_vget_lane_i32: i = 1; u = 1; break;
+ case ARM::BI__builtin_neon_vget_lane_f32: i = 1; u = 1; break;
+ case ARM::BI__builtin_neon_vgetq_lane_i8: i = 1; u = 15; break;
+ case ARM::BI__builtin_neon_vgetq_lane_i16: i = 1; u = 7; break;
+ case ARM::BI__builtin_neon_vgetq_lane_i32: i = 1; u = 3; break;
+ case ARM::BI__builtin_neon_vgetq_lane_f32: i = 1; u = 3; break;
+ case ARM::BI__builtin_neon_vget_lane_i64: i = 1; u = 0; break;
+ case ARM::BI__builtin_neon_vgetq_lane_i64: i = 1; u = 1; break;
+ case ARM::BI__builtin_neon_vld1q_lane_v: i = 1; u = RFT(TV); break;
+ case ARM::BI__builtin_neon_vld1_lane_v: i = 1; u = RFT(TV); break;
+ case ARM::BI__builtin_neon_vld2q_lane_v: i = 1; u = RFT(TV); break;
+ case ARM::BI__builtin_neon_vld2_lane_v: i = 1; u = RFT(TV); break;
+ case ARM::BI__builtin_neon_vld3q_lane_v: i = 1; u = RFT(TV); break;
+ case ARM::BI__builtin_neon_vld3_lane_v: i = 1; u = RFT(TV); break;
+ case ARM::BI__builtin_neon_vld4q_lane_v: i = 1; u = RFT(TV); break;
+ case ARM::BI__builtin_neon_vld4_lane_v: i = 1; u = RFT(TV); break;
+ case ARM::BI__builtin_neon_vmlal_lane_v: i = 3; u = RFT(TV); break;
+ case ARM::BI__builtin_neon_vmla_lane_v: i = 3; u = RFT(TV); break;
+ case ARM::BI__builtin_neon_vmlaq_lane_v: i = 3; u = RFT(TV); break;
+ case ARM::BI__builtin_neon_vmlsl_lane_v: i = 3; u = RFT(TV); break;
+ case ARM::BI__builtin_neon_vmls_lane_v: i = 3; u = RFT(TV); break;
+ case ARM::BI__builtin_neon_vmlsq_lane_v: i = 3; u = RFT(TV); break;
+ case ARM::BI__builtin_neon_vmull_lane_v: i = 2; u = RFT(TV); break;
+ case ARM::BI__builtin_neon_vqdmlal_lane_v: i = 3; u = RFT(TV); break;
+ case ARM::BI__builtin_neon_vqdmlsl_lane_v: i = 3; u = RFT(TV); break;
+ case ARM::BI__builtin_neon_vqdmulh_lane_v: i = 2; u = RFT(TV); break;
+ case ARM::BI__builtin_neon_vqdmulhq_lane_v: i = 2; u = RFT(TV); break;
+ case ARM::BI__builtin_neon_vqdmull_lane_v: i = 2; u = RFT(TV); break;
+ case ARM::BI__builtin_neon_vqrdmulh_lane_v: i = 2; u = RFT(TV); break;
+ case ARM::BI__builtin_neon_vqrdmulhq_lane_v: i = 2; u = RFT(TV); break;
+ case ARM::BI__builtin_neon_vqrshrn_n_v: i = 1; l = 1; u = RFT(TV, true); break;
+ case ARM::BI__builtin_neon_vqrshrun_n_v: i = 1; l = 1; u = RFT(TV, true); break;
+ case ARM::BI__builtin_neon_vqshlu_n_v: i = 1; u = RFT(TV, true); break;
+ case ARM::BI__builtin_neon_vqshluq_n_v: i = 1; u = RFT(TV, true); break;
+ case ARM::BI__builtin_neon_vqshl_n_v: i = 1; u = RFT(TV, true); break;
+ case ARM::BI__builtin_neon_vqshlq_n_v: i = 1; u = RFT(TV, true); break;
+ case ARM::BI__builtin_neon_vqshrn_n_v: i = 1; l = 1; u = RFT(TV, true); break;
+ case ARM::BI__builtin_neon_vqshrun_n_v: i = 1; l = 1; u = RFT(TV, true); break;
+ case ARM::BI__builtin_neon_vrshrn_n_v: i = 1; l = 1; u = RFT(TV, true); break;
+ case ARM::BI__builtin_neon_vrshr_n_v: i = 1; l = 1; u = RFT(TV, true); break;
+ case ARM::BI__builtin_neon_vrshrq_n_v: i = 1; l = 1; u = RFT(TV, true); break;
+ case ARM::BI__builtin_neon_vrsra_n_v: i = 2; l = 1; u = RFT(TV, true); break;
+ case ARM::BI__builtin_neon_vrsraq_n_v: i = 2; l = 1; u = RFT(TV, true); break;
+ case ARM::BI__builtin_neon_vset_lane_i8: i = 2; u = 7; break;
+ case ARM::BI__builtin_neon_vset_lane_i16: i = 2; u = 3; break;
+ case ARM::BI__builtin_neon_vset_lane_i32: i = 2; u = 1; break;
+ case ARM::BI__builtin_neon_vset_lane_f32: i = 2; u = 1; break;
+ case ARM::BI__builtin_neon_vsetq_lane_i8: i = 2; u = 15; break;
+ case ARM::BI__builtin_neon_vsetq_lane_i16: i = 2; u = 7; break;
+ case ARM::BI__builtin_neon_vsetq_lane_i32: i = 2; u = 3; break;
+ case ARM::BI__builtin_neon_vsetq_lane_f32: i = 2; u = 3; break;
+ case ARM::BI__builtin_neon_vset_lane_i64: i = 2; u = 0; break;
+ case ARM::BI__builtin_neon_vsetq_lane_i64: i = 2; u = 1; break;
+ case ARM::BI__builtin_neon_vshll_n_v: i = 1; u = RFT(TV, true); break;
+ case ARM::BI__builtin_neon_vshl_n_v: i = 1; u = RFT(TV, true); break;
+ case ARM::BI__builtin_neon_vshlq_n_v: i = 1; u = RFT(TV, true); break;
+ case ARM::BI__builtin_neon_vshrn_n_v: i = 1; l = 1; u = RFT(TV, true); break;
+ case ARM::BI__builtin_neon_vshr_n_v: i = 1; l = 1; u = RFT(TV, true); break;
+ case ARM::BI__builtin_neon_vshrq_n_v: i = 1; l = 1; u = RFT(TV, true); break;
+ case ARM::BI__builtin_neon_vsli_n_v: i = 2; u = RFT(TV, true); break;
+ case ARM::BI__builtin_neon_vsliq_n_v: i = 2; u = RFT(TV, true); break;
+ case ARM::BI__builtin_neon_vsra_n_v: i = 2; l = 1; u = RFT(TV, true); break;
+ case ARM::BI__builtin_neon_vsraq_n_v: i = 2; l = 1; u = RFT(TV, true); break;
+ case ARM::BI__builtin_neon_vsri_n_v: i = 2; l = 1; u = RFT(TV, true); break;
+ case ARM::BI__builtin_neon_vsriq_n_v: i = 2; l = 1; u = RFT(TV, true); break;
+ case ARM::BI__builtin_neon_vst1q_lane_v: i = 2; u = RFT(TV); break;
+ case ARM::BI__builtin_neon_vst1_lane_v: i = 2; u = RFT(TV); break;
+ case ARM::BI__builtin_neon_vst2q_lane_v: i = 2; u = RFT(TV); break;
+ case ARM::BI__builtin_neon_vst2_lane_v: i = 2; u = RFT(TV); break;
+ case ARM::BI__builtin_neon_vst3q_lane_v: i = 2; u = RFT(TV); break;
+ case ARM::BI__builtin_neon_vst3_lane_v: i = 2; u = RFT(TV); break;
+ case ARM::BI__builtin_neon_vst4q_lane_v: i = 2; u = RFT(TV); break;
+ case ARM::BI__builtin_neon_vst4_lane_v: i = 2; u = RFT(TV); break;
};
+ // Check that the immediate argument is actually a constant.
if (SemaBuiltinConstantArg(TheCall, i, Result))
return true;
+ // Range check against the upper/lower values for this isntruction.
unsigned Val = Result.getZExtValue();
- if (Val > upper)
+ if (Val < l || Val > (u + l))
return Diag(TheCall->getLocStart(), diag::err_argument_invalid_range)
- << "0" << llvm::utostr(upper) << TheCall->getArg(i)->getSourceRange();
+ << llvm::utostr(l) << llvm::utostr(u+l)
+ << TheCall->getArg(i)->getSourceRange();
return false;
}
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