[cfe-commits] r105489 - in /cfe/trunk: include/clang/Basic/BuiltinsARM.def lib/Headers/arm_neon.td
Nate Begeman
natebegeman at mac.com
Fri Jun 4 14:36:27 PDT 2010
Author: sampo
Date: Fri Jun 4 16:36:27 2010
New Revision: 105489
URL: http://llvm.org/viewvc/llvm-project?rev=105489&view=rev
Log:
Initial support for ARM NEON builtins, codegen up next
Modified:
cfe/trunk/include/clang/Basic/BuiltinsARM.def
cfe/trunk/lib/Headers/arm_neon.td
Modified: cfe/trunk/include/clang/Basic/BuiltinsARM.def
URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/Basic/BuiltinsARM.def?rev=105489&r1=105488&r2=105489&view=diff
==============================================================================
--- cfe/trunk/include/clang/Basic/BuiltinsARM.def (original)
+++ cfe/trunk/include/clang/Basic/BuiltinsARM.def Fri Jun 4 16:36:27 2010
@@ -17,4 +17,293 @@
// FIXME: This is just a placeholder. NEON intrinsics should be listed here.
BUILTIN(__builtin_thread_pointer, "v*", "")
+// NEON
+BUILTIN(__builtin_neon_vaba_v, "V8cV8cV8cV8ci", "n")
+BUILTIN(__builtin_neon_vabaq_v, "V16cV16cV16cV16ci", "n")
+BUILTIN(__builtin_neon_vabal_v, "V16cV16cV8cV8ci", "n")
+BUILTIN(__builtin_neon_vabd_v, "V8cV8cV8ci", "n")
+BUILTIN(__builtin_neon_vabdq_v, "V16cV16cV16ci", "n")
+BUILTIN(__builtin_neon_vabdl_v, "V16cV8cV8ci", "n")
+BUILTIN(__builtin_neon_vabs_v, "V8cV8ci", "n")
+BUILTIN(__builtin_neon_vabsq_v, "V16cV16ci", "n")
+BUILTIN(__builtin_neon_vaddhn_v, "V8cV16cV16ci", "n")
+BUILTIN(__builtin_neon_vaddl_v, "V16cV8cV8ci", "n")
+BUILTIN(__builtin_neon_vaddw_v, "V16cV16cV8ci", "n")
+BUILTIN(__builtin_neon_vbsl_v, "V8cV8cV8cV8ci", "n")
+BUILTIN(__builtin_neon_vbslq_v, "V16cV16cV16cV16ci", "n")
+BUILTIN(__builtin_neon_vcage_v, "V8cV8cV8ci", "n")
+BUILTIN(__builtin_neon_vcageq_v, "V16cV16cV16ci", "n")
+BUILTIN(__builtin_neon_vcagt_v, "V8cV8cV8ci", "n")
+BUILTIN(__builtin_neon_vcagtq_v, "V16cV16cV16ci", "n")
+BUILTIN(__builtin_neon_vcale_v, "V8cV8cV8ci", "n")
+BUILTIN(__builtin_neon_vcaleq_v, "V16cV16cV16ci", "n")
+BUILTIN(__builtin_neon_vcalt_v, "V8cV8cV8ci", "n")
+BUILTIN(__builtin_neon_vcaltq_v, "V16cV16cV16ci", "n")
+BUILTIN(__builtin_neon_vcls_v, "V8cV8ci", "n")
+BUILTIN(__builtin_neon_vclsq_v, "V16cV16ci", "n")
+BUILTIN(__builtin_neon_vclz_v, "V8cV8ci", "n")
+BUILTIN(__builtin_neon_vclzq_v, "V16cV16ci", "n")
+BUILTIN(__builtin_neon_vcnt_v, "V8cV8ci", "n")
+BUILTIN(__builtin_neon_vcntq_v, "V16cV16ci", "n")
+BUILTIN(__builtin_neon_vcombine_v, "V16cV8cV8ci", "n")
+BUILTIN(__builtin_neon_vcvt_f16_v, "V8cV8ci", "n")
+BUILTIN(__builtin_neon_vcvt_f32_v, "V8cV8ci", "n")
+BUILTIN(__builtin_neon_vcvtq_f32_v, "V16cV16ci", "n")
+BUILTIN(__builtin_neon_vcvt_n_f32_v, "V8cV8cii", "n")
+BUILTIN(__builtin_neon_vcvtq_n_f32_v, "V16cV16cii", "n")
+BUILTIN(__builtin_neon_vcvt_n_s32_v, "V8cV8cii", "n")
+BUILTIN(__builtin_neon_vcvtq_n_s32_v, "V16cV16cii", "n")
+BUILTIN(__builtin_neon_vcvt_n_u32_v, "V8cV8cii", "n")
+BUILTIN(__builtin_neon_vcvtq_n_u32_v, "V16cV16cii", "n")
+BUILTIN(__builtin_neon_vcvt_s32_v, "V8cV8ci", "n")
+BUILTIN(__builtin_neon_vcvtq_s32_v, "V16cV16ci", "n")
+BUILTIN(__builtin_neon_vcvt_u32_v, "V8cV8ci", "n")
+BUILTIN(__builtin_neon_vcvtq_u32_v, "V16cV16ci", "n")
+BUILTIN(__builtin_neon_vdup_n_i8, "V8cUc", "n")
+BUILTIN(__builtin_neon_vdup_n_i16, "V8cUs", "n")
+BUILTIN(__builtin_neon_vdup_n_i32, "V8cUi", "n")
+BUILTIN(__builtin_neon_vdup_n_f32, "V8cf", "n")
+BUILTIN(__builtin_neon_vdupq_n_i8, "V16cUc", "n")
+BUILTIN(__builtin_neon_vdupq_n_i16, "V16cUs", "n")
+BUILTIN(__builtin_neon_vdupq_n_i32, "V16cUi", "n")
+BUILTIN(__builtin_neon_vdupq_n_f32, "V16cf", "n")
+BUILTIN(__builtin_neon_vdup_n_i64, "V8cULLi", "n")
+BUILTIN(__builtin_neon_vdupq_n_i64, "V16cULLi", "n")
+BUILTIN(__builtin_neon_vext_v, "V8cV8cV8cii", "n")
+BUILTIN(__builtin_neon_vextq_v, "V16cV16cV16cii", "n")
+BUILTIN(__builtin_neon_vget_high_v, "V8cV16ci", "n")
+BUILTIN(__builtin_neon_vget_lane_i8, "UcV8ci", "n")
+BUILTIN(__builtin_neon_vget_lane_i16, "UsV8ci", "n")
+BUILTIN(__builtin_neon_vget_lane_i32, "UiV8ci", "n")
+BUILTIN(__builtin_neon_vget_lane_f32, "fV8ci", "n")
+BUILTIN(__builtin_neon_vgetq_lane_i8, "UcV16ci", "n")
+BUILTIN(__builtin_neon_vgetq_lane_i16, "UsV16ci", "n")
+BUILTIN(__builtin_neon_vgetq_lane_i32, "UiV16ci", "n")
+BUILTIN(__builtin_neon_vgetq_lane_f32, "fV16ci", "n")
+BUILTIN(__builtin_neon_vget_lane_i64, "ULLiV8ci", "n")
+BUILTIN(__builtin_neon_vgetq_lane_i64, "ULLiV16ci", "n")
+BUILTIN(__builtin_neon_vget_low_v, "V8cV16ci", "n")
+BUILTIN(__builtin_neon_vhadd_v, "V8cV8cV8ci", "n")
+BUILTIN(__builtin_neon_vhaddq_v, "V16cV16cV16ci", "n")
+BUILTIN(__builtin_neon_vhsub_v, "V8cV8cV8ci", "n")
+BUILTIN(__builtin_neon_vhsubq_v, "V16cV16cV16ci", "n")
+BUILTIN(__builtin_neon_vld1q_v, "V16cvC*i", "n")
+BUILTIN(__builtin_neon_vld1_v, "V8cvC*i", "n")
+BUILTIN(__builtin_neon_vld1q_dup_v, "V16cvC*i", "n")
+BUILTIN(__builtin_neon_vld1_dup_v, "V8cvC*i", "n")
+BUILTIN(__builtin_neon_vld1q_lane_v, "V16cvC*ii", "n")
+BUILTIN(__builtin_neon_vld1_lane_v, "V8cvC*ii", "n")
+BUILTIN(__builtin_neon_vld2q_v, "V32cvC*i", "n")
+BUILTIN(__builtin_neon_vld2_v, "V16cvC*i", "n")
+BUILTIN(__builtin_neon_vld2_dup_v, "V16cvC*i", "n")
+BUILTIN(__builtin_neon_vld2q_lane_v, "V32cvC*ii", "n")
+BUILTIN(__builtin_neon_vld2_lane_v, "V16cvC*ii", "n")
+BUILTIN(__builtin_neon_vld3q_v, "V48cvC*i", "n")
+BUILTIN(__builtin_neon_vld3_v, "V24cvC*i", "n")
+BUILTIN(__builtin_neon_vld3_dup_v, "V24cvC*i", "n")
+BUILTIN(__builtin_neon_vld3q_lane_v, "V48cvC*ii", "n")
+BUILTIN(__builtin_neon_vld3_lane_v, "V24cvC*ii", "n")
+BUILTIN(__builtin_neon_vld4q_v, "V64cvC*i", "n")
+BUILTIN(__builtin_neon_vld4_v, "V32cvC*i", "n")
+BUILTIN(__builtin_neon_vld4_dup_v, "V32cvC*i", "n")
+BUILTIN(__builtin_neon_vld4q_lane_v, "V64cvC*ii", "n")
+BUILTIN(__builtin_neon_vld4_lane_v, "V32cvC*ii", "n")
+BUILTIN(__builtin_neon_vmax_v, "V8cV8cV8ci", "n")
+BUILTIN(__builtin_neon_vmaxq_v, "V16cV16cV16ci", "n")
+BUILTIN(__builtin_neon_vmin_v, "V8cV8cV8ci", "n")
+BUILTIN(__builtin_neon_vminq_v, "V16cV16cV16ci", "n")
+BUILTIN(__builtin_neon_vmlal_v, "V16cV16cV8cV8ci", "n")
+BUILTIN(__builtin_neon_vmlal_lane_v, "V16cV16cV8cV8cii", "n")
+BUILTIN(__builtin_neon_vmlal_n_s16, "V16cV16cV8cs", "n")
+BUILTIN(__builtin_neon_vmlal_n_s32, "V16cV16cV8ci", "n")
+BUILTIN(__builtin_neon_vmlal_n_u16, "V16cV16cV8cUs", "n")
+BUILTIN(__builtin_neon_vmlal_n_u32, "V16cV16cV8cUi", "n")
+BUILTIN(__builtin_neon_vmla_lane_v, "V8cV8cV8cV8cii", "n")
+BUILTIN(__builtin_neon_vmlaq_lane_v, "V16cV16cV16cV16cii", "n")
+BUILTIN(__builtin_neon_vmla_n_i16, "V8cV8cV8cUs", "n")
+BUILTIN(__builtin_neon_vmla_n_i32, "V8cV8cV8cUi", "n")
+BUILTIN(__builtin_neon_vmla_n_f32, "V8cV8cV8cf", "n")
+BUILTIN(__builtin_neon_vmlaq_n_i16, "V16cV16cV16cUs", "n")
+BUILTIN(__builtin_neon_vmlaq_n_i32, "V16cV16cV16cUi", "n")
+BUILTIN(__builtin_neon_vmlaq_n_f32, "V16cV16cV16cf", "n")
+BUILTIN(__builtin_neon_vmlsl_v, "V16cV16cV8cV8ci", "n")
+BUILTIN(__builtin_neon_vmlsl_lane_v, "V16cV16cV8cV8cii", "n")
+BUILTIN(__builtin_neon_vmlsl_n_s16, "V16cV16cV8cs", "n")
+BUILTIN(__builtin_neon_vmlsl_n_s32, "V16cV16cV8ci", "n")
+BUILTIN(__builtin_neon_vmlsl_n_u16, "V16cV16cV8cUs", "n")
+BUILTIN(__builtin_neon_vmlsl_n_u32, "V16cV16cV8cUi", "n")
+BUILTIN(__builtin_neon_vmls_lane_v, "V8cV8cV8cV8cii", "n")
+BUILTIN(__builtin_neon_vmlsq_lane_v, "V16cV16cV16cV16cii", "n")
+BUILTIN(__builtin_neon_vmls_n_i16, "V8cV8cV8cUs", "n")
+BUILTIN(__builtin_neon_vmls_n_i32, "V8cV8cV8cUi", "n")
+BUILTIN(__builtin_neon_vmls_n_f32, "V8cV8cV8cf", "n")
+BUILTIN(__builtin_neon_vmlsq_n_i16, "V16cV16cV16cUs", "n")
+BUILTIN(__builtin_neon_vmlsq_n_i32, "V16cV16cV16cUi", "n")
+BUILTIN(__builtin_neon_vmlsq_n_f32, "V16cV16cV16cf", "n")
+BUILTIN(__builtin_neon_vmovl_v, "V16cV8ci", "n")
+BUILTIN(__builtin_neon_vmovn_v, "V8cV16ci", "n")
+BUILTIN(__builtin_neon_vmov_n_i8, "V8cUc", "n")
+BUILTIN(__builtin_neon_vmov_n_i16, "V8cUs", "n")
+BUILTIN(__builtin_neon_vmov_n_i32, "V8cUi", "n")
+BUILTIN(__builtin_neon_vmov_n_f32, "V8cf", "n")
+BUILTIN(__builtin_neon_vmovq_n_i8, "V16cUc", "n")
+BUILTIN(__builtin_neon_vmovq_n_i16, "V16cUs", "n")
+BUILTIN(__builtin_neon_vmovq_n_i32, "V16cUi", "n")
+BUILTIN(__builtin_neon_vmovq_n_f32, "V16cf", "n")
+BUILTIN(__builtin_neon_vmov_n_i64, "V8cULLi", "n")
+BUILTIN(__builtin_neon_vmovq_n_i64, "V16cULLi", "n")
+BUILTIN(__builtin_neon_vmull_v, "V16cV8cV8ci", "n")
+BUILTIN(__builtin_neon_vmull_lane_v, "V16cV8cV8cii", "n")
+BUILTIN(__builtin_neon_vmull_n_s16, "V16cV8cs", "n")
+BUILTIN(__builtin_neon_vmull_n_s32, "V16cV8ci", "n")
+BUILTIN(__builtin_neon_vmull_n_u16, "V16cV8cUs", "n")
+BUILTIN(__builtin_neon_vmull_n_u32, "V16cV8cUi", "n")
+BUILTIN(__builtin_neon_vmul_n_i16, "V8cV8cUs", "n")
+BUILTIN(__builtin_neon_vmul_n_i32, "V8cV8cUi", "n")
+BUILTIN(__builtin_neon_vmul_n_f32, "V8cV8cf", "n")
+BUILTIN(__builtin_neon_vmulq_n_i16, "V16cV16cUs", "n")
+BUILTIN(__builtin_neon_vmulq_n_i32, "V16cV16cUi", "n")
+BUILTIN(__builtin_neon_vmulq_n_f32, "V16cV16cf", "n")
+BUILTIN(__builtin_neon_vpadal_v, "V8cV8cV8ci", "n")
+BUILTIN(__builtin_neon_vpadalq_v, "V16cV16cV16ci", "n")
+BUILTIN(__builtin_neon_vpadd_v, "V8cV8cV8ci", "n")
+BUILTIN(__builtin_neon_vpaddl_v, "V8cV8ci", "n")
+BUILTIN(__builtin_neon_vpaddlq_v, "V16cV16ci", "n")
+BUILTIN(__builtin_neon_vpmax_v, "V8cV8cV8ci", "n")
+BUILTIN(__builtin_neon_vpmin_v, "V8cV8cV8ci", "n")
+BUILTIN(__builtin_neon_vqabs_v, "V8cV8ci", "n")
+BUILTIN(__builtin_neon_vqabsq_v, "V16cV16ci", "n")
+BUILTIN(__builtin_neon_vqadd_v, "V8cV8cV8ci", "n")
+BUILTIN(__builtin_neon_vqaddq_v, "V16cV16cV16ci", "n")
+BUILTIN(__builtin_neon_vqdmlal_v, "V16cV16cV8cV8ci", "n")
+BUILTIN(__builtin_neon_vqdmlal_lane_v, "V16cV16cV8cV8cii", "n")
+BUILTIN(__builtin_neon_vqdmlal_n_s16, "V16cV16cV8cs", "n")
+BUILTIN(__builtin_neon_vqdmlal_n_s32, "V16cV16cV8ci", "n")
+BUILTIN(__builtin_neon_vqdmlsl_v, "V16cV16cV8cV8ci", "n")
+BUILTIN(__builtin_neon_vqdmlsl_lane_v, "V16cV16cV8cV8cii", "n")
+BUILTIN(__builtin_neon_vqdmlsl_n_s16, "V16cV16cV8cs", "n")
+BUILTIN(__builtin_neon_vqdmlsl_n_s32, "V16cV16cV8ci", "n")
+BUILTIN(__builtin_neon_vqdmulh_v, "V8cV8cV8ci", "n")
+BUILTIN(__builtin_neon_vqdmulhq_v, "V16cV16cV16ci", "n")
+BUILTIN(__builtin_neon_vqdmulh_lane_v, "V8cV8cV8cii", "n")
+BUILTIN(__builtin_neon_vqdmulhq_lane_v, "V16cV16cV16cii", "n")
+BUILTIN(__builtin_neon_vqdmulh_n_s16, "V8cV8cs", "n")
+BUILTIN(__builtin_neon_vqdmulh_n_s32, "V8cV8ci", "n")
+BUILTIN(__builtin_neon_vqdmulhq_n_s16, "V16cV16cs", "n")
+BUILTIN(__builtin_neon_vqdmulhq_n_s32, "V16cV16ci", "n")
+BUILTIN(__builtin_neon_vqdmull_v, "V16cV8cV8ci", "n")
+BUILTIN(__builtin_neon_vqdmull_lane_v, "V16cV8cV8cii", "n")
+BUILTIN(__builtin_neon_vqdmull_n_s16, "V16cV8cs", "n")
+BUILTIN(__builtin_neon_vqdmull_n_s32, "V16cV8ci", "n")
+BUILTIN(__builtin_neon_vqmovn_v, "V8cV16ci", "n")
+BUILTIN(__builtin_neon_vqmovun_v, "V8cV16ci", "n")
+BUILTIN(__builtin_neon_vqneg_v, "V8cV8ci", "n")
+BUILTIN(__builtin_neon_vqnegq_v, "V16cV16ci", "n")
+BUILTIN(__builtin_neon_vqrdmulh_v, "V8cV8cV8ci", "n")
+BUILTIN(__builtin_neon_vqrdmulhq_v, "V16cV16cV16ci", "n")
+BUILTIN(__builtin_neon_vqrdmulh_lane_v, "V8cV8cV8cii", "n")
+BUILTIN(__builtin_neon_vqrdmulhq_lane_v, "V16cV16cV16cii", "n")
+BUILTIN(__builtin_neon_vqrdmulh_n_s16, "V8cV8cs", "n")
+BUILTIN(__builtin_neon_vqrdmulh_n_s32, "V8cV8ci", "n")
+BUILTIN(__builtin_neon_vqrdmulhq_n_s16, "V16cV16cs", "n")
+BUILTIN(__builtin_neon_vqrdmulhq_n_s32, "V16cV16ci", "n")
+BUILTIN(__builtin_neon_vqrshl_v, "V8cV8cV8ci", "n")
+BUILTIN(__builtin_neon_vqrshlq_v, "V16cV16cV16ci", "n")
+BUILTIN(__builtin_neon_vqrshrn_n_v, "V8cV16cii", "n")
+BUILTIN(__builtin_neon_vqrshrun_n_v, "V8cV16cii", "n")
+BUILTIN(__builtin_neon_vqshl_v, "V8cV8cV8ci", "n")
+BUILTIN(__builtin_neon_vqshlq_v, "V16cV16cV16ci", "n")
+BUILTIN(__builtin_neon_vqshlu_n_v, "V8cV8cii", "n")
+BUILTIN(__builtin_neon_vqshluq_n_v, "V16cV16cii", "n")
+BUILTIN(__builtin_neon_vqshl_n_v, "V8cV8cii", "n")
+BUILTIN(__builtin_neon_vqshlq_n_v, "V16cV16cii", "n")
+BUILTIN(__builtin_neon_vqshrn_n_v, "V8cV16cii", "n")
+BUILTIN(__builtin_neon_vqshrun_n_v, "V8cV16cii", "n")
+BUILTIN(__builtin_neon_vqsub_v, "V8cV8cV8ci", "n")
+BUILTIN(__builtin_neon_vqsubq_v, "V16cV16cV16ci", "n")
+BUILTIN(__builtin_neon_vraddhn_v, "V8cV16cV16ci", "n")
+BUILTIN(__builtin_neon_vrecpe_v, "V8cV8ci", "n")
+BUILTIN(__builtin_neon_vrecpeq_v, "V16cV16ci", "n")
+BUILTIN(__builtin_neon_vrecps_v, "V8cV8cV8ci", "n")
+BUILTIN(__builtin_neon_vrecpsq_v, "V16cV16cV16ci", "n")
+BUILTIN(__builtin_neon_vrev16_v, "V8cV8ci", "n")
+BUILTIN(__builtin_neon_vrev16q_v, "V16cV16ci", "n")
+BUILTIN(__builtin_neon_vrev32_v, "V8cV8ci", "n")
+BUILTIN(__builtin_neon_vrev32q_v, "V16cV16ci", "n")
+BUILTIN(__builtin_neon_vrev64_v, "V8cV8ci", "n")
+BUILTIN(__builtin_neon_vrev64q_v, "V16cV16ci", "n")
+BUILTIN(__builtin_neon_vrhadd_v, "V8cV8cV8ci", "n")
+BUILTIN(__builtin_neon_vrhaddq_v, "V16cV16cV16ci", "n")
+BUILTIN(__builtin_neon_vrshl_v, "V8cV8cV8ci", "n")
+BUILTIN(__builtin_neon_vrshlq_v, "V16cV16cV16ci", "n")
+BUILTIN(__builtin_neon_vrshrn_n_v, "V8cV16cii", "n")
+BUILTIN(__builtin_neon_vrshr_n_v, "V8cV8cii", "n")
+BUILTIN(__builtin_neon_vrshrq_n_v, "V16cV16cii", "n")
+BUILTIN(__builtin_neon_vrsqrte_v, "V8cV8ci", "n")
+BUILTIN(__builtin_neon_vrsqrteq_v, "V16cV16ci", "n")
+BUILTIN(__builtin_neon_vrsqrts_v, "V8cV8cV8ci", "n")
+BUILTIN(__builtin_neon_vrsqrtsq_v, "V16cV16cV16ci", "n")
+BUILTIN(__builtin_neon_vrsra_n_v, "V8cV8cV8cii", "n")
+BUILTIN(__builtin_neon_vrsraq_n_v, "V16cV16cV16cii", "n")
+BUILTIN(__builtin_neon_vrsubhn_v, "V8cV16cV16ci", "n")
+BUILTIN(__builtin_neon_vset_lane_i8, "V8cUcV8ci", "n")
+BUILTIN(__builtin_neon_vset_lane_i16, "V8cUsV8ci", "n")
+BUILTIN(__builtin_neon_vset_lane_i32, "V8cUiV8ci", "n")
+BUILTIN(__builtin_neon_vset_lane_f32, "V8cfV8ci", "n")
+BUILTIN(__builtin_neon_vsetq_lane_i8, "V16cUcV16ci", "n")
+BUILTIN(__builtin_neon_vsetq_lane_i16, "V16cUsV16ci", "n")
+BUILTIN(__builtin_neon_vsetq_lane_i32, "V16cUiV16ci", "n")
+BUILTIN(__builtin_neon_vsetq_lane_f32, "V16cfV16ci", "n")
+BUILTIN(__builtin_neon_vset_lane_i64, "V8cULLiV8ci", "n")
+BUILTIN(__builtin_neon_vsetq_lane_i64, "V16cULLiV16ci", "n")
+BUILTIN(__builtin_neon_vshl_v, "V8cV8cV8ci", "n")
+BUILTIN(__builtin_neon_vshlq_v, "V16cV16cV16ci", "n")
+BUILTIN(__builtin_neon_vshll_n_v, "V16cV8cii", "n")
+BUILTIN(__builtin_neon_vshl_n_v, "V8cV8cii", "n")
+BUILTIN(__builtin_neon_vshlq_n_v, "V16cV16cii", "n")
+BUILTIN(__builtin_neon_vshrn_n_v, "V8cV16cii", "n")
+BUILTIN(__builtin_neon_vshr_n_v, "V8cV8cii", "n")
+BUILTIN(__builtin_neon_vshrq_n_v, "V16cV16cii", "n")
+BUILTIN(__builtin_neon_vsli_n_v, "V8cV8cV8cii", "n")
+BUILTIN(__builtin_neon_vsliq_n_v, "V16cV16cV16cii", "n")
+BUILTIN(__builtin_neon_vsra_n_v, "V8cV8cV8cii", "n")
+BUILTIN(__builtin_neon_vsraq_n_v, "V16cV16cV16cii", "n")
+BUILTIN(__builtin_neon_vsri_n_v, "V8cV8cV8cii", "n")
+BUILTIN(__builtin_neon_vsriq_n_v, "V16cV16cV16cii", "n")
+BUILTIN(__builtin_neon_vst1q_v, "vv*V16ci", "n")
+BUILTIN(__builtin_neon_vst1_v, "vv*V8ci", "n")
+BUILTIN(__builtin_neon_vst1q_lane_v, "vv*V16cii", "n")
+BUILTIN(__builtin_neon_vst1_lane_v, "vv*V8cii", "n")
+BUILTIN(__builtin_neon_vst2q_v, "vv*V16cV16ci", "n")
+BUILTIN(__builtin_neon_vst2_v, "vv*V8cV8ci", "n")
+BUILTIN(__builtin_neon_vst2q_lane_v, "vv*V16cV16cii", "n")
+BUILTIN(__builtin_neon_vst2_lane_v, "vv*V8cV8cii", "n")
+BUILTIN(__builtin_neon_vst3q_v, "vv*V16cV16cV16ci", "n")
+BUILTIN(__builtin_neon_vst3_v, "vv*V8cV8cV8ci", "n")
+BUILTIN(__builtin_neon_vst3q_lane_v, "vv*V16cV16cV16cii", "n")
+BUILTIN(__builtin_neon_vst3_lane_v, "vv*V8cV8cV8cii", "n")
+BUILTIN(__builtin_neon_vst4q_v, "vv*V16cV16cV16cV16ci", "n")
+BUILTIN(__builtin_neon_vst4_v, "vv*V8cV8cV8cV8ci", "n")
+BUILTIN(__builtin_neon_vst4q_lane_v, "vv*V16cV16cV16cV16cii", "n")
+BUILTIN(__builtin_neon_vst4_lane_v, "vv*V8cV8cV8cV8cii", "n")
+BUILTIN(__builtin_neon_vsubhn_v, "V8cV16cV16ci", "n")
+BUILTIN(__builtin_neon_vsubl_v, "V16cV8cV8ci", "n")
+BUILTIN(__builtin_neon_vsubw_v, "V16cV16cV8ci", "n")
+BUILTIN(__builtin_neon_vtbl1_v, "V8cV8cV8ci", "n")
+BUILTIN(__builtin_neon_vtbl2_v, "V8cV8cV8cV8ci", "n")
+BUILTIN(__builtin_neon_vtbl3_v, "V8cV8cV8cV8cV8ci", "n")
+BUILTIN(__builtin_neon_vtbl4_v, "V8cV8cV8cV8cV8cV8ci", "n")
+BUILTIN(__builtin_neon_vtbx1_v, "V8cV8cV8cV8ci", "n")
+BUILTIN(__builtin_neon_vtbx2_v, "V8cV8cV8cV8cV8ci", "n")
+BUILTIN(__builtin_neon_vtbx3_v, "V8cV8cV8cV8cV8cV8ci", "n")
+BUILTIN(__builtin_neon_vtbx4_v, "V8cV8cV8cV8cV8cV8cV8ci", "n")
+BUILTIN(__builtin_neon_vtrn_v, "V16cV8cV8ci", "n")
+BUILTIN(__builtin_neon_vtrnq_v, "V32cV16cV16ci", "n")
+BUILTIN(__builtin_neon_vtst_v, "V8cV8cV8ci", "n")
+BUILTIN(__builtin_neon_vtstq_v, "V16cV16cV16ci", "n")
+BUILTIN(__builtin_neon_vuzp_v, "V16cV8cV8ci", "n")
+BUILTIN(__builtin_neon_vuzpq_v, "V32cV16cV16ci", "n")
+BUILTIN(__builtin_neon_vzip_v, "V16cV8cV8ci", "n")
+BUILTIN(__builtin_neon_vzipq_v, "V32cV16cV16ci", "n")
+
#undef BUILTIN
Modified: cfe/trunk/lib/Headers/arm_neon.td
URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Headers/arm_neon.td?rev=105489&r1=105488&r2=105489&view=diff
==============================================================================
--- cfe/trunk/lib/Headers/arm_neon.td (original)
+++ cfe/trunk/lib/Headers/arm_neon.td Fri Jun 4 16:36:27 2010
@@ -210,12 +210,11 @@
////////////////////////////////////////////////////////////////////////////////
// E.3.16 Extract lanes from a vector
-// FIXME: need to test sign/zero-extractness
-def VGET_LANE : WInst<"sdi", "UcUsUicsiPcPsfQUcQUsQUiQcQsQiQPcQPsQflUlQlQUl">;
+def VGET_LANE : IInst<"sdi", "UcUsUicsiPcPsfQUcQUsQUiQcQsQiQPcQPsQflUlQlQUl">;
////////////////////////////////////////////////////////////////////////////////
// E.3.17 Set lanes within a vector
-def VSET_LANE : WInst<"dsdi", "UcUsUicsiPcPsfQUcQUsQUiQcQsQiQPcQPsQflUlQlQUl">;
+def VSET_LANE : IInst<"dsdi", "UcUsUicsiPcPsfQUcQUsQUiQcQsQiQPcQPsQflUlQlQUl">;
////////////////////////////////////////////////////////////////////////////////
// E.3.18 Initialize a vector from bit pattern
@@ -223,8 +222,8 @@
////////////////////////////////////////////////////////////////////////////////
// E.3.19 Set all lanes to same value
-def VDUP_N : WInst<"ds", "UcUsUicsiPcPsfQUcQUsQUiQcQsQiQPcQPsQflUlQlQUl">;
-def VMOV_N : WInst<"ds", "UcUsUicsiPcPsfQUcQUsQUiQcQsQiQPcQPsQflUlQlQUl">;
+def VDUP_N : IInst<"ds", "UcUsUicsiPcPsfQUcQUsQUiQcQsQiQPcQPsQflUlQlQUl">;
+def VMOV_N : IInst<"ds", "UcUsUicsiPcPsfQUcQUsQUiQcQsQiQPcQPsQflUlQlQUl">;
////////////////////////////////////////////////////////////////////////////////
// E.3.20 Combining vectors
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