[cfe-commits] r105417 - /cfe/trunk/lib/Headers/arm_neon.td
Nate Begeman
natebegeman at mac.com
Thu Jun 3 14:36:23 PDT 2010
Author: sampo
Date: Thu Jun 3 16:36:23 2010
New Revision: 105417
URL: http://llvm.org/viewvc/llvm-project?rev=105417&view=rev
Log:
Classify NEON intrinsics by overloading-type for codegen
Add a few missing instructions
Modified:
cfe/trunk/lib/Headers/arm_neon.td
Modified: cfe/trunk/lib/Headers/arm_neon.td
URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Headers/arm_neon.td?rev=105417&r1=105416&r2=105417&view=diff
==============================================================================
--- cfe/trunk/lib/Headers/arm_neon.td (original)
+++ cfe/trunk/lib/Headers/arm_neon.td Thu Jun 3 16:36:23 2010
@@ -32,13 +32,20 @@
def OP_XOR : Op;
def OP_ANDN : Op;
def OP_ORN : Op;
+def OP_CAST : Op;
-class Inst <string p, string t, Op o = OP_NONE> {
+class Inst <string p, string t, Op o> {
string Prototype = p;
string Types = t;
Op Operand = o;
}
+// Used to generate Builtins.def
+class SInst<string p, string t> : Inst<p, t, OP_NONE> {}
+class IInst<string p, string t> : Inst<p, t, OP_NONE> {}
+class WInst<string p, string t> : Inst<p, t, OP_NONE> {}
+class BInst<string p, string t> : Inst<p, t, OP_NONE> {}
+
// prototype: return (arg, arg, ...)
// v: void
// t: best-fit integer (int/poly args)
@@ -47,6 +54,8 @@
// d: default
// w: double width elements, same num elts
// n: double width elements, half num elts
+// h: half width elements, double num elts
+// e: half width elements, double num elts, unsigned
// i: constant int
// l: constant uint64
// s: scalar of element type
@@ -71,37 +80,37 @@
////////////////////////////////////////////////////////////////////////////////
// E.3.1 Addition
def VADD : Inst<"ddd", "csilfUcUsUiUlQcQsQiQlQfQUcQUsQUiQUl", OP_ADD>;
-def VADDL : Inst<"wdd", "csiUcUsUi">;
-def VADDw : Inst<"wwd", "csiUcUsUi">;
-def VHADD : Inst<"ddd", "csiUcUsUiQcQsQiQUcQUsQUi">;
-def VRHADD : Inst<"ddd", "csiUcUsUiQcQsQiQUcQUsQUi">;
-def VQADD : Inst<"ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
-def VADDHN : Inst<"dww", "csiUcUsUi">;
-def VRADDHN : Inst<"dww", "csiUcUsUi">;
+def VADDL : SInst<"wdd", "csiUcUsUi">;
+def VADDW : SInst<"wwd", "csiUcUsUi">;
+def VHADD : SInst<"ddd", "csiUcUsUiQcQsQiQUcQUsQUi">;
+def VRHADD : SInst<"ddd", "csiUcUsUiQcQsQiQUcQUsQUi">;
+def VQADD : SInst<"ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
+def VADDHN : IInst<"dww", "csiUcUsUi">;
+def VRADDHN : IInst<"dww", "csiUcUsUi">;
////////////////////////////////////////////////////////////////////////////////
// E.3.2 Multiplication
def VMUL : Inst<"ddd", "csifUcUsUiPcQcQsQiQfQUcQUsQUiQPc", OP_MUL>;
def VMLA : Inst<"dddd", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_MLA>;
-def VMLAL : Inst<"wwdd", "csiUcUsUi">;
+def VMLAL : SInst<"wwdd", "csiUcUsUi">;
def VMLS : Inst<"dddd", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_MLS>;
-def VMLSL : Inst<"wwdd", "csiUcUsUi">;
-def VQDMULH : Inst<"ddd", "siQsQi">;
-def VQRDMULH : Inst<"ddd", "siQsQi">;
-def VQDMLAL : Inst<"wwdd", "si">;
-def VQDMLSL : Inst<"wwdd", "si">;
-def VMULL : Inst<"wdd", "csiUcUsUiPc">;
-def VQDMULL : Inst<"wdd", "si">;
+def VMLSL : SInst<"wwdd", "csiUcUsUi">;
+def VQDMULH : SInst<"ddd", "siQsQi">;
+def VQRDMULH : SInst<"ddd", "siQsQi">;
+def VQDMLAL : SInst<"wwdd", "si">;
+def VQDMLSL : SInst<"wwdd", "si">;
+def VMULL : SInst<"wdd", "csiUcUsUiPc">;
+def VQDMULL : SInst<"wdd", "si">;
////////////////////////////////////////////////////////////////////////////////
// E.3.3 Subtraction
def VSUB : Inst<"ddd", "csilfUcUsUiUlQcQsQiQlQfQUcQUsQUiQUl", OP_SUB>;
-def VSUBL : Inst<"wdd", "csiUcUsUi">;
-def VSUBw : Inst<"wwd", "csiUcUsUi">;
-def VQSUB : Inst<"ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
-def VHSUB : Inst<"ddd", "csiUcUsUiQcQsQiQUcQUsQUi">;
-def VSUBHN : Inst<"dww", "csiUcUsUi">;
-def VRSUBHN : Inst<"dww", "csiUcUsUi">;
+def VSUBL : SInst<"wdd", "csiUcUsUi">;
+def VSUBW : SInst<"wwd", "csiUcUsUi">;
+def VQSUB : SInst<"ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
+def VHSUB : SInst<"ddd", "csiUcUsUiQcQsQiQUcQUsQUi">;
+def VSUBHN : IInst<"dww", "csiUcUsUi">;
+def VRSUBHN : IInst<"dww", "csiUcUsUi">;
////////////////////////////////////////////////////////////////////////////////
// E.3.4 Comparison
@@ -110,202 +119,209 @@
def VCLE : Inst<"xdd", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_LE>;
def VCGT : Inst<"xdd", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_GT>;
def VCLT : Inst<"xdd", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_LT>;
-def VCAGE : Inst<"xdd", "fQf">;
-def VCALE : Inst<"xdd", "fQf">;
-def VCAGT : Inst<"xdd", "fQf">;
-def VCALT : Inst<"xdd", "fQf">;
-def VTST : Inst<"xdd", "csiUcUsUiPcQcQsQiQUcQUsQUiQPc">;
+def VCAGE : IInst<"xdd", "fQf">;
+def VCALE : IInst<"xdd", "fQf">;
+def VCAGT : IInst<"xdd", "fQf">;
+def VCALT : IInst<"xdd", "fQf">;
+def VTST : WInst<"xdd", "csiUcUsUiPcQcQsQiQUcQUsQUiQPc">;
////////////////////////////////////////////////////////////////////////////////
// E.3.5 Absolute Difference
-def VABD : Inst<"ddd", "csiUcUsUifQcQsQiQUcQUsQUiQf">;
-def VABDL : Inst<"wdd", "csiUcUsUi">;
-def VABA : Inst<"dddd", "csiUcUsUiQcQsQiQUcQUsQUi">;
-def VABAL : Inst<"wwdd", "csiUcUsUi">;
+def VABD : SInst<"ddd", "csiUcUsUifQcQsQiQUcQUsQUiQf">;
+def VABDL : SInst<"wdd", "csiUcUsUi">;
+def VABA : SInst<"dddd", "csiUcUsUiQcQsQiQUcQUsQUi">;
+def VABAL : SInst<"wwdd", "csiUcUsUi">;
////////////////////////////////////////////////////////////////////////////////
// E.3.6 Max/Min
-def VMAX : Inst<"ddd", "csiUcUsUifQcQsQiQUcQUsQUiQf">;
-def VMIN : Inst<"ddd", "csiUcUsUifQcQsQiQUcQUsQUiQf">;
+def VMAX : SInst<"ddd", "csiUcUsUifQcQsQiQUcQUsQUiQf">;
+def VMIN : SInst<"ddd", "csiUcUsUifQcQsQiQUcQUsQUiQf">;
////////////////////////////////////////////////////////////////////////////////
// E.3.7 Pairdise Addition
-def VPADD : Inst<"ddd", "csiUcUsUif">;
-def VPADDL : Inst<"nd", "csiUcUsUiQcQsQiQUcQUsQUi">;
-def VPADAL : Inst<"nnd", "csiUcUsUiQcQsQiQUcQUsQUi">;
+def VPADD : IInst<"ddd", "csiUcUsUif">;
+def VPADDL : SInst<"nd", "csiUcUsUiQcQsQiQUcQUsQUi">;
+def VPADAL : SInst<"nnd", "csiUcUsUiQcQsQiQUcQUsQUi">;
////////////////////////////////////////////////////////////////////////////////
// E.3.8-9 Folding Max/Min
-def VPMAX : Inst<"ddd", "csiUcUsUif">;
-def VPMIN : Inst<"ddd", "csiUcUsUif">;
+def VPMAX : SInst<"ddd", "csiUcUsUif">;
+def VPMIN : SInst<"ddd", "csiUcUsUif">;
////////////////////////////////////////////////////////////////////////////////
// E.3.10 Reciprocal/Sqrt
-def VRECPS : Inst<"ddd", "fQf">;
-def VRSQRTS : Inst<"ddd", "fQf">;
+def VRECPS : IInst<"ddd", "fQf">;
+def VRSQRTS : IInst<"ddd", "fQf">;
////////////////////////////////////////////////////////////////////////////////
// E.3.11 Shifts by signed variable
-def VSHL : Inst<"ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
-def VQSHL : Inst<"ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
-def VRSHL : Inst<"ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
-def VQRSHL : Inst<"ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
+def VSHL : SInst<"ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
+def VQSHL : SInst<"ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
+def VRSHL : SInst<"ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
+def VQRSHL : SInst<"ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
////////////////////////////////////////////////////////////////////////////////
// E.3.12 Shifts by constant
-def VSHR_N : Inst<"ddi", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
-def VSHL_N : Inst<"ddi", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
-def VRSHR_N : Inst<"ddi", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
-def VSRA_N : Inst<"dddi", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
-def VRSRA_N : Inst<"dddi", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
-def VQSHL_N : Inst<"ddi", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
-def VQSHLU_N : Inst<"xdi", "csilQcQsQiQl">;
-def VSHRN_N : Inst<"dwi", "csiUcUsUi">;
-def VQSHRUN_N : Inst<"xwi", "csi">;
-def VQRSHRUN_N : Inst<"xwi", "csi">;
-def VQSHRN_N : Inst<"dwi", "csiUcUsUi">;
-def VRSHRN_N : Inst<"dwi", "csiUcUsUi">;
-def VQRSHRN_N : Inst<"dwi", "csiUcUsUi">;
-def VSHLL_N : Inst<"wdi", "csiUcUsUi">;
+def VSHR_N : SInst<"ddi", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
+def VSHL_N : IInst<"ddi", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
+def VRSHR_N : SInst<"ddi", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
+def VSRA_N : SInst<"dddi", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
+def VRSRA_N : SInst<"dddi", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
+def VQSHL_N : SInst<"ddi", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
+def VQSHLU_N : SInst<"xdi", "csilQcQsQiQl">;
+def VSHRN_N : IInst<"dwi", "csiUcUsUi">;
+def VQSHRUN_N : SInst<"xwi", "csi">;
+def VQRSHRUN_N : SInst<"xwi", "csi">;
+def VQSHRN_N : SInst<"dwi", "csiUcUsUi">;
+def VRSHRN_N : IInst<"dwi", "csiUcUsUi">;
+def VQRSHRN_N : SInst<"dwi", "csiUcUsUi">;
+def VSHLL_N : SInst<"wdi", "csiUcUsUi">;
////////////////////////////////////////////////////////////////////////////////
// E.3.13 Shifts with insert
-def VSRI_N : Inst<"dddi", "csilUcUsUiUlPcPsQcQsQiQlQUcQUsQUiQUlQPcQPs">;
-def VSLI_N : Inst<"dddi", "csilUcUsUiUlPcPsQcQsQiQlQUcQUsQUiQUlQPcQPs">;
+def VSRI_N : WInst<"dddi", "csilUcUsUiUlPcPsQcQsQiQlQUcQUsQUiQUlQPcQPs">;
+def VSLI_N : WInst<"dddi", "csilUcUsUiUlPcPsQcQsQiQlQUcQUsQUiQUlQPcQPs">;
////////////////////////////////////////////////////////////////////////////////
// E.3.14 Loads and stores of a single vector
-def VLD1 : Inst<"dc", "QUcQUsQUiQUlQcQsQiQlQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
-def VLD1_LANE : Inst<"dci", "QUcQUsQUiQUlQcQsQiQlQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
-def VLD1_DUP : Inst<"dc", "QUcQUsQUiQUlQcQsQiQlQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
-def VST1 : Inst<"vpd", "QUcQUsQUiQUlQcQsQiQlQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
-def VST1_LANE : Inst<"vpdi", "QUcQUsQUiQUlQcQsQiQlQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
+def VLD1 : WInst<"dc", "QUcQUsQUiQUlQcQsQiQlQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
+def VLD1_LANE : WInst<"dci", "QUcQUsQUiQUlQcQsQiQlQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
+def VLD1_DUP : WInst<"dc", "QUcQUsQUiQUlQcQsQiQlQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
+def VST1 : WInst<"vpd", "QUcQUsQUiQUlQcQsQiQlQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
+def VST1_LANE : WInst<"vpdi", "QUcQUsQUiQUlQcQsQiQlQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
////////////////////////////////////////////////////////////////////////////////
// E.3.15 Loads and stores of an N-element structure
-def VLD2 : Inst<"2c", "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
-def VLD3 : Inst<"3c", "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
-def VLD4 : Inst<"4c", "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
-def VLD2_DUP : Inst<"2c", "UcUsUiUlcsilhfPcPs">;
-def VLD3_DUP : Inst<"3c", "UcUsUiUlcsilhfPcPs">;
-def VLD4_DUP : Inst<"4c", "UcUsUiUlcsilhfPcPs">;
-def VLD2_LANE : Inst<"2ci", "QUsQUiQsQiQhQfQPsUcUsUicsihfPcPs">;
-def VLD3_LANE : Inst<"3ci", "QUsQUiQsQiQhQfQPsUcUsUicsihfPcPs">;
-def VLD4_LANE : Inst<"4ci", "QUsQUiQsQiQhQfQPsUcUsUicsihfPcPs">;
-def VST2 : Inst<"vp2", "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
-def VST3 : Inst<"vp3", "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
-def VST4 : Inst<"vp4", "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
-def VST2_LANE : Inst<"vp2i", "QUsQUiQsQiQhQfQPsUcUsUicsihfPcPs">;
-def VST3_LANE : Inst<"vp3i", "QUsQUiQsQiQhQfQPsUcUsUicsihfPcPs">;
-def VST4_LANE : Inst<"vp4i", "QUsQUiQsQiQhQfQPsUcUsUicsihfPcPs">;
+def VLD2 : WInst<"2c", "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
+def VLD3 : WInst<"3c", "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
+def VLD4 : WInst<"4c", "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
+def VLD2_DUP : WInst<"2c", "UcUsUiUlcsilhfPcPs">;
+def VLD3_DUP : WInst<"3c", "UcUsUiUlcsilhfPcPs">;
+def VLD4_DUP : WInst<"4c", "UcUsUiUlcsilhfPcPs">;
+def VLD2_LANE : WInst<"2ci", "QUsQUiQsQiQhQfQPsUcUsUicsihfPcPs">;
+def VLD3_LANE : WInst<"3ci", "QUsQUiQsQiQhQfQPsUcUsUicsihfPcPs">;
+def VLD4_LANE : WInst<"4ci", "QUsQUiQsQiQhQfQPsUcUsUicsihfPcPs">;
+def VST2 : WInst<"vp2", "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
+def VST3 : WInst<"vp3", "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
+def VST4 : WInst<"vp4", "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
+def VST2_LANE : WInst<"vp2i", "QUsQUiQsQiQhQfQPsUcUsUicsihfPcPs">;
+def VST3_LANE : WInst<"vp3i", "QUsQUiQsQiQhQfQPsUcUsUicsihfPcPs">;
+def VST4_LANE : WInst<"vp4i", "QUsQUiQsQiQhQfQPsUcUsUicsihfPcPs">;
////////////////////////////////////////////////////////////////////////////////
// E.3.16 Extract lanes from a vector
-def VGET_LANE : Inst<"sdi", "UcUsUicsiPcPsfQUcQUsQUiQcQsQiQPcQPsQflUlQlQUl">;
+// FIXME: need to test sign/zero-extractness
+def VGET_LANE : WInst<"sdi", "UcUsUicsiPcPsfQUcQUsQUiQcQsQiQPcQPsQflUlQlQUl">;
////////////////////////////////////////////////////////////////////////////////
// E.3.17 Set lanes within a vector
-def VSET_LANE : Inst<"dsdi", "UcUsUicsiPcPsfQUcQUsQUiQcQsQiQPcQPsQflUlQlQUl">;
+def VSET_LANE : WInst<"dsdi", "UcUsUicsiPcPsfQUcQUsQUiQcQsQiQPcQPsQflUlQlQUl">;
////////////////////////////////////////////////////////////////////////////////
// E.3.18 Initialize a vector from bit pattern
-def VCREATE: Inst<"dl", "csihfUcUsUiUlPcPsl">;
+def VCREATE: Inst<"dl", "csihfUcUsUiUlPcPsl", OP_CAST>;
////////////////////////////////////////////////////////////////////////////////
// E.3.19 Set all lanes to same value
-def VDUP_N : Inst<"ds", "UcUsUicsiPcPsfQUcQUsQUiQcQsQiQPcQPsQflUlQlQUl">;
-def VMOV_N : Inst<"ds", "UcUsUicsiPcPsfQUcQUsQUiQcQsQiQPcQPsQflUlQlQUl">;
+def VDUP_N : WInst<"ds", "UcUsUicsiPcPsfQUcQUsQUiQcQsQiQPcQPsQflUlQlQUl">;
+def VMOV_N : WInst<"ds", "UcUsUicsiPcPsfQUcQUsQUiQcQsQiQPcQPsQflUlQlQUl">;
////////////////////////////////////////////////////////////////////////////////
// E.3.20 Combining vectors
-def VCOMBINE : Inst<"kdd", "csilhfUcUsUiUlPcPs">;
+def VCOMBINE : WInst<"kdd", "csilhfUcUsUiUlPcPs">;
////////////////////////////////////////////////////////////////////////////////
// E.3.21 Splitting vectors
-def VGET_HIGH : Inst<"dk", "csilhfUcUsUiUlPcPs">;
-def VGET_LOW : Inst<"dk", "csilhfUcUsUiUlPcPs">;
+def VGET_HIGH : WInst<"dk", "csilhfUcUsUiUlPcPs">;
+def VGET_LOW : WInst<"dk", "csilhfUcUsUiUlPcPs">;
////////////////////////////////////////////////////////////////////////////////
// E.3.22 Converting vectors
-def VCVT_S32 : Inst<"df", "iQi">;
-def VCVT_U32 : Inst<"df", "UiQUi">;
-def VCVT_F16 : Inst<"df", "h">;
-def VCVT_N_S32 : Inst<"dfi", "iQi">;
-def VCVT_N_U32 : Inst<"dfi", "UiQUi">;
-def VCVT_F32 : Inst<"fd", "iUiQiQUih">;
-def VCVT_N_F32 : Inst<"fdi", "iUiQiQUi">;
+// FIXME: vmovn, vqmovn, vqmovun have wrong suffixes.
+def VCVT_S32 : SInst<"df", "iQi">;
+def VCVT_U32 : SInst<"df", "UiQUi">;
+def VCVT_F16 : SInst<"df", "h">;
+def VCVT_N_S32 : SInst<"dfi", "iQi">;
+def VCVT_N_U32 : SInst<"dfi", "UiQUi">;
+def VCVT_F32 : SInst<"fd", "iUiQiQUih">;
+def VCVT_N_F32 : SInst<"fdi", "iUiQiQUi">;
+def VMOVN : IInst<"hk", "silUsUiUl">;
+def VMOVL : SInst<"wd", "csiUcUsUi">;
+def VQMOVN : SInst<"hk", "silUsUiUl">;
+def VQMOVUN : SInst<"ek", "sil">;
////////////////////////////////////////////////////////////////////////////////
// E.3.23-24 Table lookup, Extended table lookup
-def VTBL1 : Inst<"ddt", "UccPc">;
-def VTBL2 : Inst<"d2t", "UccPc">;
-def VTBL3 : Inst<"d3t", "UccPc">;
-def VTBL4 : Inst<"d4t", "UccPc">;
-def VTBX1 : Inst<"dddt", "UccPc">;
-def VTBX2 : Inst<"dd2t", "UccPc">;
-def VTBX3 : Inst<"dd3t", "UccPc">;
-def VTBX4 : Inst<"dd4t", "UccPc">;
+def VTBL1 : WInst<"ddt", "UccPc">;
+def VTBL2 : WInst<"d2t", "UccPc">;
+def VTBL3 : WInst<"d3t", "UccPc">;
+def VTBL4 : WInst<"d4t", "UccPc">;
+def VTBX1 : WInst<"dddt", "UccPc">;
+def VTBX2 : WInst<"dd2t", "UccPc">;
+def VTBX3 : WInst<"dd3t", "UccPc">;
+def VTBX4 : WInst<"dd4t", "UccPc">;
////////////////////////////////////////////////////////////////////////////////
// E.3.25 Operations with a scalar value
-def VMLA_LANE : Inst<"ddddi", "siUsUifQsQiQUsQUiQf">;
-def VMLAL_LANE : Inst<"wwddi", "siUsUi">;
-def VQDMLAL_LANE : Inst<"wwddi", "si">;
-def VMLS_LANE : Inst<"ddddi", "siUsUifQsQiQUsQUiQf">;
-def VMLSL_LANE : Inst<"wwddi", "siUsUi">;
-def VQDMLSL_LANE : Inst<"wwddi", "si">;
-def VMUL_N : Inst<"dds", "sifUsUiQsQiQfQUsQUi">;
-def VMULL_N : Inst<"wds", "siUsUi">;
-def VMULL_LANE : Inst<"wddi", "siUsUi">;
-def VQDMULL_N : Inst<"wds", "si">;
-def VQDMULL_LANE : Inst<"wddi", "si">;
-def VQDMULH_N : Inst<"dds", "siQsQi">;
-def VQDMULH_LANE : Inst<"dddi", "siQsQi">;
-def VQRDMULH_N : Inst<"dds", "siQsQi">;
-def VQRDMULH_LANE : Inst<"dddi", "siQsQi">;
-def VMLA_N : Inst<"ddds", "siUsUifQsQiQUsQUiQf">;
-def VQDMLAL_N : Inst<"wwds", "si">;
-def VMLS_N : Inst<"ddds", "siUsUifQsQiQUsQUiQf">;
-def VMLSL_N : Inst<"wwds", "siUsUi">;
-def VQDMLSL_N : Inst<"wwds", "si">;
+def VMLA_LANE : IInst<"ddddi", "siUsUifQsQiQUsQUiQf">;
+def VMLAL_LANE : SInst<"wwddi", "siUsUi">;
+def VQDMLAL_LANE : SInst<"wwddi", "si">;
+def VMLS_LANE : IInst<"ddddi", "siUsUifQsQiQUsQUiQf">;
+def VMLSL_LANE : SInst<"wwddi", "siUsUi">;
+def VQDMLSL_LANE : SInst<"wwddi", "si">;
+def VMUL_N : IInst<"dds", "sifUsUiQsQiQfQUsQUi">;
+def VMULL_N : SInst<"wds", "siUsUi">;
+def VMULL_LANE : SInst<"wddi", "siUsUi">;
+def VQDMULL_N : SInst<"wds", "si">;
+def VQDMULL_LANE : SInst<"wddi", "si">;
+def VQDMULH_N : SInst<"dds", "siQsQi">;
+def VQDMULH_LANE : SInst<"dddi", "siQsQi">;
+def VQRDMULH_N : SInst<"dds", "siQsQi">;
+def VQRDMULH_LANE : SInst<"dddi", "siQsQi">;
+def VMLA_N : IInst<"ddds", "siUsUifQsQiQUsQUiQf">;
+def VMLAL_N : SInst<"wwds", "siUsUi">;
+def VQDMLAL_N : SInst<"wwds", "si">;
+def VMLS_N : IInst<"ddds", "siUsUifQsQiQUsQUiQf">;
+def VMLSL_N : SInst<"wwds", "siUsUi">;
+def VQDMLSL_N : SInst<"wwds", "si">;
////////////////////////////////////////////////////////////////////////////////
// E.3.26 Vector Extract
-def VEXT : Inst<"dddi", "cUcPcsUsPsiUilUlQcQUcQPcQsQUsQPsQiQUiQlQUl">;
+def VEXT : WInst<"dddi", "cUcPcsUsPsiUilUlQcQUcQPcQsQUsQPsQiQUiQlQUl">;
////////////////////////////////////////////////////////////////////////////////
// E.3.27 Reverse vector elements (sdap endianness)
-def VREV64 : Inst<"dd", "csiUcUsUiPcPsfQcQsQiQUcQUsQUiQPcQPsQf">;
-def VREV32 : Inst<"dd", "csUcUsPcQcQsQUcQUsQPc">;
-def VREV16 : Inst<"dd", "cUcPcQcQUcQPc">;
+def VREV64 : WInst<"dd", "csiUcUsUiPcPsfQcQsQiQUcQUsQUiQPcQPsQf">;
+def VREV32 : WInst<"dd", "csUcUsPcQcQsQUcQUsQPc">;
+def VREV16 : WInst<"dd", "cUcPcQcQUcQPc">;
////////////////////////////////////////////////////////////////////////////////
// E.3.28 Other single operand arithmetic
-def VABS : Inst<"dd", "csifQcQsQiQf">;
-def VQABS : Inst<"dd", "csiQcQsQi">;
-def VNEG : Inst<"dd", "csifQcQsQiQf", OP_NEG>;
-def VQNEG : Inst<"dd", "csiQcQsQi">;
-def VCLS : Inst<"dd", "csiQcQsQi">;
-def VCLZ : Inst<"dd", "csiUcUsUiQcQsQiQUcQUsQUi">;
-def VCNT : Inst<"dd", "UccPcQUcQcQPc">;
-def VRECPE : Inst<"dd", "fUiQfQUi">;
-def VRSQRTE : Inst<"dd", "fUiQfQUi">;
+def VABS : SInst<"dd", "csifQcQsQiQf">;
+def VQABS : SInst<"dd", "csiQcQsQi">;
+def VNEG : Inst<"dd", "csifQcQsQiQf", OP_NEG>;
+def VQNEG : SInst<"dd", "csiQcQsQi">;
+def VCLS : SInst<"dd", "csiQcQsQi">;
+def VCLZ : IInst<"dd", "csiUcUsUiQcQsQiQUcQUsQUi">;
+def VCNT : WInst<"dd", "UccPcQUcQcQPc">;
+def VRECPE : SInst<"dd", "fUiQfQUi">;
+def VRSQRTE : SInst<"dd", "fUiQfQUi">;
////////////////////////////////////////////////////////////////////////////////
// E.3.29 Logical operations
-def VMVN : Inst<"dd", "csiUcUsUiPcQcQsQiQUcQUsQUiQPc", OP_NOT>;
-def VAND : Inst<"ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl", OP_AND>;
-def VORR : Inst<"ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl", OP_OR>;
-def VEOR : Inst<"ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl", OP_XOR>;
-def VBIC : Inst<"ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl", OP_ANDN>;
-def VORN : Inst<"ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl", OP_ORN>;
-def VBSL : Inst<"dxdd", "csilUcUsUiUlfPcPsQcQsQiQlQUcQUsQUiQUlQfQPcQPs">;
+def VMVN : Inst<"dd", "csiUcUsUiPcQcQsQiQUcQUsQUiQPc", OP_NOT>;
+def VAND : Inst<"ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl", OP_AND>;
+def VORR : Inst<"ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl", OP_OR>;
+def VEOR : Inst<"ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl", OP_XOR>;
+def VBIC : Inst<"ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl", OP_ANDN>;
+def VORN : Inst<"ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl", OP_ORN>;
+def VBSL : BInst<"dxdd", "csilUcUsUiUlfPcPsQcQsQiQlQUcQUsQUiQUlQfQPcQPs">;
////////////////////////////////////////////////////////////////////////////////
// E.3.30 Transposition operations
-def VTRN: Inst<"2dd", "csiUcUsUifPcPsQcQsQiQUcQUsQUiQfQPcQPs">;
-def VZIP: Inst<"2dd", "csUcUsfPcPsQcQsQiQUcQUsQUiQfQPcQPs">;
-def VUZP: Inst<"2dd", "csiUcUsUifPcPsQcQsQiQUcQUsQUiQfQPcQPs">;
+def VTRN: WInst<"2dd", "csiUcUsUifPcPsQcQsQiQUcQUsQUiQfQPcQPs">;
+def VZIP: WInst<"2dd", "csUcUsfPcPsQcQsQiQUcQUsQUiQfQPcQPs">;
+def VUZP: WInst<"2dd", "csiUcUsUifPcPsQcQsQiQUcQUsQUiQfQPcQPs">;
////////////////////////////////////////////////////////////////////////////////
// E.3.31 Vector reinterpret cast operations
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