[all-commits] [llvm/llvm-project] cad1ee: [Clang][RISCV] Add packed narrowing shift intrinsi...

Sat Oct 3 23:45:57 PDT 2026

  Branch: refs/heads/users/vitalybuka/spr/main.nfctsan-check-no-locks-are-held-in-entersymbolizer
  Home:   https://github.com/llvm/llvm-project
  Commit: cad1eecaac838c317e23ba2c4601408da4dcc3f5
      https://github.com/llvm/llvm-project/commit/cad1eecaac838c317e23ba2c4601408da4dcc3f5
  Author: 陈子昂 <2802328816 at qq.com>
  Date:   2026-10-04 (Sun, 04 Oct 2026)

  Changed paths:
    M clang/include/clang/Basic/BuiltinsRISCV.td
    M clang/lib/CodeGen/TargetBuiltins/RISCV.cpp
    M clang/lib/Headers/riscv_packed_simd.h
    M clang/test/CodeGen/RISCV/rvp-intrinsics.c
    M cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c
    M llvm/include/llvm/IR/IntrinsicsRISCV.td
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfoP.td
    A llvm/test/CodeGen/RISCV/rvp-narrowing-shift.ll

  Log Message:
  -----------
  [Clang][RISCV] Add packed narrowing shift intrinsics (#228726)

This patch adds the Packed Narrowing Shift intrinsics:

- `__riscv_pnsrl_s_u8x4`
- `__riscv_pnsrl_s_u16x2`
- `__riscv_pnsra_s_i8x4`
- `__riscv_pnsra_s_i16x2`
- `__riscv_pnsrar_s_i8x4`
- `__riscv_pnsrar_s_i16x2`

  Commit: 894dad791c0124915dcf6b5093744c9307cffaf2
      https://github.com/llvm/llvm-project/commit/894dad791c0124915dcf6b5093744c9307cffaf2
  Author: Jianhui Li <jian.hui.li at intel.com>
  Date:   2026-10-03 (Sat, 03 Oct 2026)

  Changed paths:
    M mlir/lib/Dialect/XeGPU/Transforms/XeGPULayoutImpl.cpp
    M mlir/lib/Dialect/XeGPU/Transforms/XeGPUPeepHoleOptimizer.cpp
    M mlir/lib/Dialect/XeGPU/Transforms/XeGPUSgToLaneDistribute.cpp
    M mlir/test/Dialect/XeGPU/propagate-layout-inst-data.mlir
    M mlir/test/Dialect/XeGPU/propagate-layout.mlir
    M mlir/test/Integration/Dialect/XeGPU/WG/simple_mxfp_gemm_quantizeA_F4.mlir

  Log Message:
  -----------
  [mlir][xegpu] Raise the reduction vector size to match maxReduceVectorSize (#225122)

`maxReduceVectorSize` was pinned at 1, so a lane reduced one element at
a time no
matter how much data it held. This raises it to 16 and makes the layout
computation actually spend it, so a lane's reduce vector matches the
per-lane
budget.

```cpp
-  int64_t maxReduceVectorSize = 1; // could extend to spirv vector Size
+  int64_t maxReduceVectorSize = 16; // extend to spirv vector Size
```

The PR only raises the vector size for the innermost dim, and only when
that dim is reduced and carries a single lane.

The reason we don't raise vector size for outer dim: Raising the vector
size for the outer dim means the vector may be strided in flat element
order. In case that the producer is a shape_cast op, it causes a
potential convert_layout after shape_cast which assumes all lane data to
be contiguous.

As we simplify propagation rule, the trade-off is that the rule is
conservative since we don't know the information about producer due to
the backward propagation.

---------

Co-authored-by: Claude Opus 5 (1M context) <noreply at anthropic.com>

  Commit: e3afe37ec59c4c5f689e2c92bd0b6f16cabf6fbf
      https://github.com/llvm/llvm-project/commit/e3afe37ec59c4c5f689e2c92bd0b6f16cabf6fbf
  Author: Fangrui Song <i at maskray.me>
  Date:   2026-10-03 (Sat, 03 Oct 2026)

  Changed paths:
    M clang-tools-extra/clangd/CompileCommands.cpp
    M llvm/include/llvm/Option/LibraryOptions.td
    M llvm/include/llvm/Option/OptParser.td
    M llvm/include/llvm/Option/Option.h
    M llvm/lib/Option/Arg.cpp
    M llvm/lib/Option/LibraryOptions.cpp
    M llvm/lib/Option/OptTable.cpp
    M llvm/lib/Option/Option.cpp
    M llvm/unittests/Option/LibraryOptionsTest.cpp
    M llvm/utils/TableGen/Basic/OptionParserEmitter.cpp

  Log Message:
  -----------
  [Option] Add FlagOrEq and SeparateOrEq option kinds (#228319)

FlagOrEq accepts -x and -x=v; SeparateOrEq accepts -x=v and -x v. The
name is stored without '=', and RenderEqStyle renders -x=v. BoolField
and ValueField use them, so a library option takes one table row instead
of a Joined twin plus a Flag or a Separate alias.

CGDataOptions.cpp.o shrinks from 4,977 to 4,370 bytes and
InstCombineCLOptions.cpp.o from 4,180 to 3,553.

Aided by Opus 5.5

  Commit: 6b4b4b1b1427950550b51746ce6c1c735d4b4b9b
      https://github.com/llvm/llvm-project/commit/6b4b4b1b1427950550b51746ce6c1c735d4b4b9b
  Author: Vitaly Buka <vitalybuka at google.com>
  Date:   2026-10-03 (Sat, 03 Oct 2026)

  Changed paths:
    M clang-tools-extra/clangd/CompileCommands.cpp
    M clang/include/clang/Basic/BuiltinsRISCV.td
    M clang/lib/CodeGen/TargetBuiltins/RISCV.cpp
    M clang/lib/Headers/riscv_packed_simd.h
    M clang/test/CodeGen/RISCV/rvp-intrinsics.c
    M cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c
    M llvm/include/llvm/IR/IntrinsicsRISCV.td
    M llvm/include/llvm/Option/LibraryOptions.td
    M llvm/include/llvm/Option/OptParser.td
    M llvm/include/llvm/Option/Option.h
    M llvm/lib/Option/Arg.cpp
    M llvm/lib/Option/LibraryOptions.cpp
    M llvm/lib/Option/OptTable.cpp
    M llvm/lib/Option/Option.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfoP.td
    A llvm/test/CodeGen/RISCV/rvp-narrowing-shift.ll
    M llvm/unittests/Option/LibraryOptionsTest.cpp
    M llvm/utils/TableGen/Basic/OptionParserEmitter.cpp
    M mlir/lib/Dialect/XeGPU/Transforms/XeGPULayoutImpl.cpp
    M mlir/lib/Dialect/XeGPU/Transforms/XeGPUPeepHoleOptimizer.cpp
    M mlir/lib/Dialect/XeGPU/Transforms/XeGPUSgToLaneDistribute.cpp
    M mlir/test/Dialect/XeGPU/propagate-layout-inst-data.mlir
    M mlir/test/Dialect/XeGPU/propagate-layout.mlir
    M mlir/test/Integration/Dialect/XeGPU/WG/simple_mxfp_gemm_quantizeA_F4.mlir

  Log Message:
  -----------
  [𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.7

[skip ci]

Compare: https://github.com/llvm/llvm-project/compare/d5349560d536...6b4b4b1b1427

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