[all-commits] [llvm/llvm-project] e0533e: CodeGen: Run LiveIntervals before PHIElimination a...

Fri Oct 2 16:34:27 PDT 2026

  Branch: refs/heads/users/arsenm/codegen/move-LiveIntervals-before-PHIElimination
  Home:   https://github.com/llvm/llvm-project
  Commit: e0533e972ecf13b03da70975be5ff9b91f24c69f
      https://github.com/llvm/llvm-project/commit/e0533e972ecf13b03da70975be5ff9b91f24c69f
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2026-10-03 (Sat, 03 Oct 2026)

  Changed paths:
    M llvm/lib/CodeGen/PHIElimination.cpp
    M llvm/lib/CodeGen/TargetPassConfig.cpp
    M llvm/lib/Passes/CodeGenPassBuilder.cpp
    M llvm/test/CodeGen/AArch64/O3-pipeline.ll
    M llvm/test/CodeGen/AArch64/PHIElimination-debugloc.mir
    M llvm/test/CodeGen/AArch64/atomic-ops-not-barriers.ll
    M llvm/test/CodeGen/AArch64/call-rv-marker.ll
    M llvm/test/CodeGen/AArch64/div-i256.ll
    M llvm/test/CodeGen/AArch64/phi.ll
    M llvm/test/CodeGen/AArch64/pr164181.ll
    M llvm/test/CodeGen/AArch64/ragreedy-local-interval-cost.ll
    M llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll
    M llvm/test/CodeGen/AMDGPU/llc-pipeline.ll
    M llvm/test/CodeGen/AMDGPU/phi-elim-mli-available.mir
    M llvm/test/CodeGen/AMDGPU/phi-elimination-assertion.mir
    M llvm/test/CodeGen/AMDGPU/phi-elimination-end-cf.mir
    M llvm/test/CodeGen/AMDGPU/waterfall-loop-exec-update-terminator.mir
    M llvm/test/CodeGen/ARM/O3-pipeline.ll
    M llvm/test/CodeGen/ARM/ParallelDSP/multi-use-loads.ll
    M llvm/test/CodeGen/ARM/aes-erratum-fix.ll
    M llvm/test/CodeGen/ARM/code-placement.ll
    M llvm/test/CodeGen/ARM/fp16-promote.ll
    M llvm/test/CodeGen/ARM/fpclamptosat.ll
    M llvm/test/CodeGen/ARM/fptoi-sat-store.ll
    M llvm/test/CodeGen/ARM/fptosi-sat-scalar.ll
    M llvm/test/CodeGen/ARM/fptoui-sat-scalar.ll
    M llvm/test/CodeGen/ARM/sat-to-bitop.ll
    M llvm/test/CodeGen/BPF/jump_table_blockaddr.ll
    M llvm/test/CodeGen/BPF/sockex2.ll
    M llvm/test/CodeGen/Hexagon/rdf-copy.ll
    M llvm/test/CodeGen/Hexagon/swp-matmul-bitext.ll
    M llvm/test/CodeGen/LoongArch/opt-pipeline.ll
    M llvm/test/CodeGen/NVPTX/switch-loop-header.mir
    M llvm/test/CodeGen/PowerPC/2013-07-01-PHIElimBug.mir
    M llvm/test/CodeGen/PowerPC/O3-pipeline.ll
    M llvm/test/CodeGen/PowerPC/all-atomics.ll
    M llvm/test/CodeGen/PowerPC/atomicrmw-cond-sub-clamp.ll
    M llvm/test/CodeGen/PowerPC/atomicrmw-uinc-udec-wrap.ll
    M llvm/test/CodeGen/PowerPC/common-chain.ll
    M llvm/test/CodeGen/PowerPC/csr-split.ll
    M llvm/test/CodeGen/PowerPC/livevars-crash1.mir
    M llvm/test/CodeGen/PowerPC/livevars-crash2.mir
    M llvm/test/CodeGen/PowerPC/phi-eliminate.mir
    M llvm/test/CodeGen/PowerPC/prefer-dqform.ll
    M llvm/test/CodeGen/PowerPC/shrink-wrap.ll
    M llvm/test/CodeGen/PowerPC/umulo-128-legalisation-lowering.ll
    M llvm/test/CodeGen/RISCV/GlobalISel/double-intrinsics.ll
    M llvm/test/CodeGen/RISCV/GlobalISel/rotl-rotr.ll
    M llvm/test/CodeGen/RISCV/GlobalISel/rv32zbb-zbkb.ll
    M llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll
    M llvm/test/CodeGen/RISCV/GlobalISel/shifts.ll
    M llvm/test/CodeGen/RISCV/GlobalISel/wide-scalar-shift-by-byte-multiple-legalization.ll
    M llvm/test/CodeGen/RISCV/O3-newpm-pipeline.ll
    M llvm/test/CodeGen/RISCV/O3-pipeline.ll
    M llvm/test/CodeGen/RISCV/abdu-neg.ll
    M llvm/test/CodeGen/RISCV/abdu.ll
    M llvm/test/CodeGen/RISCV/bitint-fp-conv-200.ll
    M llvm/test/CodeGen/RISCV/fpclamptosat.ll
    M llvm/test/CodeGen/RISCV/idiv_large.ll
    M llvm/test/CodeGen/RISCV/machine-pipeliner.ll
    M llvm/test/CodeGen/RISCV/rv64m-w-insts-legalization.ll
    M llvm/test/CodeGen/RISCV/rv64xtheadbb.ll
    M llvm/test/CodeGen/RISCV/rv64zbb.ll
    M llvm/test/CodeGen/RISCV/rvv/dont-sink-splat-operands.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vector-convert-from-arbitrary-fp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
    M llvm/test/CodeGen/RISCV/rvv/fpclamptosat_vec.ll
    M llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll
    M llvm/test/CodeGen/RISCV/rvv/vector-extract-last-active.ll
    M llvm/test/CodeGen/RISCV/rvv/vpload.ll
    M llvm/test/CodeGen/RISCV/smulh.ll
    M llvm/test/CodeGen/RISCV/zicond-fp-select-zfinx.ll
    M llvm/test/CodeGen/SPARC/umulo-128-legalisation-lowering.ll
    M llvm/test/CodeGen/SystemZ/fp-half-vector-fcmp-select.ll
    M llvm/test/CodeGen/Thumb/scmp.ll
    M llvm/test/CodeGen/Thumb/ucmp.ll
    M llvm/test/CodeGen/Thumb/umul_fix_sat.ll
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/cond-vector-reduce-mve-codegen.ll
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/reductions.ll
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/varying-outer-2d-reduction.ll
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/vector-arith-codegen.ll
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/while-loops.ll
    M llvm/test/CodeGen/Thumb2/aligned-nonfallthrough.ll
    M llvm/test/CodeGen/Thumb2/mve-float16regloops.ll
    M llvm/test/CodeGen/Thumb2/mve-float32regloops.ll
    M llvm/test/CodeGen/Thumb2/mve-gather-increment.ll
    M llvm/test/CodeGen/Thumb2/mve-masked-ldst.ll
    M llvm/test/CodeGen/Thumb2/mve-phireg.ll
    M llvm/test/CodeGen/Thumb2/mve-postinc-dct.ll
    M llvm/test/CodeGen/Thumb2/mve-postinc-lsr.ll
    M llvm/test/CodeGen/Thumb2/mve-satmul-loops.ll
    M llvm/test/CodeGen/Thumb2/mve-vecreduce-loops.ll
    M llvm/test/CodeGen/VE/Scalar/atomic.ll
    M llvm/test/CodeGen/X86/2007-11-30-LoadFolding-Bug.ll
    M llvm/test/CodeGen/X86/apx/push2-pop2.ll
    M llvm/test/CodeGen/X86/atom-fixup-lea2.ll
    M llvm/test/CodeGen/X86/block-placement.ll
    M llvm/test/CodeGen/X86/branchfolding-debugloc.ll
    M llvm/test/CodeGen/X86/bsf.ll
    M llvm/test/CodeGen/X86/bsr.ll
    M llvm/test/CodeGen/X86/call-rv-marker.ll
    M llvm/test/CodeGen/X86/callbr-asm-branch-folding.ll
    M llvm/test/CodeGen/X86/callbr-asm-different-indirect-target.mir
    M llvm/test/CodeGen/X86/callbr-asm-kill.mir
    M llvm/test/CodeGen/X86/coalescer-copy-from-erasable-implicit-def.ll
    M llvm/test/CodeGen/X86/codegen-prepare-addrmode-tls.ll
    M llvm/test/CodeGen/X86/div-rem-pair-recomposition-signed.ll
    M llvm/test/CodeGen/X86/div-rem-pair-recomposition-unsigned.ll
    M llvm/test/CodeGen/X86/extract-bits.ll
    M llvm/test/CodeGen/X86/extract-lowbits.ll
    M llvm/test/CodeGen/X86/fp-intrinsics.ll
    M llvm/test/CodeGen/X86/fp-strict-scalar-fptoint-fp16.ll
    M llvm/test/CodeGen/X86/fp-strict-scalar-fptoint.ll
    M llvm/test/CodeGen/X86/fptoui-sat-scalar.ll
    M llvm/test/CodeGen/X86/fshl.ll
    M llvm/test/CodeGen/X86/fshr.ll
    M llvm/test/CodeGen/X86/gpr-to-mask.ll
    M llvm/test/CodeGen/X86/i128-udiv.ll
    M llvm/test/CodeGen/X86/lea-opt-cse4.ll
    M llvm/test/CodeGen/X86/legalize-shift-64.ll
    M llvm/test/CodeGen/X86/llc-pipeline-npm.ll
    M llvm/test/CodeGen/X86/masked_gather_scatter.ll
    M llvm/test/CodeGen/X86/opt-pipeline.ll
    M llvm/test/CodeGen/X86/phi-elim-undef-livevars.mir
    M llvm/test/CodeGen/X86/phielim-undef.mir
    M llvm/test/CodeGen/X86/pr38539.ll
    M llvm/test/CodeGen/X86/ragreedy-hoist-spill.ll
    M llvm/test/CodeGen/X86/vec-strict-fptoint-128.ll
    M llvm/test/CodeGen/X86/vec-strict-fptoint-256.ll
    M llvm/test/CodeGen/X86/vector-constrained-fp-intrinsics.ll
    M llvm/test/CodeGen/X86/x86-cmov-converter.ll
    M llvm/test/Transforms/LoopStrengthReduce/AArch64/postidx-load.ll

  Log Message:
  -----------
  CodeGen: Run LiveIntervals before PHIElimination and drop LiveVariables from it

Move LiveIntervals to run before PHIElimination in the optimized register
allocation pipeline, and make PHIElimination maintain LiveIntervals only.

This removes the last explicit use of LiveVariables. The actual analysis is no
longer used. There are implicit dependencies on the side effects of running the
analysis due to adjustments of dead flags, so further work is still needed to
complete the removal.

This perturbs register allocation in a number of tests. The same codegen result
can be achieved by not preserving the analysis and recomputing fresh. Greedy is
just sensitive to the exact slot index and value numbering with identical MIR.

Measured across every affected test the emitted instruction count goes from
145124 to 145196, +0.050%, with changes in both directions. The largest
regression is AArch64/phi.ll, where the GlobalISel output gains about 30
instructions and no longer matches the SelectionDAG output; the largest
improvements are ARM/fpclamptosat.ll and PowerPC/common-chain.ll.

Co-authored-by: Claude Opus 5 <noreply at anthropic.com>

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