[all-commits] [llvm/llvm-project] 4be402: [flang] disable cf canonicalization patterns at O0...
Graham Hunter via All-commits
all-commits at lists.llvm.org
Thu Oct 1 05:49:46 PDT 2026
Branch: refs/heads/users/huntergr-arm/splat-pattern-match
Home: https://github.com/llvm/llvm-project
Commit: 4be402e459e2fa1e98826c99e3fcef4121729e26
https://github.com/llvm/llvm-project/commit/4be402e459e2fa1e98826c99e3fcef4121729e26
Author: jeanPerier <jperier at nvidia.com>
Date: 2026-10-01 (Thu, 01 Oct 2026)
Changed paths:
M flang/include/flang/Optimizer/Transforms/Passes.h
M flang/include/flang/Optimizer/Transforms/Passes.td
M flang/lib/Optimizer/Passes/Pipelines.cpp
M flang/lib/Optimizer/Transforms/CMakeLists.txt
A flang/lib/Optimizer/Transforms/O0CanonicalizerPass.cpp
M flang/test/Driver/mlir-debug-pass-pipeline.f90
M flang/test/Driver/mlir-pass-pipeline.f90
M flang/test/Integration/OpenMP/parallel-private-reduction-worstcase.f90
A flang/test/Integration/array-assignment-entry-debug.f90
A flang/test/Integration/array-assignment-entry-paths.f90
M flang/test/Integration/cold_array_repacking.f90
A flang/test/Transforms/o0-canonicalize.mlir
Log Message:
-----------
[flang] disable cf canonicalization patterns at O0 to preserve line location (#227770)
This patch is a follow up to #202065 and intends to preserve at least one loop
header instructions for each expanded array expressions at O0 so that breakpoint
set on array expression statements that are expanded inline fire once (an not at
each iteration which happens when the only instruction with the statement line
location is in the loop body). CF canonicalization patterns may remove branch
instructions that are the only valid breakpoint position for an array expression
statement from the source.
To solve this, this patch adds a new canonicalization pass that allows skipping
ControlFlow dialect pattern registration at O0.
This replaces #227306 approach that was using a debug pattern filtering
approach instead of using a new pass.
Assisted-by: AI
Commit: c6afcd0b4ab5f089572bb8a2f8a9134fc5c59fc5
https://github.com/llvm/llvm-project/commit/c6afcd0b4ab5f089572bb8a2f8a9134fc5c59fc5
Author: Julien Villette <julien.villette at gmail.com>
Date: 2026-10-01 (Thu, 01 Oct 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64SchedNeoverseV1.td
M llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td
M llvm/test/tools/llvm-mca/AArch64/Neoverse/V1-neon-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-neon-instructions.s
Log Message:
-----------
[AArch64][NeoverseV1/V2] Fix FMULX scalar latency (#224540)
The "ASIMD FP multiply" InstRW regex required a "v" suffix, so the
scalar register-register forms FMULX16, FMULX32 and FMULX64 fell back to
a generic class with latency 2.
Measured on Neoverse V1 and V2 hardware with a single dependency chain:
3 cycles, the same as the vector forms and as FMUL, matching the SOG
row.
Commit: 86a445a3f6e3ee145fd9523a6360626b1df99fd1
https://github.com/llvm/llvm-project/commit/86a445a3f6e3ee145fd9523a6360626b1df99fd1
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-10-01 (Thu, 01 Oct 2026)
Changed paths:
M llvm/lib/Analysis/InstructionSimplify.cpp
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
A llvm/test/Transforms/InstCombine/smulh.ll
A llvm/test/Transforms/InstCombine/umulh.ll
Log Message:
-----------
[InstCombine] Add generic smulh/umulh identity folds (#227335)
Added baseline smulh/umulh tests branched from equivalent x86 pmulh/pmulhu tests
Added generic generic smulh/umulh identity folds that match the x86 pmulh (commutative) folds:
[su]mulh(x,undef) -> 0
[su]mulh(x,0) -> 0
umulh(x,1) -> 0
smulh(x,1) -> sra(x,bw-1) // signsplat
Prep work for #223627
Commit: 018a9e4a74ba5d383351bda907a8b116bc5d8c47
https://github.com/llvm/llvm-project/commit/018a9e4a74ba5d383351bda907a8b116bc5d8c47
Author: Tomohiro Kashiwada <kikairoya at gmail.com>
Date: 2026-10-01 (Thu, 01 Oct 2026)
Changed paths:
M llvm/include/llvm/Support/Compiler.h
M llvm/lib/ExecutionEngine/Orc/TargetProcess/RegisterEHFrames.cpp
Log Message:
-----------
[ORC] Define `LLVM_HAS_ATTRIBUTE_WEAK` and guard `__unw_*_dynamic_eh_frame_section` by it (#227709)
#212260 causes a linker error on Cygwin, which expands
`LLVM_ATTRIBUTE_WEAK` to empty:
```
ld.lld: error: undefined symbol: __unw_add_dynamic_eh_frame_section
>>> referenced by libLLVMOrcTargetProcess.a(RegisterEHFrames.cpp.o):(llvm::orc::registerEHFrameSection(void const*, unsigned long))
>>> referenced by libLLVMOrcTargetProcess.a(RegisterEHFrames.cpp.o):(registerEHFrameWrapper(llvm::orc::ExecutorAddrRange))
```
---------
Co-authored-by: Lang Hames <lhames at gmail.com>
Commit: 180b69dfdf76a1d42cc00489ce3c885f4c434a29
https://github.com/llvm/llvm-project/commit/180b69dfdf76a1d42cc00489ce3c885f4c434a29
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-10-01 (Thu, 01 Oct 2026)
Changed paths:
M llvm/include/llvm/IR/IRBuilder.h
Log Message:
-----------
[IRBuilder] Remove FPMathTag and OpBundles constructor arguments (#228013)
Remove the FPMathTag and OpBundles IRBuilder constructor arguments,
which are never used in tree. The setDefaultFPMathTag() and
setDefaultOperandBundles() APIs can be used instead.
Commit: 326789c0a3686fa47466ae92e9c9013073799673
https://github.com/llvm/llvm-project/commit/326789c0a3686fa47466ae92e9c9013073799673
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-10-01 (Thu, 01 Oct 2026)
Changed paths:
M mlir/lib/Dialect/SPIRV/IR/MemoryOps.cpp
M mlir/test/Dialect/SPIRV/IR/memory-ops.mlir
Log Message:
-----------
[mlir][SPIR-V] Share the memory operands mask verifier between both masks (#225520)
Verify the `CopyMemory` Target and Source masks through one shared
function instead of a separate Source path
Originally discussed in https://github.com/llvm/llvm-project/pull/213621
Commit: 5b46a5d578269aca9e1f74b79f23bddc7af9a2b5
https://github.com/llvm/llvm-project/commit/5b46a5d578269aca9e1f74b79f23bddc7af9a2b5
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-10-01 (Thu, 01 Oct 2026)
Changed paths:
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVAtomicOps.td
M mlir/lib/Dialect/SPIRV/IR/AtomicOps.cpp
M mlir/test/Dialect/SPIRV/IR/atomic-ops.mlir
Log Message:
-----------
[mlir][SPIR-V] Verify memory semantics for AtomicLoad/Store/Exchange/CompareExchange ops (#212990)
Commit: d287e55d03029586399adab02977679e74c51f2d
https://github.com/llvm/llvm-project/commit/d287e55d03029586399adab02977679e74c51f2d
Author: Dmitriy Smirnov <dmitriy.smirnov at arm.com>
Date: 2026-10-01 (Thu, 01 Oct 2026)
Changed paths:
M mlir/lib/Conversion/VectorToGPU/VectorToGPU.cpp
Log Message:
-----------
[MLIR][VectorToGPU] Cache slice analysis in getOpToConvert (#221795)
ConvertVectorToGPU spent a lot of time rebuilding the same backward and
forward slices for overlapping vector/MMA use-def components, which was
especially visible on int8 cases.
This change caches backward slices, forward slices, and
supportsMMaMatrixType() results per operation, and marks fully expanded
components as already analyzed. That avoids repeatedly rediscovering and
revalidating the same component from multiple seeds without changing the
lowering itself.
The resulting conversion is unchanged, but compile time for the affected
int8 case drops significantly.
---------
Co-authored-by: Thomas Preud'homme <thomas.preudhomme at arm.com>
Commit: 24cfc481238a957453c869378ff5bad10ce3ff09
https://github.com/llvm/llvm-project/commit/24cfc481238a957453c869378ff5bad10ce3ff09
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-10-01 (Thu, 01 Oct 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
Log Message:
-----------
[LV] Remove the EpilogueVectorizerMainLoop hierarchy level (NFC). (#227885)
EpilogueVectorizerMainLoop no longer overrides
createVectorizedLoopSkeleton; all it contributes are two debug traces.
Vectorize the main loop with a plain InnerLoopVectorizer and emit the
debug traces for both the main and the epilogue loop from processLoop,
removing the printDebugTraces* hooks.
That leaves InnerLoopAndEpilogueVectorizer with a single subclass and a
single member only used by the debug traces, so fold it into
EpilogueVectorizerEpilogueLoop and drop the member.
Commit: 255694c1d3db5aa3bc87bc9b27dbf1ffe3fab65c
https://github.com/llvm/llvm-project/commit/255694c1d3db5aa3bc87bc9b27dbf1ffe3fab65c
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-10-01 (Thu, 01 Oct 2026)
Changed paths:
M llvm/test/Analysis/CostModel/AMDGPU/fsub.ll
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/phi_div_loop.ll
M llvm/test/CodeGen/AMDGPU/hsa-metadata-agpr-small.ll
M llvm/test/CodeGen/AMDGPU/lshl-add-u64.ll
M llvm/test/CodeGen/AMDGPU/mubuf-offset-private.ll
M llvm/test/CodeGen/AMDGPU/set-wave-priority.ll
M llvm/test/MC/AMDGPU/gfx1150_asm_salu_float.s
Log Message:
-----------
[AMDGPU] Add missing colons to FileCheck directives in tests (NFC) (#227999)
Commit: 9d9c4426fb0e0f0a43b283678acaafd22d6dfe8a
https://github.com/llvm/llvm-project/commit/9d9c4426fb0e0f0a43b283678acaafd22d6dfe8a
Author: dong jianqiang <dongjianqiang2 at huawei.com>
Date: 2026-10-01 (Thu, 01 Oct 2026)
Changed paths:
M llvm/lib/Target/ARM/ARMFastISel.cpp
A llvm/test/CodeGen/ARM/fast-isel-call-be-softfp.ll
Log Message:
-----------
[ARM][FastISel] Fix soft-float f64 register pair order on big endian (#227172)
Under the soft-float ABI an f64 argument or return value is passed in a
core register pair which is ordered like any other 64-bit value in core
registers: on big-endian targets the register holding the most
significant word comes first.
FastISel materialized the pair with VMOVRRD/VMOVDRR in little-endian
order on both endiannesses, disagreeing with the SelectionDAG ISel paths
and miscompiling soft-float f64 argument passing and returns for armebv7
targets at -O0.
VMOVRRD moves Dn[31:0] to Rt and Dn[63:32] to Rt2, and VMOVDRR reads
them symmetrically, so swap the destination/source pair when the data
layout is big-endian, mirroring the big-endian handling already present
in ARMISelLowering.
Fixes #227171
Commit: d844ab7db8aafe8c5de2131b5f066f8b9b80bc1c
https://github.com/llvm/llvm-project/commit/d844ab7db8aafe8c5de2131b5f066f8b9b80bc1c
Author: Henrich Lauko <xlauko at mail.muni.cz>
Date: 2026-10-01 (Thu, 01 Oct 2026)
Changed paths:
M clang/docs/CIR/CleanupAndEHDesign.md
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/lib/CIR/Dialect/Analysis/CIRBasicAliasAnalysis.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
M clang/test/CIR/Analysis/alias-analysis-underlying-object.cir
M clang/test/CIR/CodeGen/base-init-eh.cpp
M clang/test/CIR/CodeGen/base-to-derived.cpp
M clang/test/CIR/CodeGen/class.cpp
M clang/test/CIR/CodeGen/cleanup-derived-to-base-ref.cpp
M clang/test/CIR/CodeGen/ctor-null-init.cpp
M clang/test/CIR/CodeGen/ctor-try-body.cpp
M clang/test/CIR/CodeGen/ctor.cpp
M clang/test/CIR/CodeGen/delegating-ctor.cpp
M clang/test/CIR/CodeGen/derived-to-base.cpp
M clang/test/CIR/CodeGen/destructor-vtable-reinit-strict.cpp
M clang/test/CIR/CodeGen/destructor-vtable-reinit.cpp
M clang/test/CIR/CodeGen/dtors.cpp
M clang/test/CIR/CodeGen/inherited-ctors.cpp
M clang/test/CIR/CodeGen/multi-vtable.cpp
M clang/test/CIR/CodeGen/paren-list-agg-init.cpp
M clang/test/CIR/CodeGen/temporary-materialization-adjust.cpp
M clang/test/CIR/CodeGen/vbase.cpp
M clang/test/CIR/CodeGen/virtual-destructor-calls.cpp
M clang/test/CIR/CodeGen/vtt.cpp
M clang/test/CIR/IR/vtt-addrpoint.cir
M clang/test/CIR/Lowering/vtt-addrpoint.cir
M clang/test/CIR/Transforms/pure-ptr-arithmetic.cir
Log Message:
-----------
[CIR] Extract CIR_ClassCastOp base class for BaseClassAddrOp and DerivedClassAddrOp (#195478)
Both ops have identical structure (arguments, results, assembly format)
and differ only in mnemonic and description. Extract a shared TableGen
base class to eliminate the duplication.
Improve the assembly format to be more consistent with the rest of CIR.
Assisted-by: Claude Code (Claude Fable 5.1).
Commit: 7a632629eed2562fbcb0374c97ba94740a914c0a
https://github.com/llvm/llvm-project/commit/7a632629eed2562fbcb0374c97ba94740a914c0a
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-10-01 (Thu, 01 Oct 2026)
Changed paths:
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/intrinsics.ll
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/irreducible/branch-outside.ll
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/irreducible/exit-divergence.ll
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/irreducible/reducible-headers.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.workgroup.id.ll
M llvm/test/CodeGen/AMDGPU/cgp-addressing-modes.ll
M llvm/test/CodeGen/AMDGPU/default-fp-mode.ll
M llvm/test/CodeGen/AMDGPU/dpp_combine-true16.mir
M llvm/test/CodeGen/AMDGPU/fmin_fmax_legacy.amdgcn.ll
M llvm/test/CodeGen/AMDGPU/internalize.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sdot4.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.workgroup.id.ll
M llvm/test/CodeGen/AMDGPU/lshl-add-u64.ll
M llvm/test/CodeGen/AMDGPU/merge-out-of-order-ldst.ll
M llvm/test/CodeGen/AMDGPU/shift-select.ll
M llvm/test/CodeGen/AMDGPU/token-factor-inline-limit-test.ll
M llvm/test/CodeGen/AMDGPU/triv-disjoint-mem-access-neg-offset.mir
M llvm/test/CodeGen/AMDGPU/vector-alloca-bitcast.ll
Log Message:
-----------
[AMDGPU] Fix misspelled FileCheck prefixes and suffixes in tests (NFC) (#228001)
FileCheck ignores these directives, so the checks never ran
Commit: 530bcc34727376393c1b3a70bbe4f9f23e2e4f80
https://github.com/llvm/llvm-project/commit/530bcc34727376393c1b3a70bbe4f9f23e2e4f80
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-10-01 (Thu, 01 Oct 2026)
Changed paths:
M llvm/lib/CodeGen/CodeGenPrepare.cpp
M llvm/lib/CodeGen/WasmEHPrepare.cpp
M llvm/lib/IR/AutoUpgrade.cpp
M llvm/lib/Target/ARM/MVEGatherScatterLowering.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyLowerEmscriptenEHSjLj.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyRefTypeMem2Local.cpp
M llvm/lib/Transforms/Scalar/LoopSimplifyCFG.cpp
M llvm/lib/Transforms/Scalar/ScalarizeMaskedMemIntrin.cpp
Log Message:
-----------
[llvm] Pass insertion point directly to IRBuilder ctor (NFC) (#228019)
Pass insertion point directly to the ctor instead of calling
SetInsertPoint(). Also remove redundant SetCurrentDebugLocation()
calls, which SetInsertPoint() already does.
Commit: 9eb8ba1438c64085de1cf958eaf29ba9918a1ce2
https://github.com/llvm/llvm-project/commit/9eb8ba1438c64085de1cf958eaf29ba9918a1ce2
Author: Deepak Shirke <deepakshirke509 at gmail.com>
Date: 2026-10-01 (Thu, 01 Oct 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
M llvm/lib/Target/AArch64/AArch64InstrFormats.td
M llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/split-wide-shifts-multiway.ll
M llvm/test/CodeGen/AArch64/frem-power2.ll
M llvm/test/CodeGen/AArch64/fsh.ll
M llvm/test/CodeGen/AArch64/funnel-shift.ll
M llvm/test/CodeGen/AArch64/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll
M llvm/test/CodeGen/AArch64/hoist-and-by-const-from-shl-in-eqcmp-zero.ll
M llvm/test/CodeGen/AArch64/select_const.ll
M llvm/test/CodeGen/AArch64/shift-mod.ll
M llvm/test/CodeGen/AArch64/shift.ll
Log Message:
-----------
[GlobalISel] [AArch64] Skip redundant shift amount masking during isel (#223136)
AArch64 shift instructions (LSL/LSR/ASR) only use the low 5 bits (i32)or
6 bits (i64) of the shift amount. When the shift amount is masked with
an AND that was introduced by legalization of a narrow type zext, or is
a G_ZEXT itself, the operation is redundant and can be skipped during
instruction selection.
This mirrors what AArch64DAGToDAGISel::tryShiftAmountMod does for
SelectionDAG, bringing GlobalISel to parity for i32 shift amounts with
narrow shift amount types (i8, i16).
Before (GlobalISel shl i32 with i8 shift amount):
and w8, w1, #0xff
lsl w0, w0, w8
After (matches SelectionDAG):
lsl w0, w0, w1
Part of the incremental work tracked in
https://github.com/llvm/llvm-project/issues/224245 to replace
tryShiftAmountMod with ComplexPattern-based isel.
Commit: e496d3c1f3e60b27d8b016c0b36ecb89653ae38f
https://github.com/llvm/llvm-project/commit/e496d3c1f3e60b27d8b016c0b36ecb89653ae38f
Author: konoongg <120199924+konoongg at users.noreply.github.com>
Date: 2026-10-01 (Thu, 01 Oct 2026)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
M llvm/test/Transforms/InstCombine/add.ll
M llvm/test/Transforms/InstCombine/fadd.ll
Log Message:
-----------
[InstCombine] Drop one-use check in matchesSquareSum for (a*a) (#228020)
The pattern `(a * a) + (((a * 2) + b) * b)` is equivalent to `(a + b) *
(a + b)`. The current implementation requires the `a * a` subexpression
to have a single use, which prevents the fold when `a * a` is used
elsewhere. This check is unnecessary: we can still perform the fold and
keep the original `a * a` instruction for other uses.
For example, with an extra use of `a * a`:
%1 = mul i32 %a, %a
%2 = mul i32 %a, 2
%3 = add i32 %2, %b
%4 = mul i32 %3, %b
%5 = add i32 %4, %1
%6 = mul i32 %1, %1
After this change, InstCombine produces:
%1 = add i32 %a, %b
%2 = mul i32 %1, %1
%3 = mul i32 %a, %a
%4 = mul i32 %3, %3
This reduces the instruction count from 6 to 4, even though `a * a` is
now computed both explicitly (for the extra use) and implicitly as part
of `(a + b) * (a + b)`.
The same applies to the floating-point (fadd) variant. Both are
updated together.
Commit: 79b6b7aca7384ae07b42f28d258cb6fa6d1df45c
https://github.com/llvm/llvm-project/commit/79b6b7aca7384ae07b42f28d258cb6fa6d1df45c
Author: Jay Foad <jay.foad at amd.com>
Date: 2026-10-01 (Thu, 01 Oct 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
Log Message:
-----------
[AMDGPU] Early exit in getSelectConstants. NFC. (#228023)
Commit: 4b3ddb66a8defeb4caa7194ab78d182a70044424
https://github.com/llvm/llvm-project/commit/4b3ddb66a8defeb4caa7194ab78d182a70044424
Author: Pankaj Dwivedi <pankajkumar.divedi at amd.com>
Date: 2026-10-01 (Thu, 01 Oct 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
M llvm/test/CodeGen/AMDGPU/ds_read2.ll
M llvm/test/CodeGen/AMDGPU/merge-m0.mir
Log Message:
-----------
[AMDGPU] Don't merge M0 initializations across calls that clobber M0 (#221963)
hoistAndMergeSGPRInits collected clobbers only from
MRI.def_instructions(M0),
which lists explicit defs. Calls clobber M0 via a regmask and were
therefore
invisible, so M0 inits were merged and hoisted across them and the
required
re-init after a call was dropped. Scan the function using
modifiesRegister.
Issue: https://github.com/llvm/llvm-project/issues/221212
Commit: be26b1af2bd9c18be1477ca5b828157a4cefebc3
https://github.com/llvm/llvm-project/commit/be26b1af2bd9c18be1477ca5b828157a4cefebc3
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-10-01 (Thu, 01 Oct 2026)
Changed paths:
M llvm/include/llvm/Analysis/ConstraintSystem.h
M llvm/lib/Analysis/ConstraintSystem.cpp
M llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
M llvm/unittests/Analysis/ConstraintSystemTest.cpp
Log Message:
-----------
[ConstraintElim] Skip rows implied by a single existing row. (#227688)
There are a number of cases where we add duplicated rows (e.g. from
transferring facts between the signed and unsigned systems, or from
tightening a non-strict bound using !=).
Before adding rows, check if the system already has a row that the same
variable coefficient and a constant that is <= the current constant.
This helps reduce compile-time, as each row adds extra work during
constraint solving:
stage1-O3: -0.02%
stage1-ReleaseThinLTO: -0.05%
stage1-ReleaseLTO-g: -0.02%
stage1-aarch64-O3: -0.00%
stage2-O3: -0.01%
stage2-clang: -0.00%
https://llvm-compile-time-tracker.com/compare.php?from=5da194580292bc90f6577f3959dda3a9bb6d5366&to=67f7d35c131b156663342cfae20d55e7a4187196&stat=instructions:u
The impact depends on the specific module and mostly in cases where the
number of facts is on the larger side. See additional compile-time
impact here
https://github.com/dtcxzyw/llvm-opt-benchmark-nightly/pull/1527
Fewer rows in the system can improve results in a few cases where we
previously hit the maximum rows cutoff:
https://github.com/dtcxzyw/llvm-opt-benchmark-nightly/pull/1526.
PR: https://github.com/llvm/llvm-project/pull/227688
Commit: 7f5794c102a0caa350f6791e7ef541ec065d093f
https://github.com/llvm/llvm-project/commit/7f5794c102a0caa350f6791e7ef541ec065d093f
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-10-01 (Thu, 01 Oct 2026)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
M llvm/test/Transforms/InstCombine/smulh.ll
M llvm/test/Transforms/InstCombine/umulh.ll
Log Message:
-----------
[InstCombine] SimplifyDemandedVectorElts - add smulh/umulh handling (#228027)
Commit: fec418c78fe1e10016f893f3293a276093ebdfc1
https://github.com/llvm/llvm-project/commit/fec418c78fe1e10016f893f3293a276093ebdfc1
Author: Graham Hunter <graham.hunter at arm.com>
Date: 2026-10-01 (Thu, 01 Oct 2026)
Changed paths:
M llvm/include/llvm/IR/PatternMatch.h
M llvm/include/llvm/Transforms/Vectorize/LoopVectorizationLegality.h
M llvm/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlanPatternMatch.h
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.h
M llvm/test/Transforms/LoopVectorize/VPlan/early_exit_with_stores_vplan.ll
M llvm/test/Transforms/LoopVectorize/X86/vectorization-remarks-missed.ll
M llvm/test/Transforms/LoopVectorize/early_exit_combined_exits.ll
A llvm/test/Transforms/LoopVectorize/early_exit_combined_exits_epilogue.ll
M llvm/test/Transforms/LoopVectorize/early_exit_legality.ll
M llvm/test/Transforms/LoopVectorize/early_exit_store_legality.ll
M llvm/test/Transforms/LoopVectorize/early_exit_with_stores.ll
M llvm/test/Transforms/LoopVectorize/fold-epilogue-tail.ll
M llvm/test/Transforms/LoopVectorize/uncountable-single-exit-loops.ll
M llvm/test/Transforms/PhaseOrdering/AArch64/countable-and-uncountable-exits-combined.ll
Log Message:
-----------
[LV] Vectorize uncountable early exit store loops with combined conditions (#205109)
Support the case where both the countable and uncountable exit
conditions have been combined by earlier passes.
Commit: 0704576db68c95ec1835771965824ba4ed4924cb
https://github.com/llvm/llvm-project/commit/0704576db68c95ec1835771965824ba4ed4924cb
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-10-01 (Thu, 01 Oct 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/VOP1Instructions.td
M llvm/lib/Target/AMDGPU/VOPInstructions.td
M llvm/test/MC/AMDGPU/dpp-err.s
M llvm/test/MC/AMDGPU/gfx9-asm-err.s
M llvm/test/MC/Disassembler/AMDGPU/gfx9_dasm_err.txt
Log Message:
-----------
[AMDGPU] Reject 64-bit VOP1 DPP on gfx8/gfx9 (#220834)
64-bit DPP needs FeatureDPALU_DPP (gfx90a+), but HasDPALU_DPP is missing
GCN3Encoding gate that HasDPP has
Commit: ec1f5ecb04250392ed48388621050d7cdcc5f3f3
https://github.com/llvm/llvm-project/commit/ec1f5ecb04250392ed48388621050d7cdcc5f3f3
Author: Caroline Newcombe <caroline.newcombe at hpe.com>
Date: 2026-10-01 (Thu, 01 Oct 2026)
Changed paths:
M flang/docs/OpenMPSupport.md
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/test/Lower/OpenMP/collapse-imperfect-nest.f90
R flang/test/Lower/OpenMP/collapse-target-intervening-todo.f90
A offload/test/offloading/fortran/target-teams-distribute-collapse-intervening.f90
Log Message:
-----------
[flang][OpenMP] Sink intervening code unguarded into collapsed loop body (#225159)
### Summary
Lower intervening code in a collapsed imperfect loop nest by sinking it
unguarded into the innermost `omp.loop_nest` body, so it executes once
per collapsed logical iteration. Per OpenMP 6.0 6.4.3.
An earlier implementation of this work guarded intervening code so that
it ran once per enclosing iteration. That required recomputing the inner
loop's bounds inside the region — and in a `target` region, either
accessing or re-evaluating
the enclosing `omp.target`'s `host_eval` bounds (#223475) — which
overcomplicates the solution and is not required by the spec. Sinking
the intervening code removes all bound arithmetic from the region, while
the execution count remains within the permitted range.
### Notes
Fixes #199092
Assisted-by: Copilot
Commit: a9c5e57c03413e31a9293a4d938402e6204ff888
https://github.com/llvm/llvm-project/commit/a9c5e57c03413e31a9293a4d938402e6204ff888
Author: Aaron Ballman <aaron at aaronballman.com>
Date: 2026-10-01 (Thu, 01 Oct 2026)
Changed paths:
M clang/docs/ReleaseNotes.md
M clang/lib/Sema/SemaExpr.cpp
M clang/test/Sema/fp16vec-sema.c
M clang/test/Sema/vector-ops.c
M clang/test/SemaCXX/vector.cpp
Log Message:
-----------
[clang] Fix crash with follow-on diagnostics w/invalid logical operator (#227837)
If the logical operator involves a vector operand, we perform special
vector-specific checks. `CheckVectorOperands()` returns a null QualType
to signal there was an issue, and `CheckVectorLogicalOperands()` was
using that signal to decide to report an "invalid operands to binary
expression" diagnostic. However, `CheckVectorOperands()` also sometimes
modifies the given LHS and RHS values and when that happens, the caller
cannot assume they're still valid on a null QualType return. This was
causing a crash from `CheckVectorLogicalOperands()` because it was
attempting to use those newly invalidated expressions.
This fixes the crash by letting `CheckVectorOperands()` report the
diagnostics directly and removing the fallback logic from
`CheckVectorLogicalOperands()`. This also helpfully removes some
unhelpful follow-on diagnostics in other cases where we would report
"cannot convert operands" followed by "invalid operands to binary
expression".
Fixes #227588
Commit: e996ce0d9ad6443a7ea3f88ccb0a8e114b0e840e
https://github.com/llvm/llvm-project/commit/e996ce0d9ad6443a7ea3f88ccb0a8e114b0e840e
Author: David Sherwood <david.sherwood at arm.com>
Date: 2026-10-01 (Thu, 01 Oct 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/maxbandwidth-regpressure.ll
M llvm/test/Transforms/LoopVectorize/AArch64/predication_costs.ll
Log Message:
-----------
[LV][NFC] Print more debug to account for mismatch in final costs (#227757)
After printing out the costs of recipes we then print out the total
cost, including the cost per lane. Unfortunately, the final cost often
doesn't match the total of all the recipe costs due to extra precomputed
costs and reg spill costs. This PR adds the missing information.
Commit: 66008b77b133f797e80c84a00dee4ac091283e22
https://github.com/llvm/llvm-project/commit/66008b77b133f797e80c84a00dee4ac091283e22
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2026-10-01 (Thu, 01 Oct 2026)
Changed paths:
M llvm/include/llvm/Frontend/OpenMP/OMP.h
M llvm/include/llvm/Frontend/OpenMP/OMPDescriptors.h
M llvm/unittests/Frontend/EnumSetTest.cpp
Log Message:
-----------
[OpenMP] Add default value for Size argument in EnumSet (#227853)
Most of the interesting enums cover a contiguous range of values, and
define members First_ and Last_. By subtracting the underlying values
one can get the number of elements in the enum.
Commit: a04805eff3ccd42bf8cd6056d6c75f63f42a2522
https://github.com/llvm/llvm-project/commit/a04805eff3ccd42bf8cd6056d6c75f63f42a2522
Author: Hari Limaye <hari.limaye at arm.com>
Date: 2026-10-01 (Thu, 01 Oct 2026)
Changed paths:
M llvm/test/Transforms/SLPVectorizer/AArch64/gather-buildvector-with-minbitwidth-user.ll
Log Message:
-----------
SLP: Remove artificial shifts from min-bitwidth test (NFC) (#222634)
Replace shifts by zero with zero constants, using a slightly negative
threshold to preserve the test signal. This allows a future update to
the cost of foldable shifts.
Commit: 0489b48e2f2e2374bee7db19483322307d19b8bf
https://github.com/llvm/llvm-project/commit/0489b48e2f2e2374bee7db19483322307d19b8bf
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-10-01 (Thu, 01 Oct 2026)
Changed paths:
M llvm/lib/Target/Mips/MipsCallLowering.cpp
M llvm/test/CodeGen/Mips/GlobalISel/irtranslator/call.ll
M llvm/test/CodeGen/Mips/GlobalISel/irtranslator/global_address_pic.ll
Log Message:
-----------
Mips/GlobalISel: Fix adding $gp to calls as a def instead of a use (#227679)
A PIC call needs $gp to point at the GOT for the lazy binding stub.
SelectionDAG adds it as an ordinary argument register. GlobalISel
instead added it as an implicit def, which killed the $gp copy set up
right before the call.
Co-authored-by: Claude Opus 5 <noreply at anthropic.com>
Commit: d240a0be972335f43fc2bacc4b124e72a32f74d4
https://github.com/llvm/llvm-project/commit/d240a0be972335f43fc2bacc4b124e72a32f74d4
Author: David Spickett <david.spickett at arm.com>
Date: 2026-10-01 (Thu, 01 Oct 2026)
Changed paths:
M lldb/test/API/functionalities/thread/exit_during_step/TestExitDuringStep.py
M lldb/test/API/functionalities/thread/thread_exit/TestThreadExit.py
Log Message:
-----------
[lldb][test] Use external debug info on Arm in TestExitDuringStep and TestThreadExit (#228047)
Arm has to care about Arm and Thumb modes, so without the separate debug
info file installed by libc6-dbg on Linux, we cannot backtrace if the
starting point is in a libc function.
This is the case for these tests where a thread may be stopped in a libc
syscall wrapper.
As the backtrace wasn't working, the code added by #227312 did not see
that some threads were part of the main executable, which made both
these tests fail on Arm Linux.
It's possible we should be running more tests on Arm with this option
on, but for now I just want to get the bot back to green.
More details in https://github.com/llvm/llvm-project/issues/228014.
Commit: 2ccba9abdcdb293df159015d04611ed220ac86fe
https://github.com/llvm/llvm-project/commit/2ccba9abdcdb293df159015d04611ed220ac86fe
Author: Karthika Devi C <kartc at qti.qualcomm.com>
Date: 2026-10-01 (Thu, 01 Oct 2026)
Changed paths:
M polly/lib/Analysis/ScopBuilder.cpp
A polly/test/ScopInfo/assume_in_non_affine_subregion.ll
Log Message:
-----------
[Polly] Fix assertion in addUserAssumptions for unreachable blocks (#227311)
ScopBuilder::addUserAssumptions() crashes when an llvm.assume call
resides in a block that has no entry in InvalidDomainMap. This happens
when __builtin_unreachable() is converted to llvm.assume by earlier
passes, but Polly's buildDomainsWithBranchConstraints() skips the block
(e.g. due to an UnreachableInst terminator), leaving its
InvalidDomainMap entry uninitialized.
Skip such assumptions instead of asserting.
Fixes #226718
Commit: a938559a914538ef3ee82aaa323820e26cd62cf5
https://github.com/llvm/llvm-project/commit/a938559a914538ef3ee82aaa323820e26cd62cf5
Author: Alok Kumar Sharma <AlokKumar.Sharma at amd.com>
Date: 2026-10-01 (Thu, 01 Oct 2026)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp
M llvm/test/Transforms/InstCombine/pull-conditional-binop-through-shift.ll
Log Message:
-----------
[InstCombine] Keep branch weights when folding a shift through a select (#227987)
Pulling a binop out of a select and through a constant shift rebuilds
the select, and the new one was losing the original branch weights. Copy
!prof so the weights stay attached to the same condition.
Commit: 3013507d8e702c40d0ee1ac1ee4d551742092fa8
https://github.com/llvm/llvm-project/commit/3013507d8e702c40d0ee1ac1ee4d551742092fa8
Author: Deepak Shirke <deepakshirke509 at gmail.com>
Date: 2026-10-01 (Thu, 01 Oct 2026)
Changed paths:
Log Message:
-----------
[GlobalISel] [AArch64] Skip redundant shift amount masking during isel (#223136)
AArch64 shift instructions (LSL/LSR/ASR) only use the low 5 bits (i32)or
6 bits (i64) of the shift amount. When the shift amount is masked with
an AND that was introduced by legalization of a narrow type zext, or is
a G_ZEXT itself, the operation is redundant and can be skipped during
instruction selection.
This mirrors what AArch64DAGToDAGISel::tryShiftAmountMod does for
SelectionDAG, bringing GlobalISel to parity for i32 shift amounts with
narrow shift amount types (i8, i16).
Before (GlobalISel shl i32 with i8 shift amount):
and w8, w1, #0xff
lsl w0, w0, w8
After (matches SelectionDAG):
lsl w0, w0, w1
Part of the incremental work tracked in
https://github.com/llvm/llvm-project/issues/224245 to replace
tryShiftAmountMod with ComplexPattern-based isel.
Commit: 956278f0f570085eb9a2bc2a1de32d142aeb233f
https://github.com/llvm/llvm-project/commit/956278f0f570085eb9a2bc2a1de32d142aeb233f
Author: Maddy Dunn <madeleine.dunn at arm.com>
Date: 2026-10-01 (Thu, 01 Oct 2026)
Changed paths:
M mlir/include/mlir/Dialect/Tosa/IR/TosaComplianceData.h.inc
M mlir/test/Dialect/Tosa/invalid_extension.mlir
M mlir/test/Dialect/Tosa/ops.mlir
M mlir/test/Dialect/Tosa/tosa-validation-version-1p0-invalid.mlir
M mlir/test/Dialect/Tosa/tosa-validation-version-1p1-valid.mlir
Log Message:
-----------
[mlir][tosa] Add MXFP support for GATHER (#227710)
Change-Id: I007889a6d934c8588feae7d2c5a023df60c85ca5
Signed-off-by: Madeleine Dunn <madeleine.dunn at arm.com>
Commit: 8068182dd6fb1a8efae0291db1d2462d29025cd1
https://github.com/llvm/llvm-project/commit/8068182dd6fb1a8efae0291db1d2462d29025cd1
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-10-01 (Thu, 01 Oct 2026)
Changed paths:
M llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
M llvm/test/CodeGen/Hexagon/two-addr-tied-subregs.mir
M llvm/test/CodeGen/SystemZ/twoaddr-kill.mir
M llvm/test/CodeGen/X86/statepoint-cmp-sunk-past-statepoint.ll
M llvm/test/CodeGen/X86/statepoint-vreg-unlimited-tied-opnds.ll
M llvm/test/CodeGen/X86/two-address-subreg-to-reg-kill.mir
M llvm/test/CodeGen/X86/twoaddr-dbg-value.mir
Log Message:
-----------
CodeGen: Remove LiveVariables use from TwoAddressInstructionPass (#225176)
Now that LiveIntervals is computed unconditionally before TwoAddressInstructions
in the pipeline, the pass no longer needs LiveVariables.
Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
Commit: 53fb269f4658238671cebdf22fbd46e3fd3eab45
https://github.com/llvm/llvm-project/commit/53fb269f4658238671cebdf22fbd46e3fd3eab45
Author: KRM7 <krisztian.rugasi at arm.com>
Date: 2026-10-01 (Thu, 01 Oct 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/test/CodeGen/AArch64/arm64-vadd.ll
M llvm/test/CodeGen/AArch64/clmul-fixed.ll
M llvm/test/CodeGen/AArch64/neon-rshrn.ll
Log Message:
-----------
[AArch64] Select ADDHN instead of SHRN when possible (#225094)
The throughput of the ADDHN instruction is either double or the same as
the throughput of the SHRN instruction almost everywhere, so it's better
to use ADDHN when possible.
Commit: e8848e5fedbad3f20c9412eedf84fc35f6e5229a
https://github.com/llvm/llvm-project/commit/e8848e5fedbad3f20c9412eedf84fc35f6e5229a
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-10-01 (Thu, 01 Oct 2026)
Changed paths:
R llvm/test/CodeGen/AMDGPU/phi-elimination-split-critical-edge-nonoverlapping-subrange.mir
M llvm/test/CodeGen/AMDGPU/phi-elimination-split-critical-edge-subranges.mir
Log Message:
-----------
AMDGPU: Merge live interval critical edge splitting tests (#228051)
Commit: fc1f06592eb222bfdc03dc298a5952b577bc18b1
https://github.com/llvm/llvm-project/commit/fc1f06592eb222bfdc03dc298a5952b577bc18b1
Author: Graham Hunter <graham.hunter at arm.com>
Date: 2026-10-01 (Thu, 01 Oct 2026)
Changed paths:
M clang/docs/CIR/CleanupAndEHDesign.md
M clang/docs/ReleaseNotes.md
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/lib/CIR/Dialect/Analysis/CIRBasicAliasAnalysis.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
M clang/lib/Sema/SemaExpr.cpp
M clang/test/CIR/Analysis/alias-analysis-underlying-object.cir
M clang/test/CIR/CodeGen/base-init-eh.cpp
M clang/test/CIR/CodeGen/base-to-derived.cpp
M clang/test/CIR/CodeGen/class.cpp
M clang/test/CIR/CodeGen/cleanup-derived-to-base-ref.cpp
M clang/test/CIR/CodeGen/ctor-null-init.cpp
M clang/test/CIR/CodeGen/ctor-try-body.cpp
M clang/test/CIR/CodeGen/ctor.cpp
M clang/test/CIR/CodeGen/delegating-ctor.cpp
M clang/test/CIR/CodeGen/derived-to-base.cpp
M clang/test/CIR/CodeGen/destructor-vtable-reinit-strict.cpp
M clang/test/CIR/CodeGen/destructor-vtable-reinit.cpp
M clang/test/CIR/CodeGen/dtors.cpp
M clang/test/CIR/CodeGen/inherited-ctors.cpp
M clang/test/CIR/CodeGen/multi-vtable.cpp
M clang/test/CIR/CodeGen/paren-list-agg-init.cpp
M clang/test/CIR/CodeGen/temporary-materialization-adjust.cpp
M clang/test/CIR/CodeGen/vbase.cpp
M clang/test/CIR/CodeGen/virtual-destructor-calls.cpp
M clang/test/CIR/CodeGen/vtt.cpp
M clang/test/CIR/IR/vtt-addrpoint.cir
M clang/test/CIR/Lowering/vtt-addrpoint.cir
M clang/test/CIR/Transforms/pure-ptr-arithmetic.cir
M clang/test/Sema/fp16vec-sema.c
M clang/test/Sema/vector-ops.c
M clang/test/SemaCXX/vector.cpp
M flang/docs/OpenMPSupport.md
M flang/include/flang/Optimizer/Transforms/Passes.h
M flang/include/flang/Optimizer/Transforms/Passes.td
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/lib/Optimizer/Passes/Pipelines.cpp
M flang/lib/Optimizer/Transforms/CMakeLists.txt
A flang/lib/Optimizer/Transforms/O0CanonicalizerPass.cpp
M flang/test/Driver/mlir-debug-pass-pipeline.f90
M flang/test/Driver/mlir-pass-pipeline.f90
M flang/test/Integration/OpenMP/parallel-private-reduction-worstcase.f90
A flang/test/Integration/array-assignment-entry-debug.f90
A flang/test/Integration/array-assignment-entry-paths.f90
M flang/test/Integration/cold_array_repacking.f90
M flang/test/Lower/OpenMP/collapse-imperfect-nest.f90
R flang/test/Lower/OpenMP/collapse-target-intervening-todo.f90
A flang/test/Transforms/o0-canonicalize.mlir
M lldb/test/API/functionalities/thread/exit_during_step/TestExitDuringStep.py
M lldb/test/API/functionalities/thread/thread_exit/TestThreadExit.py
M llvm/include/llvm/Analysis/ConstraintSystem.h
M llvm/include/llvm/Frontend/OpenMP/OMP.h
M llvm/include/llvm/Frontend/OpenMP/OMPDescriptors.h
M llvm/include/llvm/IR/IRBuilder.h
M llvm/include/llvm/IR/PatternMatch.h
M llvm/include/llvm/Support/Compiler.h
M llvm/include/llvm/Transforms/Vectorize/LoopVectorizationLegality.h
M llvm/lib/Analysis/ConstraintSystem.cpp
M llvm/lib/Analysis/InstructionSimplify.cpp
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/lib/CodeGen/CodeGenPrepare.cpp
M llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
M llvm/lib/CodeGen/WasmEHPrepare.cpp
M llvm/lib/ExecutionEngine/Orc/TargetProcess/RegisterEHFrames.cpp
M llvm/lib/IR/AutoUpgrade.cpp
M llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
M llvm/lib/Target/AArch64/AArch64InstrFormats.td
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/AArch64SchedNeoverseV1.td
M llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td
M llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/VOP1Instructions.td
M llvm/lib/Target/AMDGPU/VOPInstructions.td
M llvm/lib/Target/ARM/ARMFastISel.cpp
M llvm/lib/Target/ARM/MVEGatherScatterLowering.cpp
M llvm/lib/Target/Mips/MipsCallLowering.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyLowerEmscriptenEHSjLj.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyRefTypeMem2Local.cpp
M llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
M llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp
M llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
M llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
M llvm/lib/Transforms/Scalar/LoopSimplifyCFG.cpp
M llvm/lib/Transforms/Scalar/ScalarizeMaskedMemIntrin.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlanPatternMatch.h
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.h
M llvm/test/Analysis/CostModel/AMDGPU/fsub.ll
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/intrinsics.ll
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/irreducible/branch-outside.ll
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/irreducible/exit-divergence.ll
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/irreducible/reducible-headers.ll
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/phi_div_loop.ll
M llvm/test/CodeGen/AArch64/GlobalISel/split-wide-shifts-multiway.ll
M llvm/test/CodeGen/AArch64/arm64-vadd.ll
M llvm/test/CodeGen/AArch64/clmul-fixed.ll
M llvm/test/CodeGen/AArch64/frem-power2.ll
M llvm/test/CodeGen/AArch64/fsh.ll
M llvm/test/CodeGen/AArch64/funnel-shift.ll
M llvm/test/CodeGen/AArch64/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll
M llvm/test/CodeGen/AArch64/hoist-and-by-const-from-shl-in-eqcmp-zero.ll
M llvm/test/CodeGen/AArch64/neon-rshrn.ll
M llvm/test/CodeGen/AArch64/select_const.ll
M llvm/test/CodeGen/AArch64/shift-mod.ll
M llvm/test/CodeGen/AArch64/shift.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.workgroup.id.ll
M llvm/test/CodeGen/AMDGPU/cgp-addressing-modes.ll
M llvm/test/CodeGen/AMDGPU/default-fp-mode.ll
M llvm/test/CodeGen/AMDGPU/dpp_combine-true16.mir
M llvm/test/CodeGen/AMDGPU/ds_read2.ll
M llvm/test/CodeGen/AMDGPU/fmin_fmax_legacy.amdgcn.ll
M llvm/test/CodeGen/AMDGPU/hsa-metadata-agpr-small.ll
M llvm/test/CodeGen/AMDGPU/internalize.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sdot4.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.workgroup.id.ll
M llvm/test/CodeGen/AMDGPU/lshl-add-u64.ll
M llvm/test/CodeGen/AMDGPU/merge-m0.mir
M llvm/test/CodeGen/AMDGPU/merge-out-of-order-ldst.ll
M llvm/test/CodeGen/AMDGPU/mubuf-offset-private.ll
R llvm/test/CodeGen/AMDGPU/phi-elimination-split-critical-edge-nonoverlapping-subrange.mir
M llvm/test/CodeGen/AMDGPU/phi-elimination-split-critical-edge-subranges.mir
M llvm/test/CodeGen/AMDGPU/set-wave-priority.ll
M llvm/test/CodeGen/AMDGPU/shift-select.ll
M llvm/test/CodeGen/AMDGPU/token-factor-inline-limit-test.ll
M llvm/test/CodeGen/AMDGPU/triv-disjoint-mem-access-neg-offset.mir
M llvm/test/CodeGen/AMDGPU/vector-alloca-bitcast.ll
A llvm/test/CodeGen/ARM/fast-isel-call-be-softfp.ll
M llvm/test/CodeGen/Hexagon/two-addr-tied-subregs.mir
M llvm/test/CodeGen/Mips/GlobalISel/irtranslator/call.ll
M llvm/test/CodeGen/Mips/GlobalISel/irtranslator/global_address_pic.ll
M llvm/test/CodeGen/SystemZ/twoaddr-kill.mir
M llvm/test/CodeGen/X86/statepoint-cmp-sunk-past-statepoint.ll
M llvm/test/CodeGen/X86/statepoint-vreg-unlimited-tied-opnds.ll
M llvm/test/CodeGen/X86/two-address-subreg-to-reg-kill.mir
M llvm/test/CodeGen/X86/twoaddr-dbg-value.mir
M llvm/test/MC/AMDGPU/dpp-err.s
M llvm/test/MC/AMDGPU/gfx1150_asm_salu_float.s
M llvm/test/MC/AMDGPU/gfx9-asm-err.s
M llvm/test/MC/Disassembler/AMDGPU/gfx9_dasm_err.txt
M llvm/test/Transforms/InstCombine/add.ll
M llvm/test/Transforms/InstCombine/fadd.ll
M llvm/test/Transforms/InstCombine/pull-conditional-binop-through-shift.ll
A llvm/test/Transforms/InstCombine/smulh.ll
A llvm/test/Transforms/InstCombine/umulh.ll
M llvm/test/Transforms/LoopVectorize/AArch64/maxbandwidth-regpressure.ll
M llvm/test/Transforms/LoopVectorize/AArch64/predication_costs.ll
M llvm/test/Transforms/LoopVectorize/VPlan/early_exit_with_stores_vplan.ll
M llvm/test/Transforms/LoopVectorize/X86/vectorization-remarks-missed.ll
M llvm/test/Transforms/LoopVectorize/early_exit_combined_exits.ll
A llvm/test/Transforms/LoopVectorize/early_exit_combined_exits_epilogue.ll
M llvm/test/Transforms/LoopVectorize/early_exit_legality.ll
M llvm/test/Transforms/LoopVectorize/early_exit_store_legality.ll
M llvm/test/Transforms/LoopVectorize/early_exit_with_stores.ll
M llvm/test/Transforms/LoopVectorize/fold-epilogue-tail.ll
M llvm/test/Transforms/LoopVectorize/uncountable-single-exit-loops.ll
M llvm/test/Transforms/PhaseOrdering/AArch64/countable-and-uncountable-exits-combined.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/gather-buildvector-with-minbitwidth-user.ll
M llvm/test/tools/llvm-mca/AArch64/Neoverse/V1-neon-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-neon-instructions.s
M llvm/unittests/Analysis/ConstraintSystemTest.cpp
M llvm/unittests/Frontend/EnumSetTest.cpp
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVAtomicOps.td
M mlir/include/mlir/Dialect/Tosa/IR/TosaComplianceData.h.inc
M mlir/lib/Conversion/VectorToGPU/VectorToGPU.cpp
M mlir/lib/Dialect/SPIRV/IR/AtomicOps.cpp
M mlir/lib/Dialect/SPIRV/IR/MemoryOps.cpp
M mlir/test/Dialect/SPIRV/IR/atomic-ops.mlir
M mlir/test/Dialect/SPIRV/IR/memory-ops.mlir
M mlir/test/Dialect/Tosa/invalid_extension.mlir
M mlir/test/Dialect/Tosa/ops.mlir
M mlir/test/Dialect/Tosa/tosa-validation-version-1p0-invalid.mlir
M mlir/test/Dialect/Tosa/tosa-validation-version-1p1-valid.mlir
A offload/test/offloading/fortran/target-teams-distribute-collapse-intervening.f90
M polly/lib/Analysis/ScopBuilder.cpp
A polly/test/ScopInfo/assume_in_non_affine_subregion.ll
Log Message:
-----------
Merge branch 'main' into users/huntergr-arm/splat-pattern-match
Compare: https://github.com/llvm/llvm-project/compare/4d62796e5cce...fc1f06592eb2
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