[all-commits] [llvm/llvm-project] cf4640: [RISCV] Remove riscv_mulh_i32/riscv_mulhu_u32 intr...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: cf46406f7ebc929d422a549e739c34904f47232a
      https://github.com/llvm/llvm-project/commit/cf46406f7ebc929d422a549e739c34904f47232a
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2026-09-30 (Wed, 30 Sep 2026)

  Changed paths:
    M clang/lib/CodeGen/TargetBuiltins/RISCV.cpp
    M clang/test/CodeGen/RISCV/rvp-intrinsics.c
    M cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c
    M llvm/include/llvm/IR/IntrinsicsRISCV.td
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rvp-simd-32.ll

  Log Message:
  -----------
  [RISCV] Remove riscv_mulh_i32/riscv_mulhu_u32 intrinsics. (#227819)

These are redundant with the llvm.smulh/umulh intrinsics that were
recently added.

This changes codegen because smulh/umulh are currently generically type
legalized with extends+mul+srli instead of using pmulh(u).w. This isn't
always a regression. Sometimes we are able to prove the inputs are
already extended or we use mul(u).w00 and sometimes we needed a sext.w
after the pmulh(u).w. I will handle this as a follow up as it will
affect more tests.



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