[all-commits] [llvm/llvm-project] 98ed2f: [ConstantTime] Drop the combine barrier from CT_SE...

[Akshay K via All-commits]

  Branch: refs/heads/users/wizardengineer/ct-select-core
  Home:   https://github.com/llvm/llvm-project
  Commit: 98ed2f367b27763682404330bd361c11a47a11c3
      https://github.com/llvm/llvm-project/commit/98ed2f367b27763682404330bd361c11a47a11c3
  Author: AkshayK <iit.akshay at gmail.com>
  Date:   2026-09-30 (Wed, 30 Sep 2026)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
    M llvm/test/CodeGen/RISCV/ctselect-fallback-gisel.ll
    M llvm/test/CodeGen/RISCV/ctselect-fallback-scalable.ll
    M llvm/test/CodeGen/RISCV/ctselect-fallback.ll
    M llvm/test/CodeGen/X86/ctselect.ll

  Log Message:
  -----------
  [ConstantTime] Drop the combine barrier from CT_SELECT expansion

ARITH_FENCE is only specified for FP types, and the earlier vreg copy
had the legalizer picking register classes. No in-tree combine folds
the XOR/AND/XOR sequence back into a select, so emit it without a
barrier. A dedicated barrier op will come in a follow-up.



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