[all-commits] [llvm/llvm-project] a18705: [AArch64][NeoverseV1/V2] Fix ASIMD FP convert and ...

[Julien Villette via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: a187057dfe16b215dc44c4be7937ceccebe9882a
      https://github.com/llvm/llvm-project/commit/a187057dfe16b215dc44c4be7937ceccebe9882a
  Author: Julien Villette <julien.villette at gmail.com>
  Date:   2026-09-30 (Wed, 30 Sep 2026)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64SchedNeoverseV1.td
    M llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td
    M llvm/test/tools/llvm-mca/AArch64/Neoverse/V1-basic-instructions.s
    M llvm/test/tools/llvm-mca/AArch64/Neoverse/V1-bf16-instructions.s
    M llvm/test/tools/llvm-mca/AArch64/Neoverse/V1-neon-instructions.s
    M llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-bf16-instructions.s
    M llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-fptoint-instructions.s
    M llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-neon-instructions.s

  Log Message:
  -----------
  [AArch64][NeoverseV1/V2] Fix ASIMD FP convert and round scheduling (#224046)

Measured on Neoverse V1 and V2 hardware with unrolled loops of
independent instances, using perf inst_spec/op_spec counters for the
micro-op counts. Both cores measure identically on every test below.

| Instruction          | uop | Latency | RThroughput | was       |
|----------------------|-----|---------|-------------|-----------|
| fcvtas h0, h1        | 1   | 3       | 0.50        | 4/6/1.00  |
| fcvtas s0, s1        | 1   | 3       | 0.50        | 2/4/1.00  |
| fcvtzs w0, s1, #1    | 1   | 3       | 1.00        | 1/3/0.50  |
| fcvtas v0.4s, v1.4s  | 1   | 4       | 1.00        | 2 uops    |
| fcvtas v0.8h, v1.8h  | 1   | 6       | 2.00        | 4/6/1.00  |
| frinta v0.8h, v1.8h  | 1   | 6       | 2.00        | 4/6/1.00  |
| bfcvtn v0.4h, v0.4s  | 1   | 4       | 1.00        | 1/4/0.50  |

Scalar H and S conversions were grouped with wider vector forms; they
measure the same as the D-form F32 row, so they move there.

Fixed-point conversions to a general register were missed by the InstRW
regex on V1, which now covers the "ri" suffix as V2 already did.

On V2 the reworked classes are new definitions, since the originals are
shared with the SVE and reciprocal-estimate rules; on V1 they had no
other user and are updated in place.



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