[all-commits] [llvm/llvm-project] a5a1b5: [Hexagon] Fix hwloop trip count for post-increment...

[Santanu Das via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: a5a1b5834ad33167aa119091a96931d526c9c962
      https://github.com/llvm/llvm-project/commit/a5a1b5834ad33167aa119091a96931d526c9c962
  Author: Santanu Das <santdas at qti.qualcomm.com>
  Date:   2026-09-30 (Wed, 30 Sep 2026)

  Changed paths:
    M llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp
    M llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
    M llvm/lib/Target/Hexagon/HexagonInstrInfo.h
    A llvm/test/CodeGen/Hexagon/hwloop-postinc-iv-ptrchase.ll
    A llvm/test/CodeGen/Hexagon/hwloop-postinc-iv-tied-operands-hvx.ll
    A llvm/test/CodeGen/Hexagon/hwloop-postinc-iv-tied-operands.ll

  Log Message:
  -----------
  [Hexagon] Fix hwloop trip count for post-increment load induction (#225411)

A pointer-chasing loop whose exit test is a null check was miscompiled
into a hardware loop with a bogus trip count.

A post-increment load defines two registers:
%3, %11 = L2_loadri_pi %1(tied-def 1), 4
%11 is the incremented address (tied to the base), but %3 is the value
loaded from memory, which bears no relation to the base. The helper only
checked that the base register is defined by the PHI, never that the
register feeding the PHI back from the latch is the incremented address.
Here the PHI is fed by %3 -- so the loop was treated as bumping its
induction variable by a constant 4 per iteration, and getLoopTripCount
derived a count from the numeric value of head.

Require that the register feeding the PHI is the post-incremented
address, located through the base operand's tie rather than a fixed
operand index: the tied def is operand 1 for loads (L2_loadri_pi,
V6_vL32b_pi) but operand 0 for stores (S2_storeri_pi, V6_vS32b_pi), and
predicated forms shift both positions.

---------

Co-authored-by: quic-santdas <quic_santdas at qti.qualcomm.com>



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