[all-commits] [llvm/llvm-project] 40e834: [RISC-V][MC][RVY] Update to v0.9.10 specification ...

[Alexander Richardson via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 40e834bb7054cacfff0c68c0b76c0a4dba7f2ab8
      https://github.com/llvm/llvm-project/commit/40e834bb7054cacfff0c68c0b76c0a4dba7f2ab8
  Author: Alexander Richardson <alexrichardson at google.com>
  Date:   2026-09-29 (Tue, 29 Sep 2026)

  Changed paths:
    M clang/test/Driver/print-supported-extensions-riscv.c
    M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
    M llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
    M llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
    M llvm/lib/Target/RISCV/RISCVFeatures.td
    M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfoY.td
    M llvm/test/CodeGen/RISCV/attributes.ll
    M llvm/test/CodeGen/RISCV/rvy/rvy-invalid-operands.mir
    M llvm/test/MC/RISCV/rvy-build-attributes.s
    M llvm/test/MC/RISCV/rvy-invalid-attributes.s
    M llvm/test/MC/RISCV/rvy/rvy-basic-invalid.s
    M llvm/test/MC/RISCV/rvy/rvy-basic.s
    M llvm/unittests/TargetParser/RISCVISAInfoTest.cpp

  Log Message:
  -----------
  [RISC-V][MC][RVY] Update to v0.9.10 specification (#227554)

Update the experimental 'Y' base ISA to 0.9.10 (0p910) and sync the base
RVY instruction encodings and mnemonics with the v0.9.10 draft
specification (https://github.com/riscv/riscv-cheri/releases/tag/v0.9.10-ar20260929):

* Replace `SRLIY` and the `yhir` alias with a dedicated 2-operand `YHIR`
  instruction (`funct7 = 0b1111010`, `funct5 = 0b00111`), and remove the
  now-unused `uimm7_eq_xlen` operand support.
* Drop `PACKY` in favor of `YHIW` (`rd = YGPR`, `rs1 = GPR`, `rs2 = GPR`).
* Rename `YSUNSEAL` to `YUNSEALS` and add `YSEALE` (`funct7 = 0b0010111`,
  `rs1 = x0`).

This commit was created with the help of AI tools

Pull-Request: https://github.com/llvm/llvm-project/pull/227554



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