[all-commits] [llvm/llvm-project] 9db7ac: [RISC-V][MC] Reject x0 as the address/temporary re...

[Alexander Richardson via All-commits]

  Branch: refs/heads/users/arichardson/risc-v-mc-reject-x0-as-the-temporary-register-for-store
  Home:   https://github.com/llvm/llvm-project
  Commit: 9db7ace37461ca4f0ebd84d4aa804300ac6f7a1b
      https://github.com/llvm/llvm-project/commit/9db7ace37461ca4f0ebd84d4aa804300ac6f7a1b
  Author: Alex Richardson <alexrichardson at google.com>
  Date:   2026-09-29 (Tue, 29 Sep 2026)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrFormats.td
    M llvm/test/MC/RISCV/rvi-pseudos-invalid.s

  Log Message:
  -----------
  [RISC-V][MC] Reject x0 as the address/temporary register for load/store pseudos

Using the zero register as the destination for integer load pseudos or as
the temporary register for floating-point load and store pseudos is
illegal since it is used to synthesize the target address, and using x0
would mean the auipc/qc.e.li result is ignored and we access an invalid
location.

This commit was created with the help of AI tools


  Commit: 7c7d56f8ad7ded1205c6603700a44029e3c116d0
      https://github.com/llvm/llvm-project/commit/7c7d56f8ad7ded1205c6603700a44029e3c116d0
  Author: Alex Richardson <alexrichardson at google.com>
  Date:   2026-09-29 (Tue, 29 Sep 2026)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrFormats.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoZclsd.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoZilsd.td
    M llvm/test/MC/RISCV/corev/XCVelw-invalid.s
    M llvm/test/MC/RISCV/rv32zilsd-invalid.s
    M llvm/test/MC/RISCV/rvi-pseudos-invalid.s
    M llvm/test/MC/RISCV/xqcilo-pseudos-invalid.s

  Log Message:
  -----------
  add support for the other pseudos too


Compare: https://github.com/llvm/llvm-project/compare/f0e6410285a0...7c7d56f8ad7d

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