[all-commits] [llvm/llvm-project] d87e01: [AMDGPU][GlobalISel] Keep typed LLTs in RegBankLeg...

[Chinmay Deshpande via All-commits]

  Branch: refs/heads/users/chinmaydd/amdgpu-rbl-combiner-typed-llt
  Home:   https://github.com/llvm/llvm-project
  Commit: d87e010b3c99f7baa30b93789b33980074744444
      https://github.com/llvm/llvm-project/commit/d87e010b3c99f7baa30b93789b33980074744444
  Author: Chinmay Deshpande <chdeshpa at amd.com>
  Date:   2026-09-29 (Tue, 29 Sep 2026)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalize.cpp
    A llvm/test/CodeGen/AMDGPU/GlobalISel/regbanklegalize-combine-s1.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-anyext.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui-regbanklegalize.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui.mir

  Log Message:
  -----------
  [AMDGPU][GlobalISel] Keep typed LLTs in RegBankLegalize combines

The S1 cleanup combines in AMDGPURegBankLegalize built new registers
with an untyped s32, missed when lowering switched to extended LLTs.
The regbank combiner later unified these with typed registers, so
constrainRegAttrs retyped e.g. an i32 G_CTPOP result to s32, which
failed instruction selection.

Take the type from the source or destination register instead.

Change-Id: I06cfb7278af045dbaa3ca0cc6c77a3938f4cef01
Co-Authored-By: Claude Opus 5.5 (1M context) <noreply at anthropic.com>



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