[all-commits] [llvm/llvm-project] 4d7013: [AMDGPU][GlobalISel] Fold neg/abs modifiers when m...

[Domenic Nutile via All-commits]

  Branch: refs/heads/users/saxlungs/fma-mix-lo-neg-fold
  Home:   https://github.com/llvm/llvm-project
  Commit: 4d701319cd914091d382acecbee1b014154099fa
      https://github.com/llvm/llvm-project/commit/4d701319cd914091d382acecbee1b014154099fa
  Author: Domenic Nutile <domenic.nutile at gmail.com>
  Date:   2026-09-29 (Tue, 29 Sep 2026)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-ext-neg-mul.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll
    M llvm/test/CodeGen/AMDGPU/mad-mix.ll

  Log Message:
  -----------
  [AMDGPU][GlobalISel] Fold neg/abs modifiers when mad-mix selects the low half

selectVOP3PMadMixModsImpl re-runs the fneg/fabs match after rewriting Src
to the 32-bit register the 16-bit value is a half of, but only did so on
the isExtractHiElt path, not for isExtractLoElt.

The two halves are not symmetric. An fneg/fabs of a 32-bit float only
touches bit 31, which is the sign bit of the high half, so folding it
into a modifier on the selected high half is correct. The low half's sign
bit is bit 15, which such an fneg/fabs leaves alone, so only a modifier
that acts on each 16-bit element can be folded there. So the source must be
a 2 x 16-bit vector to fold it.


  Commit: 0c7c264ac6539ac4de53a58491e9c7826073e999
      https://github.com/llvm/llvm-project/commit/0c7c264ac6539ac4de53a58491e9c7826073e999
  Author: Domenic Nutile <domenic.nutile at gmail.com>
  Date:   2026-09-29 (Tue, 29 Sep 2026)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp

  Log Message:
  -----------
  Use isFixedVector instead of LLT equality


Compare: https://github.com/llvm/llvm-project/compare/aebcdfe69f47...0c7c264ac653

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