[all-commits] [llvm/llvm-project] 726746: [LV] Add tests for zero branch weights and executi...
Syadus Sefat via All-commits
all-commits at lists.llvm.org
Tue Sep 29 12:41:44 PDT 2026
Branch: refs/heads/users/mssefat/anti-hints-pr4-amdgpu-pre-ra
Home: https://github.com/llvm/llvm-project
Commit: 72674697a28c25467649c4993eb033dc4af65951
https://github.com/llvm/llvm-project/commit/72674697a28c25467649c4993eb033dc4af65951
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/test/Transforms/LoopVectorize/VPlan/execution-frequencies-match-bfi.ll
M llvm/test/Transforms/LoopVectorize/X86/predicated-instruction-cost.ll
M llvm/test/Transforms/LoopVectorize/replicate-region-branch-weights.ll
Log Message:
-----------
[LV] Add tests for zero branch weights and execution frequencies (NFC). (#226553)
Add missing test coverage for VPlan-based execution frequency
computation:
* blocks entered via an edge with zero branch weight,
* blocks whose sibling edge has zero weight,
* nested branches whose skipping edges have zero weight,
* a block executing on all paths through the loop after a switch whose
probabilities do not add up to 1,
* frequencies below the smallest representable non-zero one
* all-zero weights making a join's frequency unknown
* estimated frequencies propagating through a branch with weights.
Also updates
llvm/test/Transforms/LoopVectorize/VPlan/execution-frequencies-match-bfi.ll
to check frequencies directly after the frequencies have been recorded.
Commit: a9809116ca6130906f20c727464ba8e878b59aa5
https://github.com/llvm/llvm-project/commit/a9809116ca6130906f20c727464ba8e878b59aa5
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M .github/workflows/libcxx-benchmark-commit.yml
M .github/workflows/libcxx-benchmark-cron.yml
M .github/workflows/libcxx-pr-benchmark.yml
M libcxx/utils/ci/lnt/README.md
M libcxx/utils/ci/lnt/machines.json
M libcxx/utils/ci/lnt/run-benchmarks
M libcxx/utils/ci/run-buildbot
Log Message:
-----------
[libc++] Add a benchmark machine for libstdc++ (#226346)
Add a machine that benchmarks the libstdc++ shipped with GCC 16 on macOS
instead of a libc++ build. To enable that, generalize the scripts and
workflows to make more aspects of machines.json optional (e.g. support
machines that don't need to build libc++).
Commit: 8dc7b3d92cc6371d942dc7619a81faa1f56de938
https://github.com/llvm/llvm-project/commit/8dc7b3d92cc6371d942dc7619a81faa1f56de938
Author: Joshua Batista <jbatista at microsoft.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M clang/include/clang/Basic/Builtins.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Basic/HLSLIntrinsics.td
M clang/lib/CodeGen/CGHLSLBuiltins.cpp
M clang/lib/CodeGen/CGHLSLRuntime.h
M clang/lib/Sema/SemaHLSL.cpp
A clang/test/CodeGenHLSL/builtins/WaveReadLaneFirst.hlsl
A clang/test/SemaHLSL/BuiltIns/WaveReadLaneFirst-errors.hlsl
M clang/test/SemaHLSL/WaveBuiltinAvailability.hlsl
M llvm/include/llvm/IR/IntrinsicsDirectX.td
M llvm/include/llvm/IR/IntrinsicsSPIRV.td
M llvm/lib/Target/DirectX/DXIL.td
M llvm/lib/Target/DirectX/DXILShaderFlags.cpp
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
A llvm/test/CodeGen/DirectX/LongVector/wave-readlane-first.ll
M llvm/test/CodeGen/DirectX/ShaderFlags/wave-ops.ll
A llvm/test/CodeGen/DirectX/WaveReadLaneFirst.ll
A llvm/test/CodeGen/DirectX/WaveReadLaneFirst_mat.ll
A llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_long_vector/wave-readlane-first.ll
A llvm/test/CodeGen/SPIRV/hlsl-intrinsics/WaveReadLaneFirst.ll
A llvm/test/CodeGen/SPIRV/hlsl-intrinsics/WaveReadLaneFirst_mat.ll
Log Message:
-----------
Add WaveReadLaneFirst HLSL function (#220373)
This PR adds the `WaveReadLaneFirst` HLSL function.
Fixes https://github.com/llvm/llvm-project/issues/99164
Assisted by: Github Copilot
Commit: 7b42d2f9991c3680627878a49b1b323cb56176a0
https://github.com/llvm/llvm-project/commit/7b42d2f9991c3680627878a49b1b323cb56176a0
Author: Nico Weber <thakis at chromium.org>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/Target/AMDGPU/BUILD.gn
Log Message:
-----------
[gn build] Port 07aec21c88f4 (#226571)
Commit: cc527d5399997024a68be6241e3a70a6f05a338e
https://github.com/llvm/llvm-project/commit/cc527d5399997024a68be6241e3a70a6f05a338e
Author: Nico Weber <thakis at chromium.org>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/utils/gn/secondary/lld/unittests/AsLibELF/BUILD.gn
Log Message:
-----------
[gn] port b3ed324d42c04 (#226570)
Commit: bbd2e0f7ce13d2a1ff8336018d3b034eb3c698a0
https://github.com/llvm/llvm-project/commit/bbd2e0f7ce13d2a1ff8336018d3b034eb3c698a0
Author: Jiaxun Yang <jiaxun.yang at flygoat.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/Target/Mips/MipsISelLowering.cpp
M llvm/test/CodeGen/Mips/extins.ll
Log Message:
-----------
[Mips] Enable generic bitfield extract preparation (#226491)
Enable CodeGenPrepare's shift sinking when the subtarget supports
bitfield extract instructions. This exposes shift-and-mask patterns
across basic blocks to the existing MIPS extract combine.
Use hasExtractInsert() to keep this disabled for pre-r2 targets and
MIPS16. Add a minimal cross-block regression case to extins.ll.
Commit: 5bc083e278a59853fcfcf3649ba7a20457ead1e5
https://github.com/llvm/llvm-project/commit/5bc083e278a59853fcfcf3649ba7a20457ead1e5
Author: Nico Weber <thakis at chromium.org>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/utils/gn/secondary/lld/unittests/AsLibELF/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/DebugInfo/LogicalView/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/DebugInfo/PDB/BUILD.gn
Log Message:
-----------
[gn] port b3ed324d42c04 more (#226574)
Commit: 0a21a0712b800a3cc1af87e1d0ceb1a84f2b24bd
https://github.com/llvm/llvm-project/commit/0a21a0712b800a3cc1af87e1d0ceb1a84f2b24bd
Author: Patrick Rachford <pat at modular.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/MC/WasmObjectWriter.cpp
M llvm/test/MC/WebAssembly/reloc-pic64.s
Log Message:
-----------
[WebAssembly] Emit i64 GOT import globals on wasm64 (#226326)
WasmObjectWriter hardcodes the synthetic GOT import globals
(GOT.mem/GOT.func) to i32, but on wasm64 they hold 64-bit addresses, so
the object is type-invalid against the i64 global.get that consumes
them. wasm-ld already emits i64 GOT imports on wasm64, so this aligns
the object writer with the linker: the import type is gated on
is64Bit(), and the reloc-pic64 expectations are updated. The wasm32
checks are unchanged.
Commit: 229e7000493f118d49d23073d3bfa613b3798d85
https://github.com/llvm/llvm-project/commit/229e7000493f118d49d23073d3bfa613b3798d85
Author: Marcos Ramirez Joos <mramirezjoos.oss at proton.me>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M libc/src/__support/FPUtil/FEnvImpl.h
Log Message:
-----------
[libc] Avoid system fenv.h in FEnvImpl.h when LIBC_MATH_HAS_NO_EXCEPT is set (#224384)
The warning being added under #199009 triggers errors in subprojects
(e.g., flang) using libc headers that gate the use of `#pragma STDC
FENV_ACCESS ON` on the internal libc
`LIBC_COMPILER_HAS_STDC_FENV_ACCESS` flag, when building under
`-Wfenv-access -Werror`. As the idea is for these subprojects to not
access the libc FP environment (see
https://github.com/llvm/llvm-project/pull/199009#issuecomment-5299119396),
gating the use of system fenv.h functions on the
`LIBC_MATH_HAS_NO_EXCEPT` flag avoids having to specify the
`LIBC_COMPILER_HAS_STDC_FENV_ACCESS` flag when building them.
The three line removals are a clean-up related to
https://github.com/llvm/llvm-project/pull/200268. These uses are
redundant as the called functions already use the pragma when
appropriate.
Commit: 7ca0ce59bb82557a3052666562cc8f0d6d03ec41
https://github.com/llvm/llvm-project/commit/7ca0ce59bb82557a3052666562cc8f0d6d03ec41
Author: Finn Plummer <mail at inbelic.dev>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/Target/DirectX/DXILOpBuilder.cpp
M llvm/test/CodeGen/DirectX/LoadInput.ll
M llvm/test/CodeGen/DirectX/StoreOutput.ll
Log Message:
-----------
[DirectX] Preserve all shader-stage bits during DXIL op lowering (#225874)
The vertex-stage bit is above bit 15 and was lost when the mask was
narrowed to uint16_t. This would cause an incorrect lowering error:
https://godbolt.org/z/rEMj8ssK9.
Corrected by keeping it as a 32 bit value.
Assisted by: ChatGPT 6 Astra
Commit: 44c84768990686eb1e24b4d1dcbd13fff37442bb
https://github.com/llvm/llvm-project/commit/44c84768990686eb1e24b4d1dcbd13fff37442bb
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVExpandPseudoPostRA.cpp
M llvm/lib/Target/RISCV/RISCVExpandPseudoPreEmit.cpp
M llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
M llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
M llvm/lib/Target/RISCV/RISCVLoadStoreOptimizer.cpp
M llvm/lib/Target/RISCV/RISCVZilsdOptimizer.cpp
Log Message:
-----------
[RISCV] Replace uses of RegState::Define. NFC (#226569)
Either pass the destination register to the BuildMI call or use addDef
if there are multiple defs or other flags are set.
Commit: 19d72fd6deab2ea3addd8b945807abd02b1bbb70
https://github.com/llvm/llvm-project/commit/19d72fd6deab2ea3addd8b945807abd02b1bbb70
Author: Kerry McLaughlin <kerry.mclaughlin at arm.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M clang/lib/CodeGen/TargetBuiltins/ARM.cpp
M clang/lib/Sema/SemaARM.cpp
M llvm/include/llvm/Support/AArch64MemoryHints.h
M llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
Log Message:
-----------
[AArch64] Rename memory hints to avoid clash with arm_acle.h macros (#226432)
Renames the hints in AArch64MemoryHints.h, as HINT_STSHH_KEEP and
HINT_STSHH_STRM are already defined in arm_acle.h.
Commit: e76dd51398a8ceac33e9e5bf3253dd6b03b965dd
https://github.com/llvm/llvm-project/commit/e76dd51398a8ceac33e9e5bf3253dd6b03b965dd
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
A llvm/test/Transforms/SLPVectorizer/RISCV/trimmed-node-matching-gather.ll
Log Message:
-----------
[SLP][NFC]ADd a test with the missed vectorization, NFC
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/226581
Commit: d506ee743cdaef27448964890f813bd3b7da7953
https://github.com/llvm/llvm-project/commit/d506ee743cdaef27448964890f813bd3b7da7953
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/RISCV/trimmed-node-matching-gather.ll
Log Message:
-----------
[SLP]Reuse the trimmed nodes in the perfectly matched gathers of the same user
The gather node, perfectly matching the node of the same user
transformed to gather during throttling, did not treat this node as a
reuse source, and was costed and emitted as a separate buildvector.
Fixes #219030
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/226582
Commit: f57595ff59a0f012e0481c69613be907942c30b1
https://github.com/llvm/llvm-project/commit/f57595ff59a0f012e0481c69613be907942c30b1
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanVerifier.cpp
M llvm/unittests/Transforms/Vectorize/VPlanVerifierTest.cpp
Log Message:
-----------
[VPlan] Only exempt MaskedCond from cross-block dominance in verifier. (#226512)
Previously the verifier skipped all use-before-def checks for
MaskedCond, including uses in the same block before the definition.
Restrict the exemption to users in blocks not dominated by the
MaskedCond's block, so same-block use-before-def is still diagnosed.
Commit: 08af99fae9e079b448cd8877fc57376efe680cda
https://github.com/llvm/llvm-project/commit/08af99fae9e079b448cd8877fc57376efe680cda
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/include/llvm/CodeGen/SDPatternMatch.h
Log Message:
-----------
[SDPatternMatch] Implement m_True/False using SelectionDAG::isBoolConstant. (#226216)
Better than duplicating existing functionality.
Commit: e4af48bd3b330282f36f075d6fa7a4a0742376c1
https://github.com/llvm/llvm-project/commit/e4af48bd3b330282f36f075d6fa7a4a0742376c1
Author: Ehsan Amiri <ehsan.amiri at huawei.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Scalar/LoopFuse.cpp
A llvm/test/Transforms/LoopFusion/guard_skip_empty_block.ll
Log Message:
-----------
[LoopFusion] Cleanup control flow before Fusion (#226289)
Non-loop successor of loop guard is sometimes modified by JumpThreading
(and potentially some other passes) to jump to a new block, that doesn't
post dominate the exit block of the loop:
Guard: br %c, %Preheader, %Skip
Skip: br %Merge
...
Exit: br %Merge
Merge: ...
Later on, this block becomes empty, so it can be removed. Its presence
prevents Loop::getLoopGuardBranch() from detecting the loop guard which
results in missed fusion opportunities. SimplifyCFG will run when "Skip"
is still not optimzied, so it cannot resolve this issue.
Assisted by Claude Code
Commit: ee3b6b045bc37b156c3860481090d68367e961dc
https://github.com/llvm/llvm-project/commit/ee3b6b045bc37b156c3860481090d68367e961dc
Author: agozillon <Andrew.Gozillon at amd.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M flang/lib/Lower/OpenMP/ClauseProcessor.cpp
M flang/lib/Lower/OpenMP/Utils.cpp
M flang/lib/Lower/OpenMP/Utils.h
M flang/test/Lower/OpenMP/declare-mapper.f90
A flang/test/Lower/OpenMP/target-map-nested-dtype-allocatable-member.f90
Log Message:
-----------
[Flang][OpenMP] Fix broken offload test caused by MapInfoFinalization code movement (#226384)
This change addresses the breakage in
target-map-nested-dtype-allocatable-member.f90 I inadvertently broke it
by removing the excess bit of implicit mapping code in the
MapInfoFinalizaiton pass without correctly addressing it.
This PR tries to do so by allowing mappers to be generated for member
maps such as var1%b, var2%b, which were previously being blocked.
Currently (and conveniently for this patch) we do avoid duplicate maps
in the scenario where we specify something along the lines of:
map(tofrom: var1, var1%b, var2, var2%b)
But that is through the fact that we completely negate var1/var2's
mapper attachment in this scenario, which I do not believe is the
correct behavior. But it's the existing behavior and facilitates this
patch, but it is something I'll see if I can address in a follow up PR
in the near future, the logic might need a bit of debating. For now this
simply seeks to amend the existing test without rocking the boat more
than required (that's the hope at least).
Commit: ae614a9564425ab206940f2b91607b1d77826068
https://github.com/llvm/llvm-project/commit/ae614a9564425ab206940f2b91607b1d77826068
Author: Aaron <58265908+aaronsms at users.noreply.github.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M clang/lib/Format/ContinuationIndenter.cpp
M clang/unittests/Format/FormatTest.cpp
Log Message:
-----------
[clang-format] Preserve enum initializer continuation indentation (#223435)
Fixes #223011
Enum assignment operators are annotated as TT_EnumEqual so they can be
aligned independently in #194154. However, this means
ContinuationIndenter no longer recognizes a wrapped enum `=` as
TT_BinaryOperator. As a result, it may force unnecessary breaks within
the RHS binary expression.
Co-authored-by: Aaron Saw Min Sern <aaron at aaronsms.com>
Commit: 4db3dceb8d7bffa4b69042fe043652d616396237
https://github.com/llvm/llvm-project/commit/4db3dceb8d7bffa4b69042fe043652d616396237
Author: Jeremy Kun <jkun at google.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/Support/StringRef.cpp
M llvm/unittests/ADT/StringRefTest.cpp
Log Message:
-----------
[llvm] produce a more consistent estimates of bit width needed when parsing an integer (#205947)
A colleague of mine noticed that `"12535824225335233"` parses in MLIR's
integer attribute parser as a 68-bit integer, even though it is a 53-bit
constant. I traced this back to `StringRef::consumeInteger`'s heuristic
estimate of the bit size. This change replaces that heuristic with a
default 64-bit storage, doubling the storage as more digits are parsed.
This produces a potentially larger over-estimate of the total storage
required, but does so in a less arbitrary manner and reduces the
over-approximation for numbers close to the 64-bit boundary.
Nb., A first iteration of this change tightened that estimate to at most
a 1-bit overapproximation with a lookup-table.
Assisted by Gemini
Commit: 1b4e7f41268eb3db5300e79256764140e509e3f5
https://github.com/llvm/llvm-project/commit/1b4e7f41268eb3db5300e79256764140e509e3f5
Author: Akash Manna <akash.manna.mymail at gmail.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M clang/docs/ReleaseNotes.md
M clang/lib/Sema/SemaType.cpp
M clang/test/Sema/large-bit-int.c
M clang/test/Sema/types.c
M clang/test/SemaCXX/vector.cpp
Log Message:
-----------
[Clang] Enforce the same size limits for `vector_size` and `ext_vector_type` (#226375)
Fixes #165458
A `bool` vector declared with `ext_vector_type` isn't lowered as an LLVM
vector in memory: `ConvertTypeForMem` packs it into a single integer
with one bit per element. `BuildExtVectorType` only checked that the
element count fits in 32 bits, though, so a vector of 187,553,262 bools
got through Sema and the first consumer that needed its memory type (the
zero initializer of a tentative definition here) asked
`IntegerType::get` for far more than the 2^23 bits it supports. The
count matters for every element type, not just `bool`, because Sema also
forms bool vectors out of other vectors (`c ? true : false` with a
`char` vector condition), and `vector_size` was no better off with its
limits of 2^32 elements and 2^61 bytes.
Both attributes now go through the same two limits when the type is
built, reusing the existing "vector size too large" error: at most
`llvm::IntegerType::MAX_INT_BITS` (2^23) elements, and at most 2^28
bytes so that the natural alignment, the size rounded up to a power of
two, still fits in the `unsigned` alignment of `TypeInfo`. These replace
the old `isIntN(61)` and `UINT32_MAX` checks in `BuildVectorType`.
Commit: 210ecf77c9021941ee32c496df8b715615163df4
https://github.com/llvm/llvm-project/commit/210ecf77c9021941ee32c496df8b715615163df4
Author: Eli Friedman <efriedma at qti.qualcomm.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/Transforms/IPO/Instrumentor.cpp
Log Message:
-----------
[Instrumentor] Use CreateAllocationSize to compute size of alloca (#226330)
No significant functional change, but the IR might look slightly
different.
Commit: 14e819f14307fd85fe830cf9fe8d168a27b3db89
https://github.com/llvm/llvm-project/commit/14e819f14307fd85fe830cf9fe8d168a27b3db89
Author: Eli Friedman <efriedma at qti.qualcomm.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/include/llvm/Transforms/IPO/InstrumentorUtils.h
Log Message:
-----------
[Instrumentor] Delete dead code from getAlloca() (#226331)
Commit: 8af5ec67c2001eb379d53cc61ccce0ca521a6c3c
https://github.com/llvm/llvm-project/commit/8af5ec67c2001eb379d53cc61ccce0ca521a6c3c
Author: Abhay Kanhere <a_kanhere at apple.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/include/llvm/IR/AutoUpgrade.h
M llvm/lib/Bitcode/Reader/MetadataLoader.cpp
M llvm/lib/IR/AutoUpgrade.cpp
A llvm/test/Bitcode/upgrade-tbaa-struct.ll
A llvm/test/Bitcode/upgrade-tbaa-struct.ll.bc
Log Message:
-----------
[AutoUpgrade] Upgrade old-style !tbaa.struct field tags (#225967)
Extend the TBAA auto-upgrade to rewrite old-style scalar field tags
inside !tbaa.struct
to the struct-path aware format. bitcode (MetadataLoader) upgraded to
match the existing top-level !tbaa upgrade.
Commit: 35df00b0aa5d9f4deec215306dc24d247f5eb66c
https://github.com/llvm/llvm-project/commit/35df00b0aa5d9f4deec215306dc24d247f5eb66c
Author: Abhay Kanhere <a_kanhere at apple.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/Analysis/TypeBasedAliasAnalysis.cpp
M llvm/test/Transforms/InstCombine/struct-assign-tbaa.ll
Log Message:
-----------
[TBAA] Recover !tbaa for a memcpy of struct with same type fields (#214116)
When InstCombine widens a small same-typed aggregate copy into an
integer load/store, it derives no !tbaa, and !tbaa.struct is nulled out,
so the load/store are left untyped. An untyped access may-alias every
typed access and blocks optimization:
struct Coord { int x, y; };
void copy_if_inbounds(Coord *dst, const Coord *src, const long *bound,
int n) {
for (int i = 0; i < n; ++i)
if (i < *bound)
dst[i] = *src; // {int,int} copy -> memcpy + !tbaa.struct
}
compare this to field-by-field copy, which has typed field access
void copy_fields_if_inbounds(Coord *dst, const Coord *src, const long
*bound, int n) {
for (int i = 0; i < n; ++i)
if (i < *bound) { dst[i].x = src->x; dst[i].y = src->y; } // per-field,
typed
}
Commit: 1173687801b5ab1e996f1aef21b760318e5da8c9
https://github.com/llvm/llvm-project/commit/1173687801b5ab1e996f1aef21b760318e5da8c9
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlan.cpp
M llvm/lib/Transforms/Vectorize/VPlanHelpers.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
Log Message:
-----------
[VPlan] Use NeedsSingleScalar consistently for ::get (NFC). (#226494)
IsScalar/IsSingleScalar as used currently may be consfusing, as it could
be read as implying that the VPValue is a single-scalar, see
https://github.com/llvm/llvm-project/pull/226153.
But here it means that the caller only needs a single scalar. Update
wording.
PR: https://github.com/llvm/llvm-project/pull/226494
Commit: b4842bea58e6ca2a3de8692d5214b2441285513d
https://github.com/llvm/llvm-project/commit/b4842bea58e6ca2a3de8692d5214b2441285513d
Author: Alex MacLean <amaclean at nvidia.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-undef.mir
M llvm/test/CodeGen/AMDGPU/call-constant.ll
M llvm/test/CodeGen/AMDGPU/invalid-addrspacecast.ll
M llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-pal.ll
Log Message:
-----------
[GlobalISel] Preserve volatile and ordered atomic stores of undef (#226265)
Guard `erase_undef_store` with `isUnordered()`, matching InstCombine.
Ensures volatile and ordered atomic stores are preserved.
---------
Co-authored-by: Hongyu Chen <hongchen at nvidia.com>
Commit: f9f5ed22a7026261aec0075caa9862953a8a5fe6
https://github.com/llvm/llvm-project/commit/f9f5ed22a7026261aec0075caa9862953a8a5fe6
Author: Joseph Huber <huberjn at outlook.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/runtimes/CMakeLists.txt
Log Message:
-----------
[LLVM] Use complete runtime dependency list for multilibs (#226580)
Summary:
The current handling makes the multilib job depend on the base runtimes
job. This means that we will potentially depend on things that don't
necessarily need to be built to fulfil the multilibs job. Instead, just
depend on the individual targets for that multilib.
Commit: 91d0e2e91e2dc4c4729cbe911f67388453ee509d
https://github.com/llvm/llvm-project/commit/91d0e2e91e2dc4c4729cbe911f67388453ee509d
Author: Jason Van Beusekom <jason.van-beusekom at hpe.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M offload/include/Shared/SourceInfo.h
M offload/test/offloading/info.c
M openmp/docs/ReleaseNotes.md
Log Message:
-----------
[Offload][OpenMP] remove SourceInfo::removePath (#226586)
This Pr is the same as https://github.com/llvm/llvm-project/pull/226283
(which was reverted in https://github.com/llvm/llvm-project/pull/226557)
This Pr is the same as https://github.com/llvm/llvm-project/pull/226283
but with an update to info.c to account for the new full path output.
Commit: 5f3a611fa194ca76c91d3889adb68532cef44cee
https://github.com/llvm/llvm-project/commit/5f3a611fa194ca76c91d3889adb68532cef44cee
Author: Jackson Stogel <jtstogel at gmail.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M utils/bazel/MODULE.bazel.lock
M utils/bazel/linux_uapi.bzl
Log Message:
-----------
[bazel] Download linux UAPI headers when no local dir is set (#216868)
This PR defines a hermetic source for `@linux_api//:linux_uapi_headers`
that will be used in CI. If no `LINUX_UAPI_INCLUDE_DIR` value is
specified, then Bazel will download the linux-libc-dev debian package
and use its headers.
I originally wanted to pull from https://github.com/torvalds/linux and
build UAPI headers from source as it gives more control, but the repo is
rather large and took ~20s to download and ~10s to build. Using the
debian package's headers is closer to what the LLVM-libc fullbuild CI
[currently
does](https://github.com/llvm/llvm-project/blob/007551bacb899a409218574908d96b0633d52018/.github/workflows/containers/libc/Dockerfile#L38)
and is very fast.
Commit: c4195f63a560990bdb854357d66f759259bf1d3e
https://github.com/llvm/llvm-project/commit/c4195f63a560990bdb854357d66f759259bf1d3e
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M mlir/docs/Interfaces.md
M mlir/include/mlir/Dialect/OpenMP/OpenMPOpsInterfaces.td
M mlir/test/mlir-tblgen/op-interface.td
M mlir/tools/mlir-tblgen/OpInterfacesGen.cpp
Log Message:
-----------
[mlir][ODS] Share operation interface methods with raw-op bodies (NFC) (#226317)
Allow an operation interface method to use a shared callback when its
body only needs the raw Operation. Use it for OpenMP block-argument
indexing and slicing methods, avoiding per-operation wrappers while
preserving the existing fallback and external model paths.
Reduces the size of the OpenMP dialect text section by 1.68%.
Assisted-by: Codex
Commit: 7fbfd203131aa597c63d89e45392454280f89cfa
https://github.com/llvm/llvm-project/commit/7fbfd203131aa597c63d89e45392454280f89cfa
Author: Med Ismail Bennani <ismail at bennani.ma>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M lldb/include/lldb/Utility/StructuredData.h
M lldb/source/Commands/CommandObjectVersion.cpp
M lldb/source/Utility/StructuredData.cpp
Log Message:
-----------
[lldb] Add StructuredData::Dictionary::ForEachSorted (NFC) (#226597)
`Dictionary::Serialize`, `Dictionary::GetDescription` and the build
configuration dump in `CommandObjectVersion` each collect the
dictionary's keys and sort them before iterating, so that the output
doesn't depend on StringMap's ordering. Factor that into a new
`ForEachSorted` method.
Signed-off-by: Med Ismail Bennani <ismail at bennani.ma>
Commit: 5cab2963e13496c272a482145b11796e9e26eeb4
https://github.com/llvm/llvm-project/commit/5cab2963e13496c272a482145b11796e9e26eeb4
Author: Demetrios Chiuratto Agourakis <demetrios at agourakis.med.br>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
M llvm/test/CodeGen/X86/llvm.frexp.ll
Log Message:
-----------
[SelectionDAG] Fix result index and vector width in unrollExpandedOp (#225886)
Fixes #224127.
In `DAGTypeLegalizer::WidenVectorResult`, `unrollExpandedOp` computes
the unroll count and widened vector type from the result being legalized
(`ResNo`) rather than unconditionally using result 0. For multi-result
nodes where result types differ (e.g. `ISD::FFREXP`), this prevents
mismatched vector widths and preserves the correct result index from
`DAG.UnrollVectorOp`.
Assisted-by: Claude
---------
Co-authored-by: Demetrios Chiuratto Agourakis <agourakis82 at gmail.com>
Commit: 5aa8fcc29bc47056411b3d23b0e7acc981ec3934
https://github.com/llvm/llvm-project/commit/5aa8fcc29bc47056411b3d23b0e7acc981ec3934
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/rvv/trunc-select-to-max-usat.ll
Log Message:
-----------
[RISCV] Support swapped select operands in combineTruncSelectToSMaxUSat. (#226584)
Handle (trunc (vselect (setugt X, 2^N-1), (sext (setgt X, 0)), X)) in
addition to the existing (trunc (vselect (setult X, 2^N), X,
(sext (setgt X, 0)))) form.
Co-Authored-By: Claude Opus 5.5 (1M context) <noreply at anthropic.com>
Commit: 7e91ef5d6aeaa7191a9354ddcff67d84bd8aebaf
https://github.com/llvm/llvm-project/commit/7e91ef5d6aeaa7191a9354ddcff67d84bd8aebaf
Author: Michael G. Kazakov <mike.kazakov at gmail.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M libcxx/include/CMakeLists.txt
M libcxx/include/__algorithm/pstl.h
M libcxx/include/__pstl/backend_fwd.h
M libcxx/include/__pstl/backends/default.h
M libcxx/include/__pstl/backends/libdispatch.h
M libcxx/include/__pstl/backends/serial.h
M libcxx/include/__pstl/backends/std_thread.h
A libcxx/include/__pstl/cpu_algos/swap_ranges.h
M libcxx/include/module.modulemap.in
M libcxx/test/libcxx/algorithms/pstl.iterator-requirements.verify.cpp
A libcxx/test/std/algorithms/alg.modifying.operations/alg.swap/pstl.swap_ranges.pass.cpp
M libcxx/test/std/algorithms/pstl.exception_handling.pass.cpp
Log Message:
-----------
[libc++][pstl] Implementation of parallel std::swap_ranges() based on parallel __for_each (#224967)
This PR adds an implementation of parallel `std::swap_ranges()` based on
`__parallel_for_each_iter_pair()`.
The implementation is effectively a one-liner, but has to deal with
iterator ranges, thus is located in `cpu_algos`:
```c++
__pstl::__parallel_for_each_iter_pair<_Backend>(
first1, last1, first2,
[](ForwardIterator1 brick_first1, ForwardIterator1 brick_last1, ForwardIterator2 brick_first2) {
std::swap_ranges(std::move(brick_first1), std::move(brick_last1), std::move(brick_first2));
});
```
Part of #99938
Commit: 7fc4f276a4d0a4b1f968003d863ee50dc9ebcedd
https://github.com/llvm/llvm-project/commit/7fc4f276a4d0a4b1f968003d863ee50dc9ebcedd
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M flang/lib/Parser/openacc-parsers.cpp
M flang/test/Parser/acc-label-do.f90
Log Message:
-----------
[flang][openacc] Build full shared-label DO nests in AccNonBlockDoConstruct (#225997)
When an `!$acc loop` is associated with a labeled DO,
AccNonBlockDoConstruct
turned only that outer loop into a DoConstruct and left sibling
LabelDoStmts
that share the same terminator for later CanonicalizeDo. An inner `!$acc
loop`
then swallowed the shared terminator into its own DoConstruct, so
AnalyzeLabels (which runs before CanonicalizeDo) rejected the remaining
LabelDoStmts with "Label 'N' is not in DO loop scope".
Recurse on nested LabelDoStmts while parsing the associated loop so the
whole shared-label nest is a DoConstruct before label analysis. Add a
parser test where only the outer and innermost loops have LOOP
directives.
Commit: ce8e98386b89cf25065349c0e8147f839afda5dd
https://github.com/llvm/llvm-project/commit/ce8e98386b89cf25065349c0e8147f839afda5dd
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M mlir/include/mlir/Dialect/Linalg/IR/LinalgInterfaces.td
M mlir/include/mlir/Dialect/OpenACC/OpenACCOpsInterfaces.td
M mlir/include/mlir/Dialect/OpenMP/OpenMPOpsInterfaces.td
M mlir/include/mlir/Dialect/SparseTensor/IR/SparseTensorInterfaces.td
M mlir/include/mlir/Dialect/WasmSSA/IR/WasmSSAInterfaces.td
M mlir/include/mlir/Interfaces/ControlFlowInterfaces.td
Log Message:
-----------
[mlir][Interfaces] Share more operation interface bodies (NFC) (#226603)
Use raw operation access for methods that do not depend on the concrete
operation type. Keep typed access where operation-specific APIs are
needed.
This save a little bit of code size and improves build time.
Assisted-by: Codex
Commit: b5426c132f47b14874de7ce26a4e1bca80182e4c
https://github.com/llvm/llvm-project/commit/b5426c132f47b14874de7ce26a4e1bca80182e4c
Author: Lang Hames <lhames at gmail.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M orc-rt/include/orc-rt-c/support/Logging.h
M orc-rt/test/unit/support/LoggingTest.cpp
Log Message:
-----------
[orc-rt] Add ORC_RT_LOG_ENABLED macro. (#226500)
ORC_RT_LOG_ENABLED(Level) reports whether log sites at the given level
are compiled in, taking into account both the backend and the
ORC_RT_LOG_LEVEL floor. It takes the same level token as ORC_RT_LOG and
can be used in preprocessor conditionals, allowing code that relies on
logging to surface something important (e.g. a logging error reporter)
to choose an alternative when logging is compiled out.
Commit: f739fbc831cbd670b9dc3044a492240cfede20c3
https://github.com/llvm/llvm-project/commit/f739fbc831cbd670b9dc3044a492240cfede20c3
Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
A llvm/test/Transforms/LoopVectorize/AArch64/diff-checks-force-interleave-count.ll
Log Message:
-----------
[LV] Honor -force-vector-interleave when generating diff checks (#225768)
We use both IC and UserIC in the checks below. However, once those
checks are done, UserIC will always override IC if it's non-zero. That
means using the max is unnecessary and can result in overly conservative
checks when UserIC < IC.
Commit: 201e76d4559e9d8acdfec1c202df8f2269acbd8b
https://github.com/llvm/llvm-project/commit/201e76d4559e9d8acdfec1c202df8f2269acbd8b
Author: Changpeng Fang <changpeng.fang at amd.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/CodeGen/DetectDeadLanes.cpp
A llvm/test/CodeGen/AMDGPU/detect-dead-lanes-reg-sequence-narrow-slot.mir
M llvm/test/CodeGen/AMDGPU/frem.ll
A llvm/test/CodeGen/AMDGPU/true16-uniform-f16-phi-copysign.ll
Log Message:
-----------
[CodeGen] Fix DetectDeadLanes for same-class copies with mismatched widths (#226556)
isCrossCopy() returned early whenever source and destination shared a
register class, treating the transfer as lane-for-lane. That is wrong
when a REG_SEQUENCE names a subregister slot narrower than the source
operand, e.g. a 32-bit vreg used as the lo16 piece of another 32-bit
vreg. Only take the early exit when the two widths match; otherwise fall
through to findCommonRegClass().
Fixes: ROCM-31212
Commit: 3a2787d5ca6ba0271f7203997f8a9b65679398a4
https://github.com/llvm/llvm-project/commit/3a2787d5ca6ba0271f7203997f8a9b65679398a4
Author: Lang Hames <lhames at gmail.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M orc-rt/include/orc-rt-c/config.h.in
M orc-rt/include/orc-rt-c/support/Logging.h
Log Message:
-----------
[orc-rt] Move ORC_RT_LOG_ENABLED into config.h. (#226617)
ORC_RT_LOG_ENABLED depends only on the logging configuration values
defined in config.h, but was defined in Logging.h, so checking whether a
log level is compiled in required pulling in the logging backend's
headers (e.g. <os/log.h>).
This commit moves ORC_RT_LOG_ENABLED (and its level-token aliases) into
config.h, so that headers can check the logging configuration without
including Logging.h.
Commit: f8c2918d49d3a3803ae3c9e1b6c216b24db9ad51
https://github.com/llvm/llvm-project/commit/f8c2918d49d3a3803ae3c9e1b6c216b24db9ad51
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
A llvm/test/Transforms/SLPVectorizer/AArch64/ordered-reduction-of-loads.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/ordered-reduction.ll
Log Message:
-----------
[SLP][NFC]Add extra test for reductions vectorization, NFC
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/226618
Commit: 90c150f868adb53b45dbf7489e93a23c22f6b6b3
https://github.com/llvm/llvm-project/commit/90c150f868adb53b45dbf7489e93a23c22f6b6b3
Author: Fangrui Song <i at maskray.me>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M clang/tools/clang-format/ClangFormat.cpp
M llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
M llvm/lib/Target/AArch64/AArch64CodeLayoutOpt.cpp
Log Message:
-----------
Replace cl::bits with cl::list. NFC (#226399)
cl::bits packs enum values into an unsigned, which would block migration
to TableGen based representation. The three users only test membership.
LLM-aided
Commit: 0b61b734cf84a19491f4bcb61e04956995807051
https://github.com/llvm/llvm-project/commit/0b61b734cf84a19491f4bcb61e04956995807051
Author: Fangrui Song <i at maskray.me>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M clang-tools-extra/clangd/tool/ClangdMain.cpp
Log Message:
-----------
[clangd] Report retired flags after parsing (#226360)
cl::callback will be removed to enable migration to TableGen
https://discourse.llvm.org/t/rfc-declare-library-command-line-options-in-tablegen-one-struct-per-library/91877/3
LLM-aided
Commit: ab08c75ffe0a40626a4dc62ed010d6e3ceece056
https://github.com/llvm/llvm-project/commit/ab08c75ffe0a40626a4dc62ed010d6e3ceece056
Author: Fangrui Song <i at maskray.me>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M bolt/lib/Passes/BinaryPasses.cpp
M bolt/lib/Passes/ReorderFunctions.cpp
M bolt/lib/Profile/DataAggregator.cpp
Log Message:
-----------
[BOLT] Remove cl::callback uses (#226359)
cl::callback will be removed to enable migration to TableGen based
representation.
https://discourse.llvm.org/t/rfc-declare-library-command-line-options-in-tablegen-one-struct-per-library/91877/3
LLM-aided
Commit: e59a0c697552ae7d1c3aeed5774e829cdc5e16b5
https://github.com/llvm/llvm-project/commit/e59a0c697552ae7d1c3aeed5774e829cdc5e16b5
Author: Lang Hames <lhames at gmail.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M orc-rt/include/orc-rt/bedrock/Session.h
M orc-rt/lib/bedrock/Session.cpp
M orc-rt/test/unit/CommonTestUtils.h
M orc-rt/test/unit/bedrock/InProcessControllerAccessTest.cpp
M orc-rt/test/unit/bedrock/SessionTest.cpp
M orc-rt/tools/ogre/ogre.cpp
Log Message:
-----------
[orc-rt] Pass the reporting Session to Session error reporters. (#226622)
Session error reporters previously received only the Error, and had to
be supplied to the Session constructor, so they had no direct way to
refer to the Session reporting the error (e.g. to include its address in
a log message).
This commit changes ErrorReporterFn to take the reporting Session along
with the Error, and adds a Session::logErrors reporter that logs errors
via ORC_RT_LOG at Error level in the Session category. logErrors is only
available when Error-level logging is compiled in
(ORC_RT_LOG_ENABLED(Error)), so that it can't silently discard errors in
configurations where logging is compiled out. The noErrors and
AccumulateErrors test helpers are updated to work as both plain and
Session error reporters.
Commit: 240a9cb75dd9210cae8e987700d0ef6537b723cb
https://github.com/llvm/llvm-project/commit/240a9cb75dd9210cae8e987700d0ef6537b723cb
Author: Twice <twice at apache.org>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M mlir/python/mlir/dialects/ext.py
M mlir/test/python/dialects/ext.py
Log Message:
-----------
[MLIR][Python] Allow `Attribute` to denote unconstrained attributes in Python-defined ops (#224679)
Operation definitions support attribute constraints such as
`IntegerAttr`, `StringAttr`, and `IntegerAttr | StringAttr`, but
currently reject `Attribute` itself.
This change allows `Attribute` to denote an unconstrained attribute,
accepting both built-in and Python-defined attributes:
```python
class MyOp(MyDialect.Operation, name="my_op"):
arg: Operand
attr: Attribute
res: Result
```
This complements the unconstrained `Operand` and `Result` annotations
introduced in #220216. The annotation also works with `attribute()`
field specifiers, including `kw_only` and `default_factory`.
Assisted-by: Codex / GPT6
Commit: 163950475fc724cd5d62e868bdb46ba0c39e5519
https://github.com/llvm/llvm-project/commit/163950475fc724cd5d62e868bdb46ba0c39e5519
Author: Steffen Larsen <sholstla at amd.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M clang/include/clang/CIR/Dialect/Builder/CIRBaseBuilder.h
M clang/lib/CIR/CodeGen/CIRGenDecl.cpp
M clang/test/CIR/CodeGenCUDA/address-spaces.cu
Log Message:
-----------
[CIR] Attach address space to global variables (#226455)
Signed-off-by: Steffen Holst Larsen <sholstla at amd.com>
Commit: 60059de6eb6d647857ac55b48d465580aa3ecdc5
https://github.com/llvm/llvm-project/commit/60059de6eb6d647857ac55b48d465580aa3ecdc5
Author: A. Jiang <de34 at live.cn>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M libcxx/include/__ranges/adjacent_transform_view.h
M libcxx/include/__ranges/adjacent_view.h
M libcxx/include/__ranges/chunk_by_view.h
M libcxx/include/__ranges/common_view.h
M libcxx/include/__ranges/concat_view.h
M libcxx/include/__ranges/counted.h
M libcxx/include/__ranges/drop_view.h
M libcxx/include/__ranges/drop_while_view.h
M libcxx/include/__ranges/elements_view.h
M libcxx/include/__ranges/empty_view.h
M libcxx/include/__ranges/enumerate_view.h
M libcxx/include/__ranges/filter_view.h
M libcxx/include/__ranges/iota_view.h
M libcxx/include/__ranges/join_view.h
M libcxx/include/__ranges/join_with_view.h
M libcxx/include/__ranges/lazy_split_view.h
M libcxx/include/__ranges/movable_box.h
M libcxx/include/__ranges/non_propagating_cache.h
M libcxx/include/__ranges/rbegin.h
M libcxx/include/__ranges/rend.h
M libcxx/include/__ranges/reverse_view.h
M libcxx/include/__ranges/single_view.h
M libcxx/include/__ranges/split_view.h
M libcxx/include/__ranges/stride_view.h
M libcxx/include/__ranges/take_view.h
M libcxx/include/__ranges/take_while_view.h
M libcxx/include/__ranges/to.h
M libcxx/include/__ranges/transform_view.h
M libcxx/include/__ranges/views.h
M libcxx/include/__ranges/zip_transform_view.h
M libcxx/include/__ranges/zip_view.h
Log Message:
-----------
[libc++][NFC] Avoid empty namespace in internal headers of `<ranges>` (#226034)
...in pre-C++20/23 modes. This follows up
0c94a978df783bd67535350eac84088fc482716a and fixes more complaints from
clang-tidy checks in CI.
Commit: 18af9ef08eec59d1bce7b941f164ba3f866acf59
https://github.com/llvm/llvm-project/commit/18af9ef08eec59d1bce7b941f164ba3f866acf59
Author: Douglas Yung <douglas.yung at sony.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M clang/docs/ReleaseNotes.md
M clang/lib/Sema/SemaOpenMP.cpp
R clang/test/OpenMP/error_message.c
M clang/test/OpenMP/error_message.cpp
M clang/test/OpenMP/parallel_message_messages.cpp
Log Message:
-----------
Revert "[clang][OpenMP] Only accept char strings in the message clause" (#226636)
Reverts llvm/llvm-project#226080
The newly added test error_message.c is failing on the PS4 bot
https://lab.llvm.org/buildbot/#/builders/144/builds/66294
Commit: e0316c1b4762263caa49e3c41ddde752a2b6b775
https://github.com/llvm/llvm-project/commit/e0316c1b4762263caa49e3c41ddde752a2b6b775
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M clang/lib/AST/ByteCode/ByteCodeEmitter.h
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ByteCode/Context.cpp
M clang/lib/AST/ByteCode/Disasm.cpp
M clang/lib/AST/ByteCode/EvalEmitter.cpp
M clang/lib/AST/ByteCode/EvalEmitter.h
M clang/lib/AST/ByteCode/EvaluationResult.cpp
M clang/lib/AST/ByteCode/EvaluationResult.h
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/InterpBuiltinObjectSize.cpp
M clang/lib/AST/ByteCode/Pointer.cpp
M clang/lib/AST/ByteCode/Pointer.h
M clang/lib/AST/ExprConstShared.h
M clang/lib/AST/ExprConstant.cpp
M clang/test/AST/ByteCode/builtin-functions.cpp
M clang/test/AST/ByteCode/codegen-constexpr-unknown.cpp
M clang/test/AST/ByteCode/references.cpp
M clang/test/CodeGenCXX/global-init.cpp
M clang/test/SemaCXX/PR19955.cpp
M clang/test/SemaCXX/cxx2c-expansion-stmts.cpp
Log Message:
-----------
Revert "[clang][bytecode] Stop relying on `CheckEvaluationResult()` (… (#226637)
…#186045)"
This reverts commit 55b498466a7b2620d09fcdf1b2300f71a35f6d8b.
This breaks two msan builders and reproducing the failure locally takes
forever.
Commit: 6a37cee09997b28c6cc708dd36b283bbd5bd7147
https://github.com/llvm/llvm-project/commit/6a37cee09997b28c6cc708dd36b283bbd5bd7147
Author: asudarsa-qti <asudarsa at qti.qualcomm.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M clang/lib/Interpreter/IncrementalAction.cpp
A clang/test/Interpreter/nonexistent-xcc-file.cpp
Log Message:
-----------
Fix for a clang-repl crash when passing non-existent file to --Xcc (#225861)
Problem: When clang-repl fails to initialize because an --Xcc file does
not exist, Interpreter::create() destroys the partially initialized
Interpreter. Its destructor unconditionally calls FinalizeAction(),
which invokes FrontendAction::EndSourceFile() without a registered
CompilerInstance and triggers an assertion.
Fix: Track whether interpreter initialization completed successfully and
only finalize the frontend action for successfully initialized
interpreters.
Test: Add a regression test covering a nonexistent --Xcc file.
This change resolves https://github.com/llvm/llvm-project/issues/225429
Assisted by gpt-5.6-luna
---------
Co-authored-by: Anutosh Bhat <andersonbhat491 at gmail.com>
Commit: c4896792fb97b2ad237c5c404cdda2d0cd4fcf61
https://github.com/llvm/llvm-project/commit/c4896792fb97b2ad237c5c404cdda2d0cd4fcf61
Author: Med Ismail Bennani <ismail at bennani.ma>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M lldb/include/lldb/Target/Process.h
M lldb/source/API/SBProcess.cpp
M lldb/source/Target/Process.cpp
M lldb/test/API/python_api/process/address-masks/TestAddressMasks.py
Log Message:
-----------
[lldb] Rebuild stack frames when a process address mask changes (#224989)
Commit: 4257da8ee2e84b3e62d2a2a5010e81823b799805
https://github.com/llvm/llvm-project/commit/4257da8ee2e84b3e62d2a2a5010e81823b799805
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
A llvm/test/Transforms/LoopVectorize/AArch64/low-trip-count-fixed-vf-no-epilogue.ll
M llvm/test/Transforms/LoopVectorize/RISCV/short-trip-count.ll
Log Message:
-----------
[LV] Always try to use fixed VF for low TC loops if no epilogue allowed. (#226318)
Remove the MaxPowerOf2RuntimeVF gate for falling back to using fixed
width VFs when no epilogue is allowed and the trip count is below the
minimum for tail folding.
MaxPowerOf2RuntimeVF being not set means we cannot compute the maximum
runtime VF, due to missing max vscale. In that case we are not able to
determine if a epilogue loop remains for scalable VFs, but we can still
pick a fixed VF, if no epilogue remains for it.
Also updates processLoop to ignore CM_EpilogueNotNeededFoldTail, if the
trip count is below the tail-folding threshold.
PR: https://github.com/llvm/llvm-project/pull/226318
Commit: 825903711948134578537eda6dd94a488ed50319
https://github.com/llvm/llvm-project/commit/825903711948134578537eda6dd94a488ed50319
Author: Lang Hames <lhames at gmail.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M orc-rt/include/orc-rt/support/bind.h
M orc-rt/test/unit/support/bind-test.cpp
Log Message:
-----------
[orc-rt] make bind_front match std::bind_front semantics. (#226646)
orc_rt::bind_front stands in for std::bind_front until the ORC runtime
can use C++20, so code written against it should keep working after the
switch. This commit brings its behavior in line with std::bind_front:
- noexcept propagation
- const and rvalue call operators, forwarding the wrapper's qualifiers
- no fallback to a differently-qualified call operator
- reference return types
- member pointers
- copyable wrappers, including nested binds
The unit tests are reorganized and extended to cover these.
Assisted-by: Claude
Commit: 0b4f72d00bdd2ef1707c5098d12936bfa159b414
https://github.com/llvm/llvm-project/commit/0b4f72d00bdd2ef1707c5098d12936bfa159b414
Author: Aditya Sinha <155882262+AdityaSinha149 at users.noreply.github.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M clang/include/clang/CodeGen/CodeGenAction.h
M clang/include/clang/Interpreter/Interpreter.h
M clang/lib/CodeGen/BackendConsumer.h
M clang/lib/CodeGen/CodeGenAction.cpp
M clang/lib/Interpreter/DeviceOffload.cpp
M clang/lib/Interpreter/DeviceOffload.h
M clang/lib/Interpreter/Interpreter.cpp
M clang/unittests/Basic/CMakeLists.txt
A clang/unittests/Basic/TargetIDTest.cpp
Log Message:
-----------
[clang-repl] Implement IncrementalHIPDeviceParser for HIP device compilation (#218337)
This PR implements the IncrementalHIPDeviceParser. It takes each
incremental statement's device code and lowers it all the way to a
loadable HIP fat binary: linking the ROCm device libraries, running the
AMDGPU optimization/codegen pipeline, producing a .hsaco code object,
and embedding it as __hip_fatbin for the host runtime to register and
launch.
This PR only adds the parser class, wiring it into Interpreter.cpp and
the end-to-end tests will come in a follow-up.
Assisted by Claude Opus 4.8
Commit: 5f609f950d2e80addf5566623013db68394334db
https://github.com/llvm/llvm-project/commit/5f609f950d2e80addf5566623013db68394334db
Author: Fangrui Song <i at maskray.me>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M llvm/docs/CommandLine.md
M llvm/include/llvm/Support/CommandLine.h
M llvm/unittests/Support/CommandLineTest.cpp
Log Message:
-----------
[Support] Remove cl::bits (#226628)
cl::list covers the same use, and cl::bits would block migration to
TableGen based representation.
LLM-aided
Commit: c0b6ee14c2f8dece229da557352e116f9a6d7064
https://github.com/llvm/llvm-project/commit/c0b6ee14c2f8dece229da557352e116f9a6d7064
Author: David Green <david.green at arm.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
A llvm/test/CodeGen/AArch64/sve-fixed-length-shuffle-reverse.ll
Log Message:
-----------
[AArch64] Add tests for sve fixed length reverse shuffles. NFC (#226661)
Commit: 96b5cc3d836494c56c8d5ae1e73e90864eb19a5d
https://github.com/llvm/llvm-project/commit/96b5cc3d836494c56c8d5ae1e73e90864eb19a5d
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M llvm/include/llvm/Analysis/BranchProbabilityInfo.h
M llvm/lib/Analysis/BranchProbabilityInfo.cpp
Log Message:
-----------
[BPI] Add getEdgeProbabilitiesFromWeights (NFC). (#226560)
Move computing edge probabilities from branch weights to a static
helper. This allows re-using the core logic when computing execution
frequencies in VPlan, fixing a number of subtle differences.
While touching the code, also modernize the code slightly.
Note that the helper does not handle the case where all successors are
unreachable. This would need additional info and is not needed for the
VPlan case.
PR: https://github.com/llvm/llvm-project/pull/226560
Commit: 97e9558844822e1ff8f986319ef354fda42b8215
https://github.com/llvm/llvm-project/commit/97e9558844822e1ff8f986319ef354fda42b8215
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M llvm/lib/CodeGen/DetectDeadLanes.cpp
R llvm/test/CodeGen/AMDGPU/detect-dead-lanes-reg-sequence-narrow-slot.mir
M llvm/test/CodeGen/AMDGPU/frem.ll
R llvm/test/CodeGen/AMDGPU/true16-uniform-f16-phi-copysign.ll
Log Message:
-----------
Revert "[CodeGen] Fix DetectDeadLanes for same-class copies with mismatched widths" (#226665)
Reverts llvm/llvm-project#226556
This is handling malformed IR and adding size based instead of register
class based reasoning
Commit: d94f3a52dad756d7354a9ca688b4ac76a97b9d38
https://github.com/llvm/llvm-project/commit/d94f3a52dad756d7354a9ca688b4ac76a97b9d38
Author: Lang Hames <lhames at gmail.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M orc-rt/test/unit/CMakeLists.txt
R orc-rt/test/unit/bedrock/SocketConnectorTest.cpp
M orc-rt/test/unit/bedrock/SocketTestUtils.h
M orc-rt/test/unit/bedrock/sps/SimpleRemoteCAOverSocketTest.cpp
A orc-rt/test/unit/bedrock/sys/posix/SocketConnectorTest.cpp
M orc-rt/test/unit/bedrock/sys/posix/SocketTestUtils.cpp
Log Message:
-----------
[orc-rt] Make socket unit tests portable; build them on POSIX. (#226662)
SimpleRemoteCAOverSocketTest.cpp tests a POSIX-only implementation, so
move it to the POSIX source list. Its tests are portable, so move the
fixture's POSIX code into SocketTestUtils (makeStreamSocketPair,
sendAll, recvAll, makeNativeNonStreamSocket) rather than moving the file
under sys/posix; a Windows transport will need only Windows definitions
of those helpers.
makeStreamSocketPair documents the properties the tests rely on beyond a
connected stream pair: neither direction buffers StallingPayloadSize
bytes, and closing an end delivers what it already sent even if it has
unread data. AF_UNIX provides both; a loopback TCP pair may not.
SocketConnectorTest.cpp tests fd adoption with pipe and fcntl, so it is
a test of the POSIX implementation: move it to sys/posix/.
Assisted-by: Claude
Commit: a4e311d3f80f0bc1b0912d3f9f650a8d949a06e5
https://github.com/llvm/llvm-project/commit/a4e311d3f80f0bc1b0912d3f9f650a8d949a06e5
Author: Lang Hames <lhames at gmail.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M llvm/lib/ExecutionEngine/Orc/ELFNixPlatform.cpp
M llvm/lib/ExecutionEngine/Orc/MachOPlatform.cpp
Log Message:
-----------
[ORC] Call createPThreadKey through a Proxy in MachO/ELFNixPlatform (#226656)
Replace the callSPSWrapper calls in MachOPlatform::createPThreadKey and
ELFNixPlatform::createPThreadKey with a Proxy built over the address
recorded during bootstrap, using a local CI descriptor for each
platform's create_pthread_key wrapper. The address stays in the
platforms' RuntimeFunction table, which is filled uniformly by the
bootstrap recording pass.
Commit: 0407861c32056a8ac57de2d7ef304ebbb3922139
https://github.com/llvm/llvm-project/commit/0407861c32056a8ac57de2d7ef304ebbb3922139
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M llvm/lib/Target/Mips/MipsAsmPrinter.cpp
M llvm/lib/Target/Mips/MipsAsmPrinter.h
M llvm/lib/Target/Mips/MipsBranchExpansion.cpp
M llvm/lib/Target/Mips/MipsCallLowering.cpp
M llvm/lib/Target/Mips/MipsFastISel.cpp
M llvm/lib/Target/Mips/MipsISelLowering.cpp
M llvm/lib/Target/Mips/MipsMachineFunction.cpp
M llvm/lib/Target/Mips/MipsRegisterInfo.cpp
M llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
M llvm/lib/Target/Mips/MipsSERegisterInfo.cpp
Log Message:
-----------
Mips: Route ABI queries through the subtarget (#226667)
Commit: e7019f85692bab245c02f4fa433b37105f2d9c0d
https://github.com/llvm/llvm-project/commit/e7019f85692bab245c02f4fa433b37105f2d9c0d
Author: Ivan Ho <ivan.ho at cl.cam.ac.uk>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M mlir/lib/Dialect/IRDL/IR/IRDL.cpp
M mlir/lib/Target/IRDLToCpp/IRDLToCpp.cpp
M mlir/test/lib/Dialect/TestIRDLToCpp/test_irdl_to_cpp.irdl.mlir
Log Message:
-----------
[MLIR][IRDL] Instantiate "." in IRDL-defined names as nested namespaces (#207035)
In PR #187911, it was revealed that the constraints on IRDL op names
placed by irdl-to-cpp were too restrictive.
This PR will address that by allowing "." in operation names to denote
nested namespaces, but not "$".
To discuss:
- ops like `wmma.f16.16x16x64.bf8_bf` cannot be registered as C++
identifiers cannot begin with a number. In discussions, we have opted to
prefix the generated namespaces with _.
Codex was used to generate the lit tests.
Close #187911.
Assisted-by: OpenAI Codex (GPT-5 and 6)
Commit: e8e4a54cfbbc054ec9801dea03e6c6868bf0708a
https://github.com/llvm/llvm-project/commit/e8e4a54cfbbc054ec9801dea03e6c6868bf0708a
Author: David Green <david.green at arm.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/test/CodeGen/AArch64/sve-fixed-length-shuffle-reverse.ll
Log Message:
-----------
[AArch64] Use SVE rev for full reverse shuffles with SVE128 (#224589)
When the vscale_range is always 1, we can make use of the SVE rev
instruction to perform a full 128bit vector reverse.
Sidesteps #223597 for SVE128
Commit: fccc8632f21fa8a13f7962932b614e8c1079d9ac
https://github.com/llvm/llvm-project/commit/fccc8632f21fa8a13f7962932b614e8c1079d9ac
Author: Lang Hames <lhames at gmail.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M orc-rt/include/orc-rt/bedrock/sps/SimpleRemoteCAOverSocket.h
M orc-rt/lib/bedrock/sys/posix/sps/SimpleRemoteCAOverSocket.cpp
M orc-rt/test/unit/bedrock/sps/SimpleRemoteCAOverSocketTest.cpp
Log Message:
-----------
[orc-rt] SimpleRemoteCAOverSocket: require a stream socket. (#226676)
SimpleRemote framing reads each message in as many parts as the socket
delivers it, which a socket that preserves message boundaries (datagram,
seqpacket) would truncate. Check SO_TYPE up front and reject anything
but SOCK_STREAM; the socket is owned by then, so it is closed on
failure.
Assisted-by: Claude
Commit: e9e27436e89127e5e42863cc6804945b3619b015
https://github.com/llvm/llvm-project/commit/e9e27436e89127e5e42863cc6804945b3619b015
Author: Ben Shi <2283975856 at qq.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M llvm/lib/Target/AVR/AVRAsmPrinter.cpp
M llvm/lib/Target/AVR/AVRDevices.td
M llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp
M llvm/lib/Target/AVR/AVRISelLowering.cpp
M llvm/lib/Target/AVR/AVRInstrInfo.cpp
M llvm/lib/Target/AVR/AVRInstrInfo.td
M llvm/lib/Target/AVR/AVRRegisterInfo.cpp
M llvm/lib/Target/AVR/MCTargetDesc/AVRMCAsmInfo.cpp
M llvm/lib/Target/AVR/MCTargetDesc/AVRMCTargetDesc.h
R llvm/lib/Target/AVR/TODO.md
Log Message:
-----------
[AVR][NFC] Improve some comment messages (#226423)
Commit: c495a9b796c46456e523a5eeb3690415ba99f5db
https://github.com/llvm/llvm-project/commit/c495a9b796c46456e523a5eeb3690415ba99f5db
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M clang/include/clang/CIR/Dialect/IR/CIRDialect.td
M flang/include/flang/Optimizer/Dialect/CUF/CUFDialect.td
M flang/include/flang/Optimizer/Dialect/FIRCG/CGOps.td
M flang/include/flang/Optimizer/Dialect/FIRDialect.td
M flang/include/flang/Optimizer/Dialect/MIF/MIFDialect.td
M flang/include/flang/Optimizer/HLFIR/HLFIROpBase.td
M mlir/docs/DefiningDialects/Operations.md
M mlir/docs/DefiningDialects/_index.md
M mlir/docs/ReleaseNotes.md
M mlir/examples/toy/Ch4/include/toy/Ops.td
M mlir/examples/toy/Ch5/include/toy/Ops.td
M mlir/examples/toy/Ch6/include/toy/Ops.td
M mlir/examples/toy/Ch7/include/toy/Ops.td
M mlir/include/mlir/Dialect/AMDGPU/IR/AMDGPUBase.td
M mlir/include/mlir/Dialect/Affine/IR/AffineOps.td
M mlir/include/mlir/Dialect/Arith/IR/ArithBase.td
M mlir/include/mlir/Dialect/ArmNeon/ArmNeon.td
M mlir/include/mlir/Dialect/ArmSME/IR/ArmSME.td
M mlir/include/mlir/Dialect/ArmSVE/IR/ArmSVE.td
M mlir/include/mlir/Dialect/Async/IR/AsyncDialect.td
M mlir/include/mlir/Dialect/Bufferization/IR/BufferizationBase.td
M mlir/include/mlir/Dialect/Complex/IR/ComplexBase.td
M mlir/include/mlir/Dialect/ControlFlow/IR/ControlFlowOps.td
M mlir/include/mlir/Dialect/DLTI/DLTIBase.td
M mlir/include/mlir/Dialect/EmitC/IR/EmitCBase.td
M mlir/include/mlir/Dialect/Func/IR/FuncOps.td
M mlir/include/mlir/Dialect/GPU/IR/GPUBase.td
M mlir/include/mlir/Dialect/IRDL/IR/IRDL.td
M mlir/include/mlir/Dialect/Index/IR/IndexDialect.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMDialect.td
M mlir/include/mlir/Dialect/LLVMIR/NVVMDialect.td
M mlir/include/mlir/Dialect/LLVMIR/ROCDLDialect.td
M mlir/include/mlir/Dialect/LLVMIR/VCIXOps.td
M mlir/include/mlir/Dialect/LLVMIR/XeVMOps.td
M mlir/include/mlir/Dialect/Linalg/IR/LinalgBase.td
M mlir/include/mlir/Dialect/MLProgram/IR/MLProgramBase.td
M mlir/include/mlir/Dialect/MPI/IR/MPI.td
M mlir/include/mlir/Dialect/Math/IR/MathBase.td
M mlir/include/mlir/Dialect/MemRef/IR/MemRefBase.td
M mlir/include/mlir/Dialect/NVGPU/IR/NVGPU.td
M mlir/include/mlir/Dialect/OpenACC/OpenACCBase.td
M mlir/include/mlir/Dialect/OpenMP/OpenMPDialect.td
M mlir/include/mlir/Dialect/PDL/IR/PDLDialect.td
M mlir/include/mlir/Dialect/PDLInterp/IR/PDLInterpOps.td
M mlir/include/mlir/Dialect/Ptr/IR/PtrDialect.td
M mlir/include/mlir/Dialect/Quant/IR/QuantBase.td
M mlir/include/mlir/Dialect/SCF/IR/SCFOps.td
M mlir/include/mlir/Dialect/SMT/IR/SMTDialect.td
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBase.td
M mlir/include/mlir/Dialect/Shape/IR/ShapeBase.td
M mlir/include/mlir/Dialect/Shard/IR/ShardBase.td
M mlir/include/mlir/Dialect/SparseTensor/IR/SparseTensorBase.td
M mlir/include/mlir/Dialect/Tensor/IR/TensorBase.td
M mlir/include/mlir/Dialect/Tosa/IR/TosaOpBase.td
M mlir/include/mlir/Dialect/Transform/IR/TransformDialect.td
M mlir/include/mlir/Dialect/UB/IR/UBOps.td
M mlir/include/mlir/Dialect/Vector/IR/Vector.td
M mlir/include/mlir/Dialect/WasmSSA/IR/WasmSSABase.td
M mlir/include/mlir/Dialect/X86/X86.td
M mlir/include/mlir/Dialect/XeGPU/IR/XeGPUDialect.td
M mlir/include/mlir/IR/BuiltinDialect.td
M mlir/include/mlir/IR/DialectBase.td
M mlir/test/lib/Dialect/Test/TestDialect.td
M mlir/test/mlir-tblgen/op-format-invalid.td
M mlir/test/mlir-tblgen/op-format.td
M mlir/test/python/python_test_ops.td
Log Message:
-----------
[mlir] Enable strict properties in assembly formats by default (#225742)
Make strict property assembly formats the default and remove redundant
per-dialect settings. Keep legacy test fixtures explicitly opted out and
update the documentation.
Downstream can opt out for now using `let
useStrictPropertiesInAssemblyFormat = 0;` ; This will be removed in a
future release.
Part of #155475
Assisted-by: Codex
Commit: 9f8d812535d90508d9932cc7c7d39756a5e5d2db
https://github.com/llvm/llvm-project/commit/9f8d812535d90508d9932cc7c7d39756a5e5d2db
Author: theRonShark <ron.lieberman at amd.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M clang/include/clang/CodeGen/CodeGenAction.h
M clang/include/clang/Interpreter/Interpreter.h
M clang/lib/CodeGen/BackendConsumer.h
M clang/lib/CodeGen/CodeGenAction.cpp
M clang/lib/Interpreter/DeviceOffload.cpp
M clang/lib/Interpreter/DeviceOffload.h
M clang/lib/Interpreter/Interpreter.cpp
M clang/unittests/Basic/CMakeLists.txt
R clang/unittests/Basic/TargetIDTest.cpp
Log Message:
-----------
Revert "[clang-repl] Implement IncrementalHIPDeviceParser for HIP device compilation" (#226679)
Reverts llvm/llvm-project#218337 buildbot failures
Commit: 10872feadab49e23b8a2ef831dc454b712937ae2
https://github.com/llvm/llvm-project/commit/10872feadab49e23b8a2ef831dc454b712937ae2
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
A llvm/test/Transforms/SLPVectorizer/AArch64/reduced-value-next-to-fused-fmul.ll
A llvm/test/Transforms/SLPVectorizer/AMDGPU/fmul-sunk-into-fadd-block.ll
Log Message:
-----------
[SLP][NFC]Add extra FMA candidates tests, NFC
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/226684
Commit: 8b96ddbf9cb3437ee4e47a9f60dc983a1f2be8d5
https://github.com/llvm/llvm-project/commit/8b96ddbf9cb3437ee4e47a9f60dc983a1f2be8d5
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
A llvm/test/Transforms/SLPVectorizer/X86/trimmed-node-matching-gather-emitted-first.ll
Log Message:
-----------
[SLP]Do not reuse transformed nodes in gathers emitted before their user
Gathers of the users with all scalars used outside the block are emitted
before the user, while the transformed nodes are emitted with the user.
Reusing such a transformed node postponed the gather and moved only the
last instruction of the transformed node buildvector, breaking dominance.
Fixes #226674
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/226687
Commit: ea0493b90c036776652105da246ce3fa56e33901
https://github.com/llvm/llvm-project/commit/ea0493b90c036776652105da246ce3fa56e33901
Author: Balázs Benics <benicsbalazs at gmail.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
A clang/include/clang/ScalableStaticAnalysis/Analyses/VirtualMethodFamily/VirtualMethodFamily.h
M clang/include/clang/ScalableStaticAnalysis/BuiltinAnchorSources.def
M clang/lib/ScalableStaticAnalysis/Analyses/CMakeLists.txt
A clang/lib/ScalableStaticAnalysis/Analyses/VirtualMethodFamily/VirtualMethodEntityExtractor.cpp
A clang/unittests/ScalableStaticAnalysis/Analyses/VirtualMethodFamily/VirtualMethodFamilyExtractorTest.cpp
A clang/unittests/ScalableStaticAnalysis/Analyses/VirtualMethodFamily/VirtualMethodFamilyTestSupport.h
M clang/unittests/ScalableStaticAnalysis/CMakeLists.txt
A clang/unittests/ScalableStaticAnalysis/ParsedAST.h
Log Message:
-----------
[SSAF] Extract the virtual method override relation per TU (#213316)
A virtual call may dispatch to any override of its callee, so a whole-program
analysis cannot reason about a method's parameters and return value in
isolation. It needs to know which method overrides which, and which slots
that relates. Collect this per TU, so a later pass can join the related
slots into families.
JSON serialization lands separately, so the summary is not writable via
`--ssaf-extract-summaries` yet.
§1 of rdar://179151603
Assisted-By: claude
Commit: 2305da864cb3b66e1fe857c3018bf7d94253bb8a
https://github.com/llvm/llvm-project/commit/2305da864cb3b66e1fe857c3018bf7d94253bb8a
Author: Dmitry Sidorov <Dmitry.Sidorov at amd.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
A llvm/test/Transforms/SLPVectorizer/AMDGPU/cross-block-fmul-fadd.ll
Log Message:
-----------
[NFC][SLP][AMDGPU] Precommit a cross-block fmul fadd contraction test (#226609)
Two contract fmuls feed contract fadds in different successors. AMDGPU
sinks such an fmul into the block of its user and fuses the pair, so the
scalar form is one fma per path. Record the current behaviour, the pair
is kept scalar when the fmul is operand 0 of the fadd and paired when it
is operand 1.
Commit: 6b85e67a473ebe127aa31b742adc1fe2d53cb5bf
https://github.com/llvm/llvm-project/commit/6b85e67a473ebe127aa31b742adc1fe2d53cb5bf
Author: Konstantinos Parasyris <koparasy at gmail.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M clang/include/clang/CIR/Dialect/IR/CIRCUDAAttrs.td
M clang/include/clang/CIR/Dialect/IR/CIRDialect.td
M clang/lib/CIR/CodeGen/CIRGenCUDANV.cpp
M clang/lib/CIR/CodeGen/CIRGenModule.cpp
M clang/lib/CIR/Dialect/IR/CIRDialect.cpp
M clang/lib/CIR/Dialect/Transforms/LoweringPrepare.cpp
M clang/test/CIR/CodeGenCUDA/device-stub.cu
A clang/test/CIR/CodeGenCUDA/missing-gpubinary.cu
A clang/test/CIR/Diagnostics/mlir-error-routing.cpp
R clang/test/CIR/Diagnostics/mlir-error-routing.cu
A clang/test/CIR/IR/invalid-cuda-device-binary.cir
Log Message:
-----------
[CIR][CUDA] Read fat binary in CIRGen and store its bytes on the module (#225971)
Two problems with the current implementation of GPU CIR:
1. `LoweringPrepare` read the fat binary from disk, via
`astCtx->getSourceManager().getFileManager().getVirtualFileSystem()`. A
transform pass should not do I/O, and this is one of the `ASTContext`
dependencies that keeps the post-CIRGen pipeline from being IR-to-IR.
Some of the related discussion on this has been done
[here](https://discourse.llvm.org/t/rfc-clangir-making-cir-pipeline-boundaries-first-class-driver-artifacts/90998)
and PR: #219048
2. `#cir.cu.binary_handle` stored the *file path*. That's a build input,
not a
property of the program: it bakes one machine's directory layout into a
`.cir`.
The PR removes the file path and adds an attribute
CIRGen now reads the file in and records the contents
as `#cir.cu.device_binary`, a `StringAttr` of raw bytes. The
attribute is deleted once LoweringPrepare "consumes" it.
A couple of notes:
1. The GPU dialect has a similar representation. We may want to move
towards that direction slowly, but I don't see any value doing this now.
It will confuse the direction of this PR.
2. The test `clang/test/CIR/Diagnostics/mlir-error-routing.cu` has
completely
changed, because it relied on an error occurring when the file attribute
was missing.
Since we deleted that attribute completely, the test was failing.
---------
Co-authored-by: Claude Opus 5 <noreply at anthropic.com>
Commit: 0a90c92d5285cae7f7b7ae26573e39df5898cafc
https://github.com/llvm/llvm-project/commit/0a90c92d5285cae7f7b7ae26573e39df5898cafc
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M mlir/examples/toy/Ch4/include/toy/Ops.td
M mlir/examples/toy/Ch5/include/toy/Ops.td
M mlir/examples/toy/Ch6/include/toy/Ops.td
M mlir/examples/toy/Ch7/include/toy/Ops.td
M mlir/test/Analysis/DataFlow/test-last-modified-callgraph.mlir
M mlir/test/Analysis/DataFlow/test-last-modified.mlir
M mlir/test/Analysis/DataFlow/test-next-access.mlir
M mlir/test/Analysis/DataFlow/test-strided-metadata-range-analysis.mlir
M mlir/test/Dialect/Affine/affine-loop-normalize.mlir
M mlir/test/Dialect/Affine/int-range-interface.mlir
M mlir/test/Dialect/Affine/simplify-min-max-ops.mlir
M mlir/test/Dialect/Affine/simplify-with-bounds.mlir
M mlir/test/Dialect/Affine/transform-op-simplify-min-max-ops.mlir
M mlir/test/Dialect/Arith/int-range-analysis-convergence.mlir
M mlir/test/Dialect/Arith/int-range-interface.mlir
M mlir/test/Dialect/Arith/int-range-loop-iter-args.mlir
M mlir/test/Dialect/Arith/int-range-narrowing.mlir
M mlir/test/Dialect/Arith/int-range-opts-bug-119045.mlir
M mlir/test/Dialect/Arith/int-range-opts.mlir
M mlir/test/Dialect/GPU/int-range-interface-cluster.mlir
M mlir/test/Dialect/GPU/int-range-interface.mlir
M mlir/test/Dialect/MLProgram/pipeline-globals.mlir
M mlir/test/Dialect/MemRef/int-range-inference.mlir
M mlir/test/Dialect/OpenACC/acc-implicit-routine.mlir
M mlir/test/Dialect/Tensor/int-range-inference.mlir
M mlir/test/Dialect/Vector/int-range-interface.mlir
M mlir/test/IR/attribute.mlir
M mlir/test/Interfaces/InferIntRangeInterface/infer-int-range-test-ops-invalid.mlir
M mlir/test/Interfaces/InferIntRangeInterface/infer-int-range-test-ops.mlir
M mlir/test/Transforms/loop-invariant-code-motion.mlir
M mlir/test/Transforms/make-composed-folded-affine-apply.mlir
M mlir/test/lib/Dialect/Test/TestDialect.td
M mlir/test/lib/Dialect/Test/TestOps.td
M mlir/test/lib/Dialect/Test/TestOpsSyntax.td
M mlir/test/mlir-tblgen/constant-str-attr-invalid.mlir
M mlir/test/mlir-tblgen/op-format-invalid.td
M mlir/test/mlir-tblgen/op-format.mlir
M mlir/test/mlir-tblgen/op-format.td
M mlir/test/mlir-tblgen/pattern.mlir
M mlir/test/python/dialects/python_test.py
M mlir/test/python/python_test_ops.td
Log Message:
-----------
[mlir] Remove remaining strict property assembly opt-outs (#226702)
Migrate Toy, test, and Python dialect formats to use prop-dict for
inherent properties. Update assembly fixtures and expected output for
strict property printing.
Assisted-by: Codex
Commit: 688a1498b3ce9011ee58c214086e3cd408e86f5e
https://github.com/llvm/llvm-project/commit/688a1498b3ce9011ee58c214086e3cd408e86f5e
Author: Amit Tiwari <Amit.Tiwari at amd.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M clang/lib/Sema/SemaOpenMP.cpp
A clang/test/OpenMP/collapse_iv_width_codegen.cpp
Log Message:
-----------
[Clang][OpenMP] Optimize `collapse` IV bit-width precision expression (#225612)
`collapse` used to build both a 32-bit and a 64-bit trip-count, then
keep one.
This patch does the same in `checkOpenMPLoop`:
If we know 32-bit is enough, build only 32-bit.
Else build 64-bit first.
Build 32-bit only when the product is a compile-time constant and fits.
Origin: `flatten` already builds only the width it keeps.
Commit: e217205575ac65acd6d301b036bea8875f5eaa16
https://github.com/llvm/llvm-project/commit/e217205575ac65acd6d301b036bea8875f5eaa16
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/conditional-scalar-assignment-fold-tail.ll
M llvm/test/Transforms/LoopVectorize/AArch64/conditional-scalar-assignment.ll
M llvm/test/Transforms/LoopVectorize/RISCV/conditional-scalar-assignment-fold-tail.ll
M llvm/test/Transforms/LoopVectorize/RISCV/conditional-scalar-assignment.ll
M llvm/test/Transforms/LoopVectorize/X86/conditional-scalar-assignment.ll
M llvm/test/Transforms/LoopVectorize/find-last-ptr-induction.ll
M llvm/test/Transforms/LoopVectorize/iv-select-cmp-non-const-iv-start.ll
M llvm/test/Transforms/LoopVectorize/iv-select-cmp-trunc.ll
M llvm/test/Transforms/LoopVectorize/iv-select-cmp.ll
Log Message:
-----------
[VPlan] Mark default value or ExtractLastActive as only first lane used. (#226153)
The default value (operand 0) of ExtractLastActive is the scalar value
of @llvm.experimental.vector.extract.last.active. Only the first lane is
used, mark accordingly.
PR: https://github.com/llvm/llvm-project/pull/226153
Commit: f950b04465ee6a198f3fa5644e4f70711041df8a
https://github.com/llvm/llvm-project/commit/f950b04465ee6a198f3fa5644e4f70711041df8a
Author: Kazu Hirata <kazu at google.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M llvm/include/llvm/Transforms/Utils/LoopUtils.h
M llvm/lib/Transforms/Utils/LoopUnroll.cpp
M llvm/lib/Transforms/Utils/LoopUtils.cpp
Log Message:
-----------
[Transforms] Remove unused functions (NFC) (#226655)
createAnyOfReduction:
The last caller was removed on January 18, 2026 in commit
ae1bd068db293c494c4c6314da3b9d138706460d.
canHaveUnrollRemainder:
The last caller, in an assert, was removed on May 1, 2026 in commit
316f0d3bfeaf7eee7b6d4ae60d357a8216ec5264.
Assisted-by: Antigravity
Commit: ab52e9f971d626346d70190df72636b477f6c089
https://github.com/llvm/llvm-project/commit/ab52e9f971d626346d70190df72636b477f6c089
Author: Yordan Vásquez <vyordangiovani at gmail.com>
Date: 2026-09-27 (Sun, 27 Sep 2026)
Changed paths:
M libcxx/include/complex
M libcxx/include/valarray
A libcxx/test/std/numerics/complex.number/complex/complex_requires_cv_unqualified_object.verify.cpp
A libcxx/test/std/numerics/numarray/template.valarray/valarray_requires_cv_unqualified_object.verify.cpp
Log Message:
-----------
[libc++] Add static_assert diagnostics for LWG3133 named requirements (#212360)
Add a static_assert to both std::complex<T> and std::valarray<T>
requiring that T be a cv-unqualified object type that satisfies the
Cpp17DefaultConstructible, Cpp17CopyConstructible, Cpp17CopyAssignable,
and Cpp17Destructible named requirements, per the revised wording in
[numeric.requirements]. This mirrors the existing pattern already used
by std::optional<T>.
Non-_v (class-style) trait forms are used throughout so that the
assertion is well-formed even when <complex>/<valarray> are included in
C++03/11/14 mode.
Test coverage:
- A .verify.cpp for complex<T> and one for valarray<T>, each covering
six failure modes: cv-qualified types, and one type violating each of
the four named requirements individually.
Follows-up e062a29cf865bb7cadea6cb605c9f3515e5b883f.
Commit: 5302d361339066363854a4e12e16e413af9ce1ce
https://github.com/llvm/llvm-project/commit/5302d361339066363854a4e12e16e413af9ce1ce
Author: geoffreygaren <ggaren at apple.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M clang/docs/analyzer/checkers.md
M clang/lib/StaticAnalyzer/Checkers/WebKit/ASTUtils.cpp
M clang/lib/StaticAnalyzer/Checkers/WebKit/PtrTypesSemantics.cpp
M clang/lib/StaticAnalyzer/Checkers/WebKit/PtrTypesSemantics.h
M clang/test/Analysis/Checkers/WebKit/mock-canborrow.h
M clang/test/Analysis/Checkers/WebKit/unborrowed-call-args.cpp
M clang/test/Analysis/Checkers/WebKit/unborrowed-local-vars-cxx23.cpp
M clang/test/Analysis/Checkers/WebKit/unborrowed-local-vars.cpp
Log Message:
-----------
[WebKit Checkers] Add built-in recognition for standard view types (#226350)
libc++ doesn't fully annotate `[[clang::lifetimebound]]` for all view
types. This results in false negatives in borrow checking.
Ultimately we need to fix this in libc++, but for now we can work around
the most common / most important false negatives. For example, borrow
checking can now check
for (auto& x : vector | std::views::reverse) { ... }
Assisted-by: Claude
Commit: 207f7f00ced9adf54e79f2bbf2c59a485a608495
https://github.com/llvm/llvm-project/commit/207f7f00ced9adf54e79f2bbf2c59a485a608495
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M llvm/test/Analysis/CostModel/X86/arith-fp.ll
Log Message:
-----------
[CostModel][X86] arith-fp.ll - test AVX512DQ instead of AVX512BW (#226519)
AVX512DQ has instructions relevant to fp arithmetic (vXi64 fp2int in particular)
Commit: d297af3b3d7a086d64f1477cfa682a16fcfa3260
https://github.com/llvm/llvm-project/commit/d297af3b3d7a086d64f1477cfa682a16fcfa3260
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
A llvm/test/Transforms/LoopVectorize/AArch64/sve-induction-wrapflags.ll
M llvm/test/Transforms/LoopVectorize/induction-wrapflags.ll
Log Message:
-----------
[LV] Add tests for wide induction wrap flags (NFC). (#226715)
Add tests for:
* inductions where the lane offsets may signed-overflow, even if the
scalar induction values do not,
* inductions whose increment does not directly update the phi, where the
increment's wrap flags do not apply to the induction,
* narrow inductions where the VF may exceed the signed maximum of the
induction type.
Commit: 555d8a58b85f0cfcbad0fc7cf7b13bbef4d4ca30
https://github.com/llvm/llvm-project/commit/555d8a58b85f0cfcbad0fc7cf7b13bbef4d4ca30
Author: David Green <david.green at arm.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64PerfectShuffle.h
Log Message:
-----------
[AArch64] Reorganise perfect shuffle generation. NFC (#224526)
This adds a generatePerfectShuffle implementation for parsing through
the perfect shuffle tables, generating a list of ShuffleEntry's that
represent the sequence of shuffles that need to be performed. This is
intended to be a NFC as-is, allowing it to be reused in global isel and
extended in the future to handle shuffles that are not part of the
shuffle table. The number of instructions generated can also be used for
costing shuffles, as we do for immediate generation.
Commit: 0ead65c731fa09596fbcc9b5109e504e9e7adb7e
https://github.com/llvm/llvm-project/commit/0ead65c731fa09596fbcc9b5109e504e9e7adb7e
Author: Michael G. Kazakov <mike.kazakov at gmail.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
A libcxx/test/benchmarks/algorithms/nonmodifying/pstl.find.bench.cpp
A libcxx/test/benchmarks/algorithms/sorting/pstl.sort.bench.cpp
A libcxx/test/benchmarks/numeric/pstl.transform_reduce.bench.cpp
Log Message:
-----------
[libc++][pstl] Add more benchmarks of the parallel algorithms (#225908)
This PR adds benchmarks of these 3 parallel algorithms:
- `std::find(policy, ...)`
- `std::sort(policy, ...)`
- `std::transform_reduce(policy, ...)`
---------
Co-authored-by: Louis Dionne <ldionne.2 at gmail.com>
Commit: 6aefa9a60eb523ca3d8601ab69509e057730ac8d
https://github.com/llvm/llvm-project/commit/6aefa9a60eb523ca3d8601ab69509e057730ac8d
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M llvm/lib/Target/ARM/ARMTargetMachine.cpp
M llvm/lib/Target/ARM/ARMTargetMachine.h
M llvm/lib/Target/ARM/ARMTargetObjectFile.cpp
M llvm/lib/Target/ARM/ARMTargetObjectFile.h
M llvm/test/CodeGen/ARM/module-target-abi.ll
Log Message:
-----------
ARM: Remove cached TargetABI from ARMBaseTargetMachine (#226482)
This cannot account for the "target-abi" module flag, so
let the uses query that. ARMElfTargetObjectFile was the one user of
this value, so this failed to respect the module flag.
Co-Authored-By: Claude Opus 5 <noreply at anthropic.com>
Commit: fc99ddb168769dd732f40b74c09f9d800c30e7e3
https://github.com/llvm/llvm-project/commit/fc99ddb168769dd732f40b74c09f9d800c30e7e3
Author: Alan Zhao <ayzhao at google.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M llvm/cmake/modules/GetLibraryName.cmake
Log Message:
-----------
[cmake][Windows] Do not strip library prefixes on Windows (#226635)
Commit: 808c726db2fe24f7ba2901f5701ae19cfe602f0a
https://github.com/llvm/llvm-project/commit/808c726db2fe24f7ba2901f5701ae19cfe602f0a
Author: Prajit Rahul <prajitrahul05 at gmail.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M llvm/docs/Lexicon.md
Log Message:
-----------
[LLVM][Docs] Define IR in the lexicon (#221388)
Define IR in the LLVM lexicon using terminology from the LLVM Language
Reference Manual, including its SSA-based structure and three equivalent
representations.
Fixes #139867
AI Usage: ChatGPT
Commit: 315a38a1ef3825e4e7ebe188353b4c5329751453
https://github.com/llvm/llvm-project/commit/315a38a1ef3825e4e7ebe188353b4c5329751453
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
M llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
M llvm/lib/Transforms/Vectorize/VPlanUtils.h
M llvm/test/Transforms/LoopVectorize/AArch64/epilog-vectorization-widen-inductions.ll
M llvm/test/Transforms/LoopVectorize/X86/pr36524.ll
M llvm/test/Transforms/LoopVectorize/induction-wrapflags.ll
M llvm/test/Transforms/LoopVectorize/induction.ll
M llvm/test/Transforms/LoopVectorize/pr30654-phiscev-sext-trunc.ll
M llvm/test/Transforms/LoopVectorize/pr35773.ll
M llvm/test/Transforms/LoopVectorize/predicated-inductions.ll
M llvm/test/Transforms/LoopVectorize/single-value-blend-phis.ll
Log Message:
-----------
[VPlan] Take wide induction wrap flags from the increment of the phi. (#226726)
The binary operator of an integer InductionDescriptor is the incoming
value from the latch, which is not required to have the phi as operand.
E.g. for
%x = add i32 %iv, 5
%iv.next = add nuw nsw i32 %x, 1
the flags only apply to %x + 1, while the induction step is 6, and %iv +
6 may wrap even though %iv.next does not. Determine the wrap flags from
the increment of the header phi instead, and only if it adds to or
subtracts from the phi directly.
Commit: 899d817c7950c997402cd229935cd822acf45b08
https://github.com/llvm/llvm-project/commit/899d817c7950c997402cd229935cd822acf45b08
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/sve-low-trip-count.ll
M llvm/test/Transforms/LoopVectorize/RISCV/countable-early-exit-no-epilogue.ll
Log Message:
-----------
[LV] Skip low-trip count logic there is no scalar tail. (#225633)
https://github.com/llvm/llvm-project/pull/195823 added logic consider
vectorization of low trip count loops if there was no or a single
iteration remaining.
This causes loops to be vectorized with a VF where no scalar tail
remains, even if it is required for legality (loop with multiple
countable exits require scalar epilogue to pick the exit).
For now, limit to cases where there's a scalar iteration remaining.
PR: https://github.com/llvm/llvm-project/pull/225633
Commit: e0b3e4c82911376fcb2dfcbc4a3dd3f4f5891aba
https://github.com/llvm/llvm-project/commit/e0b3e4c82911376fcb2dfcbc4a3dd3f4f5891aba
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M llvm/include/llvm/Analysis/LoopAccessAnalysis.h
M llvm/lib/Analysis/LoopAccessAnalysis.cpp
Log Message:
-----------
[LAA] Remove unused functions (NFC) (#226733)
Remove RuntimePointerChecking::empty and LoopAccessInfo::getNumLoads /
getNumStores, which have no callers, together with the NumLoads and
NumStores counters that were only read by the latter.
Commit: 8c153f78f7c0a842edfee3f1601dee1776c941d6
https://github.com/llvm/llvm-project/commit/8c153f78f7c0a842edfee3f1601dee1776c941d6
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M llvm/include/llvm/Analysis/ScalarEvolutionExpressions.h
Log Message:
-----------
[SCEV] Remove unused classof(const SCEVUse *) overloads (NFC) (#226734)
isa/cast/dyn_cast on SCEVUse go through simplify_type or CastInfo.
classof(SCEVUse) is unused.
Commit: 7615da10b75c57286a4032eac8bb43c1b8d2ba46
https://github.com/llvm/llvm-project/commit/7615da10b75c57286a4032eac8bb43c1b8d2ba46
Author: Dan Salvato <dan at teamsalvato.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M llvm/lib/Target/M68k/M68kExpandPseudo.cpp
M llvm/lib/Target/M68k/M68kInstrArithmetic.td
M llvm/lib/Target/M68k/M68kInstrData.td
M llvm/lib/Target/M68k/M68kInstrInfo.cpp
M llvm/lib/Target/M68k/M68kInstrInfo.h
M llvm/test/CodeGen/M68k/Arith/divide-by-constant.ll
M llvm/test/CodeGen/M68k/Arith/smul-with-overflow.ll
M llvm/test/CodeGen/M68k/Arith/umul-with-overflow.ll
M llvm/test/CodeGen/M68k/Bits/btst.ll
M llvm/test/CodeGen/M68k/Control/cmp.ll
M llvm/test/CodeGen/M68k/Control/non-cmov-switch.ll
M llvm/test/CodeGen/M68k/Control/setcc.ll
M llvm/test/CodeGen/M68k/Data/load-extend.ll
M llvm/test/CodeGen/M68k/Data/sext-i1.ll
M llvm/test/CodeGen/M68k/register-spills.ll
Log Message:
-----------
[M68k] Finish implementation of `MOVX` (move and extend) pseudo-instructions and fix related errors (#218938)
This patch adds remaining addressing modes to the "move and extend"
pseudo-instructions, and fixes a few errors and inconsistencies in the
logic that caused inefficient code generation.
- Remaining addressing modes were implemented to match non-pseudo `MOVE`
instructions.
- Names of the pseudos now correctly reflect the register classes they
operate on, e.g. `MOVZXd32r16` for XR16 -> DR32.
- Fixed an issue where `MOVZX` could be allocated to an address
register, which has no way to zero-extend the result. (There were even
some of these in the test `register-spills.ll`, emitted as illegal
instructions, but the test doesn't have instruction verification
enabled, so it wasn't caught.)
- Fixed some `extload` patterns where the register was unnecessarily
extended to 32 bits before being truncated to its final size, causing
redundant instructions to be omitted.
- Fixed `anyext` patterns lowering to `MOVZX` instead of `MOVX`, causing
unnecessary zero-extensions.
- An inconsistency was fixed where the expansion logic would perform a
source-sized move when loading from memory, but a destination-sized move
when moving between registers. They now always perform a source-sized
move, which improves clarity in the assembly output and has more
opportunity for future optimizations.
Commit: bf529329b5ce85d42a5c793951ec9b31100cd84e
https://github.com/llvm/llvm-project/commit/bf529329b5ce85d42a5c793951ec9b31100cd84e
Author: Alexander Richardson <alexrichardson at google.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
A clang/test/CodeGen/RISCV/lto-module-asm-abi.c
A cross-project-tests/.clang-format
A cross-project-tests/riscv/lit.local.cfg
A cross-project-tests/riscv/lto-inline-asm-abi.c
M lld/test/ELF/lto/riscv-target-abi.ll
M llvm/test/CodeGen/RISCV/module-asm-features.ll
M llvm/test/CodeGen/RISCV/riscv-func-target-feature.ll
M llvm/test/LTO/RISCV/module-asm.ll
M llvm/test/MC/RISCV/mapping-across-sections.s
Log Message:
-----------
[RISC-V][LTO] Add baseline tests for LTO inline assembly and mapping symbols (#225129)
No functional change intended here, just adding test coverage for RISC-V LTO
inline assembly ABI handling (following up on
https://github.com/llvm/llvm-project/pull/223606) and for the `$x<arch>` ELF
mapping symbols emitted for module and function target features.
The `TODO`s for `.lto_discard` dropping module inline asm target features and
for the missing/duplicate `$x<arch>` mapping symbols will be addressed in the
following commits.
This commit was created with the help of AI tools
Pull-Request: https://github.com/llvm/llvm-project/pull/225129
Commit: 22d3cccd0beaf7d2c7728d0bc6fa347283b0bc13
https://github.com/llvm/llvm-project/commit/22d3cccd0beaf7d2c7728d0bc6fa347283b0bc13
Author: Alexander Richardson <alexrichardson at google.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M cross-project-tests/riscv/lto-inline-asm-abi.c
M llvm/lib/LTO/LTO.cpp
M llvm/lib/Linker/IRMover.cpp
M llvm/test/LTO/RISCV/module-asm.ll
Log Message:
-----------
[LTO] Preserve module inline asm target properties for .lto_discard and symvers (#225130)
Previously, LTO::addRegularLTO() and IRLinker::run() called
prependModuleInlineAsm() and appendModuleInlineAsm() with a plain string when
synthesizing `.lto_discard` and imported `.symver` directives, creating a new
GlobalAsmFragment with empty TargetCPU and TargetFeatures instead of preserving
the existing module inline asm's properties. Copy the front fragment's Props so
these synthesized directives are merged into the module's inline asm with the
same target features.
This commit was created with the help of AI tools
Pull-Request: https://github.com/llvm/llvm-project/pull/225130
Commit: 0ab3502ec56a5d8330c79849945b9fefd2668f01
https://github.com/llvm/llvm-project/commit/0ab3502ec56a5d8330c79849945b9fefd2668f01
Author: Alexander Richardson <alexrichardson at google.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp
M llvm/test/MC/RISCV/mapping-across-sections.s
Log Message:
-----------
[RISC-V][MC] Fix mapping symbol section tracking on popSection() (#225131)
Previously, RISCVELFStreamer::changeSection() saved LastEMS and LastEmittedArch
under getPreviousSection().first instead of getCurrentSection().first. When
MCStreamer::popSection() switches back to a previous section,
getPreviousSection() already points to the destination section being restored
rather than the section being exited. This clobbered the destination section's
saved mapping symbol state and caused duplicate `$x<arch>` mapping symbols to
be emitted whenever returning to `.text`.
Use getCurrentSection().first instead, matching AArch64ELFStreamer and
ARMELFStreamer.
This commit was created with the help of AI tools
Pull-Request: https://github.com/llvm/llvm-project/pull/225131
Commit: 6eeb3b4ebdae20cd5f1e0fe5e74df3b418b654e2
https://github.com/llvm/llvm-project/commit/6eeb3b4ebdae20cd5f1e0fe5e74df3b418b654e2
Author: Alexander Richardson <alexrichardson at google.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M cross-project-tests/riscv/lto-inline-asm-abi.c
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.h
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.h
Log Message:
-----------
[RISC-V][MC] Update ELF streamer ArchString in setFlagsFromFeatures() (#225140)
During LTO, the TargetMachine subtarget is initialized with the linker's
default CPU (e.g. `generic-rv64`, `rv64i2p1`), while
RISCVAsmPrinter::emitStartOfAsmFile() reconstructs the module's actual ISA from
the `riscv-isa` module flag and calls RISCVTargetStreamer::setFlagsFromFeatures()
and RISCVTargetStreamer::emitTargetAttributes(). Because
RISCVTargetELFStreamer previously only initialized InitialArchString and
ArchString in its constructor rather than in setFlagsFromFeatures(), direct
object emission bypassed the update and tagged `.text` with `$xrv64i2p1`
instead of the module's full architecture string.
Move the InitialArchString and ArchString initialization into
RISCVTargetELFStreamer::setFlagsFromFeatures() and also call setArchString()
alongside emitTextAttribute(RISCVAttrs::ARCH, ...) in
RISCVTargetStreamer::emitTargetAttributes().
This commit was created with the help of AI tools
Pull-Request: https://github.com/llvm/llvm-project/pull/225140
Commit: 0e2ebe79f5c4ea36d7daecb76fb4867452d6973e
https://github.com/llvm/llvm-project/commit/0e2ebe79f5c4ea36d7daecb76fb4867452d6973e
Author: Alexander Richardson <alexrichardson at google.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
M llvm/test/CodeGen/RISCV/module-asm-features.ll
M llvm/test/CodeGen/RISCV/riscv-func-target-feature.ll
Log Message:
-----------
[RISC-V] Update streamer ArchString in emitTargetFeaturePush() (#225133)
Previously, RISCVAsmPrinter::emitTargetFeaturePush() only emitted `.option push`
and `.option arch` without updating the streamer's active ArchString. When
emitting an ELF object file directly (`-filetype=obj`),
RISCVTargetELFStreamer::emitDirectiveOptionArch() is a no-op while
emitTargetFeaturePop() resets ArchString back to the pushed ArchString, so
module-level inline assembly and functions with custom `target-features` failed
to emit updated `$x<arch>` mapping symbols.
Call RTS.setArchString() with the parsed ISA string in emitTargetFeaturePush()
so `-filetype=obj` records the active `$x<arch>` mapping symbol alongside
`.option arch`.
This commit was created with the help of AI tools
Pull-Request: https://github.com/llvm/llvm-project/pull/225133
Commit: b380036c75b82ab16aa988331b65cea6323091e7
https://github.com/llvm/llvm-project/commit/b380036c75b82ab16aa988331b65cea6323091e7
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M .github/workflows/docs.yml
Log Message:
-----------
[Github] Build BOLT docs on changes (#226747)
We were already set up to build the BOLT docs, but the workflow did not
actually trigger on changes to the BOLT docs specifically. This change
fixes that.
Commit: fb9596b7117dac3a1bc680b1041464944d0caa24
https://github.com/llvm/llvm-project/commit/fb9596b7117dac3a1bc680b1041464944d0caa24
Author: Letu Ren <fantasquex at gmail.com>
Date: 2026-09-27 (Sun, 27 Sep 2026)
Changed paths:
M mlir/lib/Target/LLVMIR/Dialect/LLVMIR/LLVMToLLVMIRTranslation.cpp
M mlir/test/Target/LLVMIR/llvmir.mlir
Log Message:
-----------
[MLIR][LLVM] Produce canonical const GEP in convertGEPOp (#226699)
The DataLayout overload of ConstantExpr::getGetElementPtr is the form
that replaces typed constant GEPs. Use it for inrange GEPs and fail
translation when the indices cannot be reduced to a byte offset.
This resolves
https://github.com/llvm/llvm-project/pull/220424#discussion_r4092337505
Assisted-by: grok-4.7
Signed-off-by: Letu Ren <fantasquex at gmail.com>
Commit: e54a8d183eda0097771b422399ee929a334fb0af
https://github.com/llvm/llvm-project/commit/e54a8d183eda0097771b422399ee929a334fb0af
Author: Alan Zhao <ayzhao at google.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M llvm/cmake/modules/GetLibraryName.cmake
Log Message:
-----------
[cmake][Windows] Fix CMake variable (#226745)
As a follow-up fix to #226635, the variable is `WIN32` not `Win32`.
Commit: 32ee4f7ed0ba2f169d22416c73360146153c9711
https://github.com/llvm/llvm-project/commit/32ee4f7ed0ba2f169d22416c73360146153c9711
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M llvm/include/llvm/CodeGen/SDPatternMatch.h
Log Message:
-----------
[SDPatternMatch] Simplify EffectiveOperands and drop the template specialization. NFC (#226036)
The chain and glue operands are in fixed locations, we don't need a loop
to find them.
Use the template parameter to skip the constructor body instead of using
template specialization.
Commit: 50f802581bd16b82bd68a9a4682cdbdc560368df
https://github.com/llvm/llvm-project/commit/50f802581bd16b82bd68a9a4682cdbdc560368df
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-09-27 (Sun, 27 Sep 2026)
Changed paths:
M clang/include/clang/AST/APValue.h
M clang/lib/AST/ExprConstant.cpp
Log Message:
-----------
[clang][AST] Mark APValue as LLVM_ATTRIBUTE_WARN_UNUSED (#226632)
Commit: 4c85cbebc59d62d6845ea31f649d8519813b55ff
https://github.com/llvm/llvm-project/commit/4c85cbebc59d62d6845ea31f649d8519813b55ff
Author: Reid Kleckner <rkleckner at nvidia.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M clang/docs/AllocToken.md
M clang/docs/ClangLinkerWrapper.md
M clang/docs/ClangOffloadBundler.md
M clang/docs/ClangTransformerTutorial.md
M clang/docs/ControlFlowIntegrity.md
M clang/docs/ControlFlowIntegrityDesign.md
M clang/docs/InternalsManual.md
M clang/docs/IntroductionToTheClangAST.md
M clang/docs/LanguageExtensions.md
M clang/docs/LibASTImporter.md
M clang/docs/LifetimeSafety.md
M clang/docs/SafeBuffers.md
M clang/docs/ScalableStaticAnalysis/user-docs/SummaryExtraction.md
M clang/docs/WarningSuppressionMappings.md
M clang/docs/analyzer/checkers.md
M clang/docs/analyzer/user-docs/Annotations.md
M clang/docs/conf.py
M clang/include/clang/Basic/AttrDocs.td
M llvm/docs/SphinxQuickstartTemplate.md
M utils/docs/llvm_sphinx/ext/absolute_links.py
M utils/docs/llvm_sphinx/ext/absolute_links_test/markdown.md
Log Message:
-----------
[docs] Replace clang.llvm.org/docs links with Sphinx links (#222507)
Use Sphinx document and option roles or project-relative links for links
within the Clang documentation. Repair stale generated-document
fragments found while validating the replacements. This ensures that
standalone documentation builds are self-contained, although
cross-project links (Clang->LLVM) typically go via absolute llvm.org
hrefs.
Part of #214861
Assisted-by: Codex
Commit: dbea9bd01b3ffec3ff35bfacb628257db8655ee5
https://github.com/llvm/llvm-project/commit/dbea9bd01b3ffec3ff35bfacb628257db8655ee5
Author: Amilendra Kodithuwakku <amilendra.kodithuwakku at arm.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M bolt/docs/conf.py
Log Message:
-----------
[docs][bolt] Remove Markdown enum (#226411)
Remove use of Markdown enum from the bolt docs. Related to #223829.
This should fix our ATfL build
[failure](https://github.com/arm/arm-toolchain/actions/runs/36103090912/job/107969633028#step:7:22533)
```
Traceback (most recent call last):
File "/workspace/python/.venv/lib/python3.12/site-packages/sphinx/config.py", line 529, in eval_config_file
exec(code, namespace) # NoQA: S102
^^^^^^^^^^^^^^^^^^^^^
File "/workspace/src/bolt/docs/conf.py", line 18, in <module>
globals().update(common_conf(tags, markdown=Markdown.NEVER))
^^^^^^^^
NameError: name 'Markdown' is not defined
```
Commit: 126dbd97fc5d33edf43a1fce12fb5d3ea46e5be7
https://github.com/llvm/llvm-project/commit/126dbd97fc5d33edf43a1fce12fb5d3ea46e5be7
Author: Alexander Richardson <alexrichardson at google.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M clang/test/CodeGen/RISCV/lto-module-asm-abi.c
Log Message:
-----------
[Clang][RISC-V] Fix lto-module-asm-abi.c on non-asserts/no-lld builds (#226752)
Pass `-fno-discard-value-names` so the `entry:` label is preserved in
non-asserts builds, and drop `-fuse-ld=lld` so the driver check succeeds
on bots that do not have `ld.lld` installed.
Fixes: bf529329b5ce ("[RISC-V][LTO] Add baseline tests for LTO inline assembly and mapping symbols (#225129)")
Pull-Request: https://github.com/llvm/llvm-project/pull/226752
Commit: 57721b7c631b3dacc8f59b2467992e3ff4866cc6
https://github.com/llvm/llvm-project/commit/57721b7c631b3dacc8f59b2467992e3ff4866cc6
Author: Lang Hames <lhames at gmail.com>
Date: 2026-09-27 (Sun, 27 Sep 2026)
Changed paths:
M orc-rt/include/CMakeLists.txt
M orc-rt/include/orc-rt-c/config.h.in
A orc-rt/include/orc-rt-c/support/LogLevel.h
M orc-rt/include/orc-rt-c/support/Logging.h
M orc-rt/include/orc-rt/bedrock/Session.h
Log Message:
-----------
[orc-rt] Move ORC_RT_LOG_ENABLED out of config.h; catch typos. (#226751)
Move ORC_RT_LOG_ENABLED to orc-rt-c/support/LogLevel.h so that config.h
is kept for build options only.
Switch to using function-like macros so that typos in level-names become
compilation errors.
Commit: 689040ca0cb30b3f93edb5e51f64333b23e4610f
https://github.com/llvm/llvm-project/commit/689040ca0cb30b3f93edb5e51f64333b23e4610f
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-27 (Sun, 27 Sep 2026)
Changed paths:
M llvm/include/llvm/CodeGen/TargetLoweringObjectFileImpl.h
M llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
M llvm/lib/Target/M68k/M68kTargetObjectFile.cpp
M llvm/lib/Target/M68k/M68kTargetObjectFile.h
Log Message:
-----------
CodeGen: Remove shadowing TargetMachine members from COFF and M68k TLOFs (#226769)
TargetLoweringObjectFile::Initialize already records the TargetMachine
in a base class field.
Co-authored-by: Claude Opus 5 <noreply at anthropic.com>
Commit: 9bf0c497dceba0c7eb882c0f2a96c8151ce74ae3
https://github.com/llvm/llvm-project/commit/9bf0c497dceba0c7eb882c0f2a96c8151ce74ae3
Author: Lang Hames <lhames at gmail.com>
Date: 2026-09-27 (Sun, 27 Sep 2026)
Changed paths:
M orc-rt/include/orc-rt/bedrock/ConnectorRegistry.h
M orc-rt/lib/bedrock/ConnectorRegistry.cpp
M orc-rt/lib/bedrock/sys/posix/SocketConnector.cpp
M orc-rt/test/unit/bedrock/sys/posix/SocketConnectorTest.cpp
M orc-rt/tools/ogre/ogre.cpp
Log Message:
-----------
[orc-rt] Simplify ConnectorRegistry::connect and ogre setup. (#226772)
ConnectorRegistry::connect and ConnectorFn now take the Session and
BootstrapInfo directly, replacing the GetAttachInfo callback and the
AttachInfo struct. The callback let the Session be built lazily, after
the connector had validated its spec, but a connection can fail after
validation anyway, so callers already had to handle discarding a Session
built for a failed connection. Build the Session first, then connect.
ogre's setup is restructured to match: makeSession detects the process
info, builds a thread-pool dispatcher and the Session, adds the host
services, then connects; runOgre waits for the detach. Errors are
reported via Session::logErrors when logging is enabled.
SocketConnectorTest now connects a real Session. Its ownership test
adopts a non-stream socket, which the connector accepts and
createSimpleRemoteCAOverSocket then rejects, rather than relying on a
failing GetAttachInfo.
Commit: 80b46c9d74a868cd20720cc7932a2f88bda43d25
https://github.com/llvm/llvm-project/commit/80b46c9d74a868cd20720cc7932a2f88bda43d25
Author: Letu Ren <fantasquex at gmail.com>
Date: 2026-09-27 (Sun, 27 Sep 2026)
Changed paths:
M clang/test/CIR/CodeGenBuiltins/builtin-nondeterministic-value.c
Log Message:
-----------
[CIR][NFC] Add vector of boolean test to __builtin_nondeterministic_value (#219550)
Assisted-by: grok-4.6
Signed-off-by: Letu Ren <fantasquex at gmail.com>
Commit: dfde6ac69e6e0c5a717042de3fa7f118eea7d830
https://github.com/llvm/llvm-project/commit/dfde6ac69e6e0c5a717042de3fa7f118eea7d830
Author: Mamadou Wane <mamadouswane at gmail.com>
Date: 2026-09-27 (Sun, 27 Sep 2026)
Changed paths:
M clang-tools-extra/clang-tidy/bugprone/RedundantBranchConditionCheck.cpp
M clang-tools-extra/docs/ReleaseNotes.md
M clang-tools-extra/test/clang-tidy/checkers/bugprone/redundant-branch-condition.cpp
Log Message:
-----------
[clang-tidy] Fix redundant-branch-condition false positive in loops (#225827)
Fixes #205685.
`bugprone-redundant-branch-condition` decides whether the condition
variable changes between the outer and inner `if` by comparing source
positions. When a loop sits between the two, a mutation that comes after
the inner `if` in the source still runs before the inner condition is
evaluated again on the next iteration, so the check reports a redundant
condition that isn't, and the fix-it changes behavior.
The fix walks the parents of the inner `if` up to the outer `if` and
finds the outermost enclosing loop. If the variable is mutated anywhere
in that loop, the check does not warn. This follows NagyDonat's
suggestion in the issue: the existing check already covers mutations
between the outer condition and the loop, so only the loop itself needs
the extra query. The walk passes through declarations, so an inner `if`
inside a lambda stored in a variable is handled too, and it stops at the
enclosing function. I chose a syntactic walk instead of the CFG
(`utils::ExprSequence`), since it covers the range the issue asks for
without building a CFG on every match.
Tests cover `for`, `while`, `do`, and range-based `for`, a mutation in a
`do`/`while` condition, a lambda stored in a variable inside the loop,
and an inner loop whose enclosing loop does the mutation. Each of these
warns without the patch. Three positive cases confirm the warning is
kept when the loop never mutates the variable, when the mutation comes
after the loop, and when the loop encloses both `if` statements.
Limitations:
- Any mutation in the loop suppresses the warning, including one
followed by an exit from the loop (`break`, `return`, `throw`) or one
that cannot make the condition false. The inner condition is still
redundant in those cases; telling them apart needs the CFG. I added the
`break` case under Unhandled Cases. The change only removes warnings, so
it adds no new false positives.
- Loops built with `goto` and Objective-C `for ... in` loops are not
recognized, so the false positive remains there.
I used Claude to help write the code. I tested and reviewed all of it
myself, and worked through the approach and suggestions with Claude.
Commit: 719341a64c02261b7b43e4aa6a25f597cca8626d
https://github.com/llvm/llvm-project/commit/719341a64c02261b7b43e4aa6a25f597cca8626d
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-09-27 (Sun, 27 Sep 2026)
Changed paths:
M llvm/include/llvm/Analysis/TargetTransformInfo.h
M llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
M llvm/include/llvm/CodeGen/BasicTTIImpl.h
M llvm/lib/Analysis/TargetTransformInfo.cpp
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
M llvm/test/Analysis/CostModel/AArch64/speculative-load.ll
M llvm/test/Analysis/CostModel/X86/speculative-load.ll
Log Message:
-----------
[TTI] Provide conservative legality + costs for @llvm.speculative.load. (#180036)
Add TTI support for @llvm.speculative.load, including cost and legaltiy
checking support.
The initial implementation for AArch64 checks if the loaded type is
<= 16 bytes, and only considers such cases legal due to MTE.
PR:
https://github.com/llvm/llvm-project/pull/180036
Depends on https://github.com/llvm/llvm-project/pull/179642
Commit: 6909c17f14683203621f5a3d8fbf04dfd5d9c623
https://github.com/llvm/llvm-project/commit/6909c17f14683203621f5a3d8fbf04dfd5d9c623
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-09-27 (Sun, 27 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
M llvm/test/Transforms/ConstraintElimination/analysis-invalidation.ll
Log Message:
-----------
[ConstraintElim] Don't request SCEV if there are no loops. (NFC) (#226736)
ConstraintElimination only uses SCEV when there are any loops. Don't
request the analysis if there are no loops.
This reduces compile-time a bit (more for workloads with large number of
functions w/o loops):
stage1-O3: -0.03%
stage1-ReleaseThinLTO: -0.04%
stage1-ReleaseLTO-g: -0.02%
stage1-aarch64-O3: -0.03%
stage2-O3: -0.04%
stage2-clang: -0.09%
https://llvm-compile-time-tracker.com/compare.php?from=899d817c7950c997402cd229935cd822acf45b08&to=c4453240417d8705b0752c3feda8d02365f8175c&stat=instructions:u
PR: https://github.com/llvm/llvm-project/pull/226736
Commit: 57630fd809ca4964f887dd531e1a09618d962b10
https://github.com/llvm/llvm-project/commit/57630fd809ca4964f887dd531e1a09618d962b10
Author: Chibuoyim (Wilson) Ogbonna <chibuoyim.faith.ogbonna at huawei.com>
Date: 2026-09-27 (Sun, 27 Sep 2026)
Changed paths:
R clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_addv.c
A clang/test/CodeGen/AArch64/sve/addv.c
Log Message:
-----------
[clang][CIR] Add tests for SVE ADDV intrinsics (#225648)
This adds CIR tests for `svaddv` (plain SVE) intrinsics following the
task description in
[223963](https://github.com/llvm/llvm-project/issues/223963).
Moves and adapts `sve-intrinsics/acle_sve_addv.c` to `sve/addv.c`.
Commit: 68fddbbe019b63698e9c4a898b313b9112019cab
https://github.com/llvm/llvm-project/commit/68fddbbe019b63698e9c4a898b313b9112019cab
Author: David Green <david.green at arm.com>
Date: 2026-09-27 (Sun, 27 Sep 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
M llvm/test/CodeGen/AArch64/lowmaskedlanes.ll
Log Message:
-----------
[DAG] Scalarise trivial splat operations (#226257)
This fixes an issue reported on #224255, where a single active lane
masked store is converted to a v1f16 extract_subvector, which becomes a
v1f16 splat, which fails to scalarize. Add the necessary trivial
scalarisation of the splat by using the f16 input operand.
(I was originally going to fix this by generating a scalar f16 extract
directly (which would have the benefit of treating f16 as legal), but
that seems to cause a regression in 2 x86 tests).
Commit: 6b51046ae30cd78fc4b26605e2dcf3b70c282f4c
https://github.com/llvm/llvm-project/commit/6b51046ae30cd78fc4b26605e2dcf3b70c282f4c
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-09-27 (Sun, 27 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
A llvm/test/Transforms/SLPVectorizer/X86/narrowed-reduction-gathered-leftover-leaf.ll
Log Message:
-----------
[SLP]Fix erasing gathered leftover narrowed reduction leaves
A leftover narrowed reduction leaf, only gathered in the tree, loses all
users once the tree scalars are erased and is swept as a dead operand,
though the reduction epilogue still uses it. Keep such values alive.
Fixes https://github.com/llvm/llvm-project/pull/224919#issuecomment-5855368565
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/226782
Commit: a9407d59c4abfb8bf49da7dfcec6775707288b9e
https://github.com/llvm/llvm-project/commit/a9407d59c4abfb8bf49da7dfcec6775707288b9e
Author: Nico Weber <thakis at chromium.org>
Date: 2026-09-27 (Sun, 27 Sep 2026)
Changed paths:
M libcxx/include/__ostream/print.h
Log Message:
-----------
[libc++] Port #200996 to ostream (#226372)
Reduces the time to compile a TU with just `#include <ostream>` from
254.7 ms ± 3.0 ms to 227.7 ms ± 2.1 ms on my system (-std=c++23, -O2,
arm64 macOS).
See #195466 for details. Without this, the call is evaluated when the
template is parsed, which evaluates format_string's consteval
constructor for "\n" in every translation unit that includes <ostream>,
even if nothing calls println().
No behavior change.
Commit: 14df65f5db67d0096ef2360abb1e30891dae66b5
https://github.com/llvm/llvm-project/commit/14df65f5db67d0096ef2360abb1e30891dae66b5
Author: Leonidas Spyropoulos <artafinde at gmail.com>
Date: 2026-09-27 (Sun, 27 Sep 2026)
Changed paths:
M libcxx/include/__chrono/duration.h
M libcxx/test/std/time/months.pass.cpp
M libcxx/test/std/time/years.pass.cpp
Log Message:
-----------
[libc++][chrono] Fix years/months periods on GCC/i386 (#223669)
`static_cast<int>(365.2425 * 60 * 60 * 24)`, added in
f537b4e51822b19780386e0575ff95e82f8ec445, isn't exactly 31556952 on
every host: GCC targeting i386 folds it in x87 extended precision and
gets 31556951, making `years::period` and `months::period` coprime and
breaking `year_month` arithmetic.
Use the literal values instead, there's no readability to lose since
they were only there to avoid a template instantiation in the first
place.
Signed-off-by: Leonidas Spyropoulos <artafinde at archlinux.org>
Commit: 0b401e859b9fec54231b11ffb39085ea02e053c0
https://github.com/llvm/llvm-project/commit/0b401e859b9fec54231b11ffb39085ea02e053c0
Author: Kazu Hirata <kazu at google.com>
Date: 2026-09-27 (Sun, 27 Sep 2026)
Changed paths:
M llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp
M llvm/lib/Target/PowerPC/PPC.h
M llvm/tools/dsymutil/DwarfLinkerForBinary.h
M llvm/tools/llvm-cov/CodeCoverage.cpp
M llvm/tools/llvm-objdump/COFFDump.h
M llvm/tools/llvm-objdump/ELFDump.h
M llvm/tools/llvm-objdump/OffloadDump.cpp
M llvm/tools/llvm-objdump/WasmDump.h
M llvm/tools/llvm-profgen/PerfReader.h
Log Message:
-----------
[llvm] Remove declarations without definitions (NFC) (#226764)
HexagonConstEvaluator::evaluateHexVector2: Added on July 28, 2016 in
commit 167d918225ecd05a63f6b8d449c317feda741e18 without a definition or
any callers.
initializePPCExpandISELPass: The definition and caller were removed on
August 27, 2024 in commit 8e901c255df45e38cb1d69a576804029e20868bf.
dsymutil::DwarfLinkerForBinary::createStreamer: The definition and
caller were removed on April 1, 2023 in commit
36f351098cd50809658493d9b2e22a795874bab0 (when the non-template
declaration in DwarfLinkerForBinary.h was replaced with a template
declaration without a definition).
exportCoverageDataToJson: The definition and caller were replaced with
CoverageExporterJson on January 4, 2018 in commit
1ef3a778ac47564aa5a7f04bbf572d22d1c616fb.
objdump::printCOFFFileHeader, objdump::printELFFileHeader, and
objdump::printWasmFileHeader: The definitions and callers were replaced
with Dumper::printPrivateHeaders on July 14, 2023 in commit
0af663f80da0009f6fd879cf4d41743d4c88a2db.
disassembleObject: Added on May 23, 2025 in commit
51a03ed27282166d418399f2ade9814ea5be9944 without a definition or any
callers.
sampleprof::VirtualUnwinder::recordRangeCount: The definition and
callers were removed on January 11, 2021 in commit
3869309a0c92735228afaa5663d1c10bb372bb54.
Assisted-by: Antigravity
Commit: 1345a4fa8d60bdd33d59b7a1c0613eaef7d8e01f
https://github.com/llvm/llvm-project/commit/1345a4fa8d60bdd33d59b7a1c0613eaef7d8e01f
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-09-27 (Sun, 27 Sep 2026)
Changed paths:
A llvm/test/Transforms/SLPVectorizer/X86/extracted-subfields-shifted-trunc.ll
Log Message:
-----------
[SLP][NFC]Add an extra test witj missing vectorization, NFC
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/226802
Commit: 0f5a125bad555b6bf4bb2318b9f1ea7936adf19d
https://github.com/llvm/llvm-project/commit/0f5a125bad555b6bf4bb2318b9f1ea7936adf19d
Author: Reid Kleckner <rkleckner at nvidia.com>
Date: 2026-09-27 (Sun, 27 Sep 2026)
Changed paths:
A libcxx/docs/ABIGuarantees.md
R libcxx/docs/ABIGuarantees.rst
A libcxx/docs/AddingNewCIJobs.md
R libcxx/docs/AddingNewCIJobs.rst
A libcxx/docs/CodingGuidelines.md
R libcxx/docs/CodingGuidelines.rst
A libcxx/docs/Contributing.md
R libcxx/docs/Contributing.rst
A libcxx/docs/Contributing/NewStandardProcedure.md
R libcxx/docs/Contributing/NewStandardProcedure.rst
A libcxx/docs/Contributing/PostMeetingProcedure.md
R libcxx/docs/Contributing/PostMeetingProcedure.rst
A libcxx/docs/Contributing/ReleaseProcedure.md
R libcxx/docs/Contributing/ReleaseProcedure.rst
A libcxx/docs/DesignDocs/ABIVersioning.md
R libcxx/docs/DesignDocs/ABIVersioning.rst
A libcxx/docs/DesignDocs/AtomicDesign.md
R libcxx/docs/DesignDocs/AtomicDesign.rst
A libcxx/docs/DesignDocs/CapturingConfigInfo.md
R libcxx/docs/DesignDocs/CapturingConfigInfo.rst
A libcxx/docs/DesignDocs/ExperimentalFeatures.md
R libcxx/docs/DesignDocs/ExperimentalFeatures.rst
A libcxx/docs/DesignDocs/ExtendedCXX03Support.md
R libcxx/docs/DesignDocs/ExtendedCXX03Support.rst
A libcxx/docs/DesignDocs/FeatureTestMacros.md
R libcxx/docs/DesignDocs/FeatureTestMacros.rst
A libcxx/docs/DesignDocs/FileTimeType.md
R libcxx/docs/DesignDocs/FileTimeType.rst
A libcxx/docs/DesignDocs/HeaderRemovalPolicy.md
R libcxx/docs/DesignDocs/HeaderRemovalPolicy.rst
M libcxx/include/__configuration/abi.h
Log Message:
-----------
[libc++][docs] Rename documentation files to Markdown (batch 1) (#221512)
Tracking issue: #201242
See the [migration guide] for more information.
[migration guide]:
https://llvm.org/docs/SphinxQuickstartTemplate.html#markdown-migration-guidelines
This is the initial straight rename commit. It will probably break the
docs build, but it has to be a separate PR for blame preservation
purposes.
Commit: 61b428e0edfe674b84d77f7b55aa687fce3b501e
https://github.com/llvm/llvm-project/commit/61b428e0edfe674b84d77f7b55aa687fce3b501e
Author: Reid Kleckner <rkleckner at nvidia.com>
Date: 2026-09-27 (Sun, 27 Sep 2026)
Changed paths:
M libcxx/docs/ABIGuarantees.md
M libcxx/docs/AddingNewCIJobs.md
M libcxx/docs/CodingGuidelines.md
M libcxx/docs/Contributing.md
M libcxx/docs/Contributing/NewStandardProcedure.md
M libcxx/docs/Contributing/PostMeetingProcedure.md
M libcxx/docs/Contributing/ReleaseProcedure.md
M libcxx/docs/DesignDocs/ABIVersioning.md
M libcxx/docs/DesignDocs/AtomicDesign.md
M libcxx/docs/DesignDocs/CapturingConfigInfo.md
M libcxx/docs/DesignDocs/ExperimentalFeatures.md
M libcxx/docs/DesignDocs/ExtendedCXX03Support.md
M libcxx/docs/DesignDocs/FeatureTestMacros.md
M libcxx/docs/DesignDocs/FileTimeType.md
M libcxx/docs/DesignDocs/HeaderRemovalPolicy.md
M libcxx/docs/conf.py
Log Message:
-----------
[libc++][docs] Convert documentation from reST to Markdown (batch 1) (#221513)
This is the first batch of changes to migrate libc++ documentation from
rst to markdown.
I use a local pixel diff tool to compare the rendered HTML, and all
diffs seem like fixes. They tend to fall into the following categories:
- dashed bullet lists were previously not rendered, but now they are
- extra indentation interpreted as blockquotes has been removed
- single backticks are now codefont spans, not italic spans
Tracking issue: #201242
See the [migration guide] for more information.
[migration guide]:
https://llvm.org/docs/SphinxQuickstartTemplate.html#markdown-migration-guidelines
This is a stacked PR based on #221512, which will be a standalone commit
that
renames *.rst -> *.md before this PR lands for history preservation
purposes.
-----
Before/after validation links:
| Source file | Before HTML | After HTML |
| --- | --- | --- |
| `libcxx/docs/ABIGuarantees.md` |
[before](https://llvmdocs.staging.reidkleckner.dev/before/libcxx/docs/ABIGuarantees.html)
|
[after](https://llvmdocs.staging.reidkleckner.dev/after/libcxx/docs/ABIGuarantees.html)
|
| `libcxx/docs/AddingNewCIJobs.md` |
[before](https://llvmdocs.staging.reidkleckner.dev/before/libcxx/docs/AddingNewCIJobs.html)
|
[after](https://llvmdocs.staging.reidkleckner.dev/after/libcxx/docs/AddingNewCIJobs.html)
|
| `libcxx/docs/CodingGuidelines.md` |
[before](https://llvmdocs.staging.reidkleckner.dev/before/libcxx/docs/CodingGuidelines.html)
|
[after](https://llvmdocs.staging.reidkleckner.dev/after/libcxx/docs/CodingGuidelines.html)
|
| `libcxx/docs/Contributing/NewStandardProcedure.md` |
[before](https://llvmdocs.staging.reidkleckner.dev/before/libcxx/docs/Contributing/NewStandardProcedure.html)
|
[after](https://llvmdocs.staging.reidkleckner.dev/after/libcxx/docs/Contributing/NewStandardProcedure.html)
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| `libcxx/docs/Contributing/PostMeetingProcedure.md` |
[before](https://llvmdocs.staging.reidkleckner.dev/before/libcxx/docs/Contributing/PostMeetingProcedure.html)
|
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|
| `libcxx/docs/Contributing/ReleaseProcedure.md` |
[before](https://llvmdocs.staging.reidkleckner.dev/before/libcxx/docs/Contributing/ReleaseProcedure.html)
|
[after](https://llvmdocs.staging.reidkleckner.dev/after/libcxx/docs/Contributing/ReleaseProcedure.html)
|
| `libcxx/docs/Contributing.md` |
[before](https://llvmdocs.staging.reidkleckner.dev/before/libcxx/docs/Contributing.html)
|
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[before](https://llvmdocs.staging.reidkleckner.dev/before/libcxx/docs/DesignDocs/ABIVersioning.html)
|
[after](https://llvmdocs.staging.reidkleckner.dev/after/libcxx/docs/DesignDocs/ABIVersioning.html)
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| `libcxx/docs/DesignDocs/AtomicDesign.md` |
[before](https://llvmdocs.staging.reidkleckner.dev/before/libcxx/docs/DesignDocs/AtomicDesign.html)
|
[after](https://llvmdocs.staging.reidkleckner.dev/after/libcxx/docs/DesignDocs/AtomicDesign.html)
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[before](https://llvmdocs.staging.reidkleckner.dev/before/libcxx/docs/DesignDocs/CapturingConfigInfo.html)
|
[after](https://llvmdocs.staging.reidkleckner.dev/after/libcxx/docs/DesignDocs/CapturingConfigInfo.html)
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| `libcxx/docs/DesignDocs/ExperimentalFeatures.md` |
[before](https://llvmdocs.staging.reidkleckner.dev/before/libcxx/docs/DesignDocs/ExperimentalFeatures.html)
|
[after](https://llvmdocs.staging.reidkleckner.dev/after/libcxx/docs/DesignDocs/ExperimentalFeatures.html)
|
| `libcxx/docs/DesignDocs/ExtendedCXX03Support.md` |
[before](https://llvmdocs.staging.reidkleckner.dev/before/libcxx/docs/DesignDocs/ExtendedCXX03Support.html)
|
[after](https://llvmdocs.staging.reidkleckner.dev/after/libcxx/docs/DesignDocs/ExtendedCXX03Support.html)
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| `libcxx/docs/DesignDocs/FeatureTestMacros.md` |
[before](https://llvmdocs.staging.reidkleckner.dev/before/libcxx/docs/DesignDocs/FeatureTestMacros.html)
|
[after](https://llvmdocs.staging.reidkleckner.dev/after/libcxx/docs/DesignDocs/FeatureTestMacros.html)
|
| `libcxx/docs/DesignDocs/FileTimeType.md` |
[before](https://llvmdocs.staging.reidkleckner.dev/before/libcxx/docs/DesignDocs/FileTimeType.html)
|
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|
Commit: 6cff1c56d1678e3d7eb70650d1fe138eac80c05e
https://github.com/llvm/llvm-project/commit/6cff1c56d1678e3d7eb70650d1fe138eac80c05e
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-09-27 (Sun, 27 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPUtils.cpp
M llvm/test/Transforms/SLPVectorizer/X86/extracted-subfields-shifted-trunc.ll
Log Message:
-----------
[SLP]Look through truncation of shifted extracted sub-fields
The masked sub-field of the shifted truncation of a wider scalar was
matched with the truncation as its source, while the other fields
matched the scalar itself, so the gather of the fields was rejected.
The field is within the truncated bits, look through the truncation.
Fixes #74380
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/226803
Commit: 20bbd88cf9e7be286b25c29c877c2d0564da9ecf
https://github.com/llvm/llvm-project/commit/20bbd88cf9e7be286b25c29c877c2d0564da9ecf
Author: Guy David <guyda96 at gmail.com>
Date: 2026-09-27 (Sun, 27 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Utils/SimplifyCFG.cpp
A llvm/test/Transforms/SimplifyCFG/AArch64/speculate-vector-phi-select-cost.ll
A llvm/test/Transforms/SimplifyCFG/ARM/speculate-vector-phi-select-cost.ll
A llvm/test/Transforms/SimplifyCFG/RISCV/speculate-mask-phi-select-cost.ll
A llvm/test/Transforms/SimplifyCFG/X86/speculate-mask-phi-select-cost.ll
Log Message:
-----------
[SimplifyCFG] Cost speculated selects with their real scalar condition (#217664)
`validateAndCostRequiredSelects()` priced the selects that
`speculativelyExecuteBB()` would create using
`CmpInst::makeCmpResultType(PN->getType())` as the condition type. For a
vector phi, that asks the target for the cost of a per-lane vector
select, but the select actually created uses the branch condition, which
is always a scalar `i1`.
This only changes behaviour where a target's cost model distinguishes
the two condition types. Of the targets checked, only AArch64 does.
This may worsen the compiler's output in RISC-V, X86, ARM, so no
intention to merge soon before collecting more feedback on how the
different targets should communicate this property.
Commit: f8cfaa7dc0caf6bd51b82798718c51ac3fd68c12
https://github.com/llvm/llvm-project/commit/f8cfaa7dc0caf6bd51b82798718c51ac3fd68c12
Author: Jake Egan <Jake.egan at ibm.com>
Date: 2026-09-27 (Sun, 27 Sep 2026)
Changed paths:
M libcxx/test/configs/ibm-libc++-shared.cfg.in
Log Message:
-----------
[libc++][AIX] Add system library path via blibpath for lldb (#223837)
On AIX some tools we use for testing libc++, like lldb, are linked
against the system libc++, which has additional members (e.g
`shr2_64.o`) that the newly built libc++.a doesn't have. But the current
test harness set the `LIBPATH` to point at the newly built libc++, which
can load break these tools.
This change removes the `LIBPATH` and instead sets the `blibpath`
(equivalent to rpath on other systems), which helps lldb find the system
libc++.a, while still running the tests against the libc++ build under
test.
Commit: db9f06ce021c54523afc8bf9d0cfe45aba2eba09
https://github.com/llvm/llvm-project/commit/db9f06ce021c54523afc8bf9d0cfe45aba2eba09
Author: Fangrui Song <i at maskray.me>
Date: 2026-09-27 (Sun, 27 Sep 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64CodeLayoutOpt.cpp
M llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp
Log Message:
-----------
Remove cl::callback from AArch64CodeLayoutOpt and AddressSanitizer (#226757)
cl::callback will be removed to enable migration to TableGen based
representation
LLM-aided
Commit: 8e6f2603dc5d4a93400aa8ba28ea624644be0c9a
https://github.com/llvm/llvm-project/commit/8e6f2603dc5d4a93400aa8ba28ea624644be0c9a
Author: Fangrui Song <i at maskray.me>
Date: 2026-09-27 (Sun, 27 Sep 2026)
Changed paths:
M llvm/include/llvm/ADT/DenseMap.h
M llvm/include/llvm/ADT/DenseMapInfo.h
M llvm/lib/Support/CMakeLists.txt
A llvm/lib/Support/DenseMap.cpp
M llvm/unittests/ADT/DenseMapTest.cpp
M llvm/utils/gn/secondary/llvm/lib/Support/BUILD.gn
Log Message:
-----------
[DenseMap] Share rehash and grow for relocatable bucket types. NFC (#225018)
DenseMap is heavily instantiated and moveFrom and grow are among the
largest code families. For trivially copy constructible and destructible
bucket types (also satisfied by std::pair), call an out-of-line
`growRelocatable` with size/align/hasher (dictionary passing style).
A pointer key hashed by its value hashes inline, which a null
BucketHasher asks for, sparing a call per entry.
DenseMapInfo<T *>::PointerValueHash names the class declaring it, so an
info that specializes or inherits it to hash the pointee -- Attributor's
InstExclusionSet, VPCSEDenseMapInfo, MachineInstrExpressionTrait --
keeps its own hash. Any other key hashes through a thunk, one per
(KeyT, KeyInfoT) whatever the map's value type.
SmallDenseMap's in-place rehash for remove_if shares the loop through
`rehashRelocatable`. It rehashes once rather than into a temporary map
and back, which can reorder a probe chain that wraps around the table.
Building clang takes 0.86% fewer instructions and the binary is 0.64%
smaller.
Aided by Opus 5
Commit: 9e44a6664500bcc01fb9ddc35710b4d0fd748b06
https://github.com/llvm/llvm-project/commit/9e44a6664500bcc01fb9ddc35710b4d0fd748b06
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-09-27 (Sun, 27 Sep 2026)
Changed paths:
M llvm/test/Transforms/SLPVectorizer/X86/extracted-subfields.ll
Log Message:
-----------
[SLP][NFC]Add extra tests with incorrect vectorization, NFC
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/226827
Commit: eea552937b1e30c8b74bf3748cccab1357dd0d57
https://github.com/llvm/llvm-project/commit/eea552937b1e30c8b74bf3748cccab1357dd0d57
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-09-27 (Sun, 27 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/X86/extracted-subfields.ll
Log Message:
-----------
[SLP]Fix reused scales for sub-fields gathered in natural order
The reduction root sub-fields were emitted in the natural order, but the
reused values were scaled by the original lane order. Reorder the root
scalars instead.
Fixes https://github.com/llvm/llvm-project/pull/224919#issuecomment-5858504241
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/226828
Commit: d0ea8a8e46091f71684091f48412ce500165d76f
https://github.com/llvm/llvm-project/commit/d0ea8a8e46091f71684091f48412ce500165d76f
Author: Martin Storsjö <martin at martin.st>
Date: 2026-09-27 (Sun, 27 Sep 2026)
Changed paths:
M llvm/unittests/Support/LLVMToolSession/LLVMToolSessionTest.cpp
Log Message:
-----------
[unittests] Fix a recent test on Windows with LLVM_WINDOWS_PREFER_FORWARD_SLASH (#224963)
This fixes errors like these:
```
Expected equality of these values:
Context.Path
Which is: "D:/a/llvm-mingw/llvm-mingw/llvm-project/build/unittests/Support/LLVMToolSession/./LLVMToolSessionTests.exe"
ExecutablePath.c_str()
Which is: "D:\\a\\llvm-mingw\\llvm-mingw\\llvm-project\\build\\unittests\\Support\\LLVMToolSession\\.\\LLVMToolSessionTests.exe"
```
Commit: df7a21f8210426653d12c50475651c4d7518b804
https://github.com/llvm/llvm-project/commit/df7a21f8210426653d12c50475651c4d7518b804
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-09-27 (Sun, 27 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.h
Log Message:
-----------
[LV] Remove EpilogueLoopVectorizationInfo::EpilogueUF (NFC). (#226792)
The epilogue vector loop is always unrolled by 1: the only construction
site passes 1 and the constructor asserted it. Drop the field and use 1
directly at its users, and drop the now always 1 EpilogueUF parameter of
addMinimumVectorEpilogueIterationCheck.
Clean-up in preparation for removing/simplifying
EpilogueLoopVectorizationInfo.
Commit: d8b43a8db3cd5314e5c9cc51af04fca342715187
https://github.com/llvm/llvm-project/commit/d8b43a8db3cd5314e5c9cc51af04fca342715187
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-27 (Sun, 27 Sep 2026)
Changed paths:
M llvm/lib/Target/Mips/MipsAsmPrinter.cpp
M llvm/lib/Target/Mips/MipsSubtarget.cpp
M llvm/lib/Target/Mips/MipsSubtarget.h
M llvm/lib/Target/Mips/MipsTargetMachine.cpp
M llvm/lib/Target/Mips/MipsTargetMachine.h
A llvm/test/CodeGen/Mips/target-abi-module-flag.ll
Log Message:
-----------
Mips: Properly account for target-abi in subtarget construction (#226721)
Commit: 5ad4959a040a6e31eba7ab46f3bf4fd41cd224dc
https://github.com/llvm/llvm-project/commit/5ad4959a040a6e31eba7ab46f3bf4fd41cd224dc
Author: Kazu Hirata <kazu at google.com>
Date: 2026-09-27 (Sun, 27 Sep 2026)
Changed paths:
M clang/include/clang/AST/ASTContext.h
M clang/include/clang/AST/NestedNameSpecifierBase.h
M clang/lib/AST/NestedNameSpecifier.cpp
Log Message:
-----------
[clang] Unique NamespaceAndPrefixStorages with a UniquingSet (NFC) (#224221)
This patch migrates NamespaceAndPrefixStorages in ASTContext from
llvm::FoldingSet to llvm::UniquingSet.
NamespaceAndPrefixStorage keys on a pair of const NamespaceBaseDecl *
and NestedNameSpecifier. Switching to UniquingSet allows us to look
up storages with a typed key, eliminating FoldingSetNodeID
serialization at lookup sites and removing
NamespaceAndPrefixStorage::Profile.
Assisted-by: Antigravity
Commit: 15eef1398e36befcaaf6cc19872805f6eb3ae5a4
https://github.com/llvm/llvm-project/commit/15eef1398e36befcaaf6cc19872805f6eb3ae5a4
Author: Lang Hames <lhames at gmail.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M llvm/include/llvm/ExecutionEngine/Orc/Debugging/PerfSupportPlugin.h
M llvm/include/llvm/ExecutionEngine/Orc/Debugging/VTuneSupportPlugin.h
M llvm/lib/ExecutionEngine/Orc/Debugging/PerfSupportPlugin.cpp
M llvm/lib/ExecutionEngine/Orc/Debugging/VTuneSupportPlugin.cpp
Log Message:
-----------
[ORC] Call Perf/VTune support wrappers through Proxies (#226677)
Hold PerfSupportPlugin's start/end registration wrappers and
VTuneSupportPlugin's unregister wrapper as Proxy members, replacing
their callSPSWrapper calls. Each proxy is built in the constructor from
the address it already takes, so the constructor signatures are
unchanged. The Perf impl and VTune register wrappers are only used as
alloc-action tags and stay ExecutorAddrs.
Commit: dbde1428562362792d85cb9bbb58415f1b21cb48
https://github.com/llvm/llvm-project/commit/dbde1428562362792d85cb9bbb58415f1b21cb48
Author: Jared Wyles <jared.wyles at gmail.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M orc-rt/test/regression/jit-free-foundations/check-rt-process-info.test
M orc-rt/test/regression/lit.cfg.py
Log Message:
-----------
[orc-rt] Fixing linux tests to enable CI (#226766)
Commit: a432c764f54c72f60bb1c2df0c050e5cc29db2dd
https://github.com/llvm/llvm-project/commit/a432c764f54c72f60bb1c2df0c050e5cc29db2dd
Author: Ben Shi <2283975856 at qq.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M llvm/lib/Target/X86/X86RegisterInfo.td
Log Message:
-----------
[X86][NFC] Simplify definition of TMM registers (#226779)
Commit: 6c75b015778cdb22d688d6c6f6e40ccb6d9eb352
https://github.com/llvm/llvm-project/commit/6c75b015778cdb22d688d6c6f6e40ccb6d9eb352
Author: Letu Ren <fantasquex at gmail.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/LLVMIntrinsicOps.td
M mlir/test/Dialect/LLVMIR/roundtrip.mlir
M mlir/test/Target/LLVMIR/Import/intrinsic.ll
M mlir/test/Target/LLVMIR/llvmir-intrinsics.mlir
Log Message:
-----------
[mlir][LLVM] Add smulh and umulh intrinsics. (#226776)
Assisted-by: grok-4.7
Signed-off-by: Letu Ren <fantasquex at gmail.com>
Commit: cef4b65cbd0d960b7ab8aa19654be28f5a5f830e
https://github.com/llvm/llvm-project/commit/cef4b65cbd0d960b7ab8aa19654be28f5a5f830e
Author: Harrison Hao <57025411+harrisonGPU at users.noreply.github.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
M llvm/test/Transforms/InstCombine/AMDGPU/llvm.amdgcn.dot.ll
Log Message:
-----------
[AMDGPU][InstCombine] Fold zero dot operands to accumulator (#225003)
Fold AMDGPU dot intrinsics when either operand is zero.
`dot(a, 0) = 0` and `dot(0, b) = 0`, so replace the intrinsic with its
accumulator.
This avoids unrelated clamp and add/sub reassociation cases.
Commit: 373c54d763c98487df27599247412f80d933e177
https://github.com/llvm/llvm-project/commit/373c54d763c98487df27599247412f80d933e177
Author: Lang Hames <lhames at gmail.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M orc-rt/test/regression/jit-free-foundations/check-rt-process-info.test
M orc-rt/test/tools/orc-rt-process-info-check.cpp
Log Message:
-----------
[orc-rt] Prefix test tool output, update test. (#226862)
Prefix the triple, page-size, and cpu-features lines of the
orc-rt-process-info-check. The prefixes can be used to ensure that the
test doesn't try to match patterns against the wrong lines.
Also relaxes the feature string check to allow an empty feature string.
Commit: 795457f653fb5e9f769678ed025ecb63d7bfbf53
https://github.com/llvm/llvm-project/commit/795457f653fb5e9f769678ed025ecb63d7bfbf53
Author: Fangrui Song <i at maskray.me>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M llvm/include/llvm/BinaryFormat/ELF.h
M llvm/include/llvm/Object/ELFTypes.h
M llvm/lib/MC/ELFObjectWriter.cpp
Log Message:
-----------
[MC] Add ELF::getSymbolInfo and fix bitwise OR between enumeration types. NFC (#226860)
`ELF::STT_FILE | ELF::STB_LOCAL` puts the binding in the type bits,
which only works because STB_LOCAL is 0.
It combines enumerators from two distinct unnamed enums, which is
deprecated in C++20 and ill-formed in C++26 (P2864R2).
Commit: d34c0c8bdcd3c718eb1f4b125a44bd3863dd3ef6
https://github.com/llvm/llvm-project/commit/d34c0c8bdcd3c718eb1f4b125a44bd3863dd3ef6
Author: Lang Hames <lhames at gmail.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M orc-rt/test/regression/jit-free-foundations/check-rt-process-info.test
M orc-rt/test/regression/lit.cfg.py
Log Message:
-----------
[orc-rt] Rename os-version substitution. (#226863)
This substitution is available and being tested on all platforms. It's
currently only populated on Darwin, but may be useful on other
platforms, so rename it to reflect its role.
Commit: 372dc97670f7b3ce422dc26e5f626b2711426e8d
https://github.com/llvm/llvm-project/commit/372dc97670f7b3ce422dc26e5f626b2711426e8d
Author: ykiko <ykiko at clice.io>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M libcxx/include/__format/buffer.h
A libcxx/test/std/utilities/format/format.functions/bug_154670.pass.cpp
Log Message:
-----------
[libc++][format] Don't leave the output buffer full after a bulk write (#226791)
__output_buffer::push_back writes a code unit before it makes room, so
the buffer must always have a free one. __copy, __transform and __fill
write in chunks of the available space and could end with the buffer
full. Formatting into a back_insert_iterator of a string, vector or
deque goes through a 256 code unit buffer, so an argument or fill whose
length is a multiple of 256, followed by a literal, wrote that literal
past the end of the buffer.
Make room in a full buffer at the end of these functions, as push_back
does.
Fixes #154670
Commit: 6bc9070d58e6b1396f380fcc48234e49ede900f8
https://github.com/llvm/llvm-project/commit/6bc9070d58e6b1396f380fcc48234e49ede900f8
Author: Nico Weber <thakis at chromium.org>
Date: 2026-09-27 (Sun, 27 Sep 2026)
Changed paths:
M clang/lib/Sema/SemaOverload.cpp
Log Message:
-----------
[clang] clang-format two constructors (#226737)
I'd like to change these two in a patch, and the diff looks a bit
confusing since they aren't formatted yet. So format them in a prep
commit to make the diff clearer.
No behavior change.
Commit: af39a0147d97320ccf9de1ca4a58f92a519ecbff
https://github.com/llvm/llvm-project/commit/af39a0147d97320ccf9de1ca4a58f92a519ecbff
Author: Nico Weber <thakis at chromium.org>
Date: 2026-09-27 (Sun, 27 Sep 2026)
Changed paths:
M llvm/utils/gn/secondary/clang/lib/ScalableStaticAnalysis/Analyses/BUILD.gn
M llvm/utils/gn/secondary/clang/unittests/ScalableStaticAnalysis/BUILD.gn
Log Message:
-----------
[gn build] Port ea0493b90c03 (#226870)
Commit: 3e36b024db71848df98de3124953316c49dd9131
https://github.com/llvm/llvm-project/commit/3e36b024db71848df98de3124953316c49dd9131
Author: Nico Weber <thakis at chromium.org>
Date: 2026-09-27 (Sun, 27 Sep 2026)
Changed paths:
M llvm/utils/gn/secondary/libcxx/include/BUILD.gn
Log Message:
-----------
[gn build] Port 7e91ef5d6aea (#226869)
Commit: fb720063a6a01d1d31c8ac1b9318e5259110be58
https://github.com/llvm/llvm-project/commit/fb720063a6a01d1d31c8ac1b9318e5259110be58
Author: Lang Hames <lhames at gmail.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M orc-rt/test/regression/README.md
M orc-rt/test/regression/jit-free-foundations/lit.local.cfg
M orc-rt/test/regression/languages/c/lit.local.cfg
M orc-rt/test/regression/languages/c/return-zero.c
M orc-rt/test/regression/lit.cfg.py
M orc-rt/test/regression/object-formats/lit.local.cfg
M orc-rt/test/regression/object-formats/mach-o/arm64/return-zero.s
Log Message:
-----------
[orc-rt] Rename lit %{jit} substitution to %{obj-jit}. (#226867)
This substitution jit-loads object files via llvm-jitlink. Future tests,
e.g. for lazy compilation, may want to JIT from other representations
and will need different substitutions. Rename now to make the intent
clear and save us renaming later.
Commit: c52392a6f464e5aa6bff198e4056ca58e43e0656
https://github.com/llvm/llvm-project/commit/c52392a6f464e5aa6bff198e4056ca58e43e0656
Author: aokblast <aokblast at FreeBSD.org>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/Interp.h
M clang/lib/AST/ByteCode/Opcodes.td
M clang/lib/AST/ExprConstant.cpp
A clang/test/SemaCXX/new-nothrow-by-value.cpp
Log Message:
-----------
[Clang][ExprConst] Drop PRValue for nothrow new (#226753)
A user defined operator new can accept prvalue for nothrow. However, it
should not be a ConstExpr. Early returns by
isUsableAsGlobalAllocationFunctionInConstantEvaluation instead of doing
LValue evaluation.
Also, move CheckPlacement new logic into new OpCode. This decouples
checking from Interp.cpp to Compiler.cpp.
Commit: b1f5907d79d1d52ca5e938875ca4018ed6fb8bd7
https://github.com/llvm/llvm-project/commit/b1f5907d79d1d52ca5e938875ca4018ed6fb8bd7
Author: Lang Hames <lhames at gmail.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M llvm/tools/llvm-jitlink/llvm-jitlink.cpp
Log Message:
-----------
[llvm-jitlink] Call __orc_rt_run_program_wrapper through a Proxy (#226859)
Replace runWithRuntime's callSPSWrapper call with a Proxy.
Commit: bebb7fe62f8883d822f084687cfb84c5cfe12bbb
https://github.com/llvm/llvm-project/commit/bebb7fe62f8883d822f084687cfb84c5cfe12bbb
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M clang/include/clang/AST/APValue.h
M clang/include/clang/AST/CharUnits.h
M clang/lib/AST/APValue.cpp
M clang/lib/AST/ASTContext.cpp
M clang/lib/AST/ExprConstant.cpp
Log Message:
-----------
[clang][NFC] Pass/Return `CharUnits` by value (#226115)
`CharUnits` is just an `int64_t`, but passed around by const reference
for some reason.
Also update the `CharUnits` documentation since we touch most of the
lines anyway (due to clang-format).
Commit: b1f66905515904d048c9c53e92b1c0d2423aca19
https://github.com/llvm/llvm-project/commit/b1f66905515904d048c9c53e92b1c0d2423aca19
Author: Sairudra More <sairudra60 at gmail.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M flang/docs/OpenMPSupport.md
M flang/lib/Lower/OpenMP/OpenMP.cpp
A flang/test/Integration/OpenMP/allocate-clause-equivalence.f90
A flang/test/Integration/OpenMP/scope-allocate-clause.f90
M flang/test/Lower/OpenMP/Todo/allocate-clause-unsupported.f90
A flang/test/Lower/OpenMP/Todo/scope-allocate-clause-unsupported.f90
M flang/test/Lower/OpenMP/scope.f90
M flang/test/Lower/OpenMP/target-scope.f90
M mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
M mlir/test/Dialect/OpenMP/invalid.mlir
M mlir/test/Dialect/OpenMP/ops.mlir
M mlir/test/Target/LLVMIR/openmp-allocate-clause.mlir
A mlir/test/Target/LLVMIR/openmp-scope-allocate-clause.mlir
M mlir/test/Target/LLVMIR/openmp-todo.mlir
Log Message:
-----------
[flang][OpenMP] Support allocate clauses on scope constructs (#221229)
Flang already lowers OpenMP 5.2 `allocate` clauses on `scope` constructs
to `omp.scope`, but LLVM IR translation previously rejected them.
This change maps allocation operands to their corresponding private or
firstprivate slots and reuses the existing allocator-backed
private-storage and OpenMPIRBuilder allocation/free paths.
Support is currently limited to host-side fixed-size intrinsic scalar
private and firstprivate variables, including SAVE variables and
individually listed COMMON-block members. Arrays, descriptors, pointers,
allocatables, derived types, named COMMON-block list items, and
target/device allocation remain unsupported.
Commit: a98dcad4fed01b7d1d2f3a5306a30d658059c431
https://github.com/llvm/llvm-project/commit/a98dcad4fed01b7d1d2f3a5306a30d658059c431
Author: Kazu Hirata <kazu at google.com>
Date: 2026-09-27 (Sun, 27 Sep 2026)
Changed paths:
M llvm/include/llvm/ADT/DenseMap.h
M llvm/utils/LLVMVisualizers/llvm.natvis
M llvm/utils/gdb-scripts/prettyprinters.py
M llvm/utils/lldbDataFormatters.py
Log Message:
-----------
[ADT] Extract DenseMapStorage from DenseMap (NFC) (#226664)
This patch extracts the bucket and occupancy storage management from
DenseMap into a new helper class, densemap::detail::DenseMapStorage,
and updates DenseMap to use it via composition.
DenseMapBase::Rep is also moved to densemap::detail::StorageRep so
that DenseMapStorage::getRep() can return it directly.
This is part of the effort to replace CRTP in DenseMapBase with
composition (see #168255). I'm planning to post a similar patch for
SmallDenseMap before actually removing CRTP.
Commit: 4564e3842abad0130a6dba143e91307e1336224e
https://github.com/llvm/llvm-project/commit/4564e3842abad0130a6dba143e91307e1336224e
Author: Jared Wyles <jared.wyles at gmail.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
A orc-rt/lib/bedrock/sys/windows/SocketConnector.cpp
M orc-rt/tools/ogre/CMakeLists.txt
Log Message:
-----------
[orc-rt] add stub for windows socket support. (#226855)
Commit: e50507339d91208da79b28f70d4f927828bb7d29
https://github.com/llvm/llvm-project/commit/e50507339d91208da79b28f70d4f927828bb7d29
Author: Mend Renovate <bot at renovateapp.com>
Date: 2026-09-27 (Sun, 27 Sep 2026)
Changed paths:
M .github/workflows/bazel-checks.yml
M .github/workflows/build-ci-container-tooling.yml
M .github/workflows/build-ci-container-windows.yml
M .github/workflows/build-ci-container.yml
M .github/workflows/build-libc-container.yml
M .github/workflows/build-metrics-container.yml
M .github/workflows/check-ci.yml
M .github/workflows/ci-post-commit-analyzer.yml
M .github/workflows/commit-access-review.yml
M .github/workflows/compiler-rt-libc-builtins-tests.yml
M .github/workflows/docs.yml
M .github/workflows/email-check.yaml
M .github/workflows/get-llvm-version/action.yml
M .github/workflows/gha-codeql.yml
M .github/workflows/hlsl-test-all.yaml
M .github/workflows/ids-check.yml
M .github/workflows/issue-release-workflow.yml
M .github/workflows/issue-write.yml
M .github/workflows/libc-freebsd-vm-tests.yml
M .github/workflows/libc-fullbuild-tests.yml
M .github/workflows/libc-overlay-tests.yml
M .github/workflows/libc-shared-tests.yml
M .github/workflows/libclang-abi-tests.yml
M .github/workflows/libcxx-benchmark-commit.yml
M .github/workflows/libcxx-benchmark-cron.yml
M .github/workflows/libcxx-build-containers.yml
M .github/workflows/libcxx-pr-benchmark.yml
M .github/workflows/libcxx-pr-check-generated-files.yml
M .github/workflows/libcxx-pr-conformance-tests.yaml
M .github/workflows/libcxx-pr-test-tools.yml
M .github/workflows/lldb-pylint-action.yml
M .github/workflows/llvm-abi-tests.yml
M .github/workflows/llvm-bugs.yml
M .github/workflows/mlir-spirv-tests.yml
M .github/workflows/new-prs.yml
M .github/workflows/pr-code-format.yml
M .github/workflows/pr-code-lint.yml
M .github/workflows/premerge.yaml
M .github/workflows/prune-branches.yml
M .github/workflows/release-asset-audit.yml
M .github/workflows/release-binaries.yml
M .github/workflows/release-documentation.yml
M .github/workflows/release-llvm-testing-tools.yml
M .github/workflows/release-sources.yml
M .github/workflows/release-tasks.yml
M .github/workflows/scorecard.yml
M .github/workflows/spirv-tests.yml
M .github/workflows/sycl-tests.yml
M .github/workflows/test-suite.yml
M .github/workflows/test-unprivileged-download-artifact.yml
M .github/workflows/upload-release-artifact/action.yml
M .github/workflows/version-check.yml
M .github/workflows/zizmor.yml
Log Message:
-----------
Update [Github] Update GHA Dependencies to v7 (#226858)
This PR contains the following updates:
| Package | Type | Update | Change |
|---|---|---|---|
| [actions/checkout](https://redirect.github.com/actions/checkout) |
action | major | `v6.0.3` → `v7.0.1` |
| [actions/checkout](https://redirect.github.com/actions/checkout) |
action | major | `v6.0.2` → `v7.0.1` |
| [actions/labeler](https://redirect.github.com/actions/labeler) |
action | major | `v6.2.0` → `v7.0.0` |
| [actions/setup-node](https://redirect.github.com/actions/setup-node) |
action | major | `v6.5.0` → `v7.0.0` |
|
[actions/setup-python](https://redirect.github.com/actions/setup-python)
| action | major | f |
Commit: e7dc4d6436526c4c7b31afec47a47530d98a6801
https://github.com/llvm/llvm-project/commit/e7dc4d6436526c4c7b31afec47a47530d98a6801
Author: Pavel Labath <pavel at labath.sk>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M libc/src/__support/OSUtil/linux/syscall_wrappers/close.h
M libc/src/__support/OSUtil/linux/syscall_wrappers/dup.h
M libc/src/__support/OSUtil/linux/syscall_wrappers/dup2.h
M libc/src/__support/OSUtil/linux/syscall_wrappers/dup3.h
M libc/src/__support/OSUtil/linux/syscall_wrappers/fcntl.h
M libc/src/__support/OSUtil/linux/syscall_wrappers/fsync.h
M libc/src/__support/OSUtil/linux/syscall_wrappers/ftruncate.h
M libc/src/__support/OSUtil/linux/syscall_wrappers/lseek.h
M libc/src/__support/OSUtil/linux/syscall_wrappers/memfd_create.h
M libc/src/__support/OSUtil/linux/syscall_wrappers/read.h
M libc/src/__support/OSUtil/linux/syscall_wrappers/write.h
Log Message:
-----------
[libc] Migrate file I/O syscall wrappers to syscall_checked (#226477)
Migrate a batch of related file descriptor and core I/O syscall wrappers
to use syscall_checked instead of manual syscall_impl error checking.
While in there:
- update file headers to the new style
- reformat includes into a single block so clang-format can sort them
Assisted-by: Gemini
Commit: be628f333947bf070839e6706f6701099e0c83eb
https://github.com/llvm/llvm-project/commit/be628f333947bf070839e6706f6701099e0c83eb
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-09-27 (Sun, 27 Sep 2026)
Changed paths:
M libcxx/utils/ci/docker/linux-builder.dockerfile
Log Message:
-----------
[libcxx] Still use CMake 3.31 in the CI image (#226749)
This ensures support with the minimum supported version rather than what
26.04 ships with by default (4.2.3).
Commit: 70f22b8e024924ff69674da78a61da4c200b0e3c
https://github.com/llvm/llvm-project/commit/70f22b8e024924ff69674da78a61da4c200b0e3c
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M llvm/lib/CodeGen/MachineBasicBlock.cpp
A llvm/test/CodeGen/AMDGPU/phi-elimination-split-critical-edge-subranges.mir
Log Message:
-----------
CodeGen: Fix SplitCriticalEdge using wrong VNInfo for subranges (#226214)
This fixes verifier errors when LiveIntervals is run before phi
elimination.
When extending a live interval across a newly split critical edge for a
PHI source operand, the subrange segments were added using the VNInfo of
the main range instead of the subrange's own value. Look up the
subrange's value at the predecessor's last index, as the other subrange
loop in the same function already does, and skip subranges with no value
there.
Co-authored-by: Claude Opus 5 <noreply at anthropic.com>
Commit: 7cb518a5a1acf0c2c1df7b5ed207518c45046916
https://github.com/llvm/llvm-project/commit/7cb518a5a1acf0c2c1df7b5ed207518c45046916
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M llvm/include/llvm/CodeGen/AsmPrinter.h
M llvm/include/llvm/CodeGen/BasicTTIImpl.h
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/include/llvm/Target/TargetMachine.h
M llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
M llvm/lib/CodeGen/CodeGenPrepare.cpp
M llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/CodeGen/TargetLoweringBase.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64TargetMachine.h
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.h
M llvm/lib/Target/ARM/ARMInstructionSelector.cpp
M llvm/lib/Target/ARM/ARMTargetMachine.h
M llvm/lib/Target/AVR/AVRTargetMachine.h
M llvm/lib/Target/Hexagon/HexagonTargetMachine.h
M llvm/lib/Target/LoongArch/LoongArchTargetMachine.h
M llvm/lib/Target/MSP430/MSP430AsmPrinter.cpp
M llvm/lib/Target/Mips/MipsTargetMachine.h
M llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
M llvm/lib/Target/PowerPC/PPCTargetMachine.h
M llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
M llvm/lib/Target/RISCV/RISCVTargetMachine.h
M llvm/lib/Target/SPIRV/SPIRVSubtarget.cpp
M llvm/lib/Target/Sparc/SparcISelLowering.cpp
M llvm/lib/Target/SystemZ/SystemZFrameLowering.cpp
M llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
M llvm/lib/Target/SystemZ/SystemZXPLINKAsmPrinter.cpp
M llvm/lib/Target/VE/VEISelLowering.cpp
M llvm/lib/Target/X86/GISel/X86LegalizerInfo.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86TargetMachine.cpp
M llvm/lib/Target/X86/X86TargetMachine.h
Log Message:
-----------
TargetMachine: Remove pointer-size query methods (#226404)
Remove the shim methods from the TargetMachine's copy of the DataLayout,
which will soon be eliminated. The Module owns the authoritative DataLayout,
so callers should read the value from the contextual Module.
Completely unreasonably, Mips's ABI name can change the pointer size which
we probably should just not support. Many other triple checks will never be
correct. This avoids potential mismatches in these contexts, but I still expect
this to be widely broken.
Some of the TargetLowering constructor changes and AMDGPULegalizerInfo
changes are kind of annoying. We could pass in the DataLayout through the
subtarget constructors but it didn't seem worth the effort and the information
should be derivable from the triple anyway.
Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
Commit: ee28ae7685e567d56e9ebb15ac4daf451d43f998
https://github.com/llvm/llvm-project/commit/ee28ae7685e567d56e9ebb15ac4daf451d43f998
Author: Lang Hames <lhames at gmail.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M orc-rt/tools/ogre/ogre.cpp
Log Message:
-----------
[orc-rt] Add comments to the ogre utility. NFC. (#226900)
Commit: 55f6f9304fff9a69373d6703d782b8e401d0af86
https://github.com/llvm/llvm-project/commit/55f6f9304fff9a69373d6703d782b8e401d0af86
Author: Lang Hames <lhames at gmail.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M orc-rt/cmake/OrcRTTesting.cmake
M orc-rt/test/regression/README.md
A orc-rt/test/regression/languages/c/addressing/cross-object/global-array-element-pointer-in-data.test
A orc-rt/test/regression/languages/c/addressing/cross-object/global-data-load.test
A orc-rt/test/regression/languages/c/addressing/cross-object/hidden-data-load.test
A orc-rt/test/regression/languages/c/addressing/same-object/global-data-pointer-in-data.c
A orc-rt/test/regression/languages/c/addressing/same-object/global-data-store.c
A orc-rt/test/regression/languages/c/addressing/same-object/static-array-element-load.c
A orc-rt/test/regression/languages/c/addressing/same-object/static-data-load.c
M orc-rt/test/regression/languages/c/lit.local.cfg
M orc-rt/test/regression/lit.cfg.py
Log Message:
-----------
[orc-rt] Add initial C addressing regression tests. (#226901)
Add tests that check that JIT'd C code can address data, both in the
same object and in other objects. Each test covers a single construct
(e.g. a load of static data, or a pointer to an array element in another
object stored in initialized data), since linker/loader bugs usually
crash the JIT'd program, and a crash identifies only the failing test.
Each test runs at -O0 and -O2.
To support multi-object tests, add a split-file substitution and lit
feature, and accept .test files in languages/c.
Update the README's test conventions to match: one construct per test,
"Check that" and "Stresses:" header comments, -O0 and -O2 RUN lines, and
guidance on keeping constructs alive under optimization without hiding
the optimized lowering.
Assisted-by: Claude
Commit: bbbfd872877d184d6a5bd0d2a5322c9fe8387648
https://github.com/llvm/llvm-project/commit/bbbfd872877d184d6a5bd0d2a5322c9fe8387648
Author: Lang Hames <lhames at gmail.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M llvm/docs/ORCv2.md
M llvm/include/llvm/ExecutionEngine/Orc/Core.h
M llvm/include/llvm/ExecutionEngine/Orc/ExecutorProcessControl.h
M llvm/unittests/ExecutionEngine/Orc/ExecutionSessionWrapperFunctionCallsTest.cpp
Log Message:
-----------
[ORC] Remove callSPSWrapper, callSPSWrapperAsync, and callWrapper (#226893)
All in-tree callers now use Proxy. Remove the SPS convenience call
methods from ExecutionSession and ExecutorProcessControl, along with the
unit tests that exercised them (Proxy dispatch is covered by
SPSProxySpecTest). Also remove the blocking callWrapper convenience
methods, which have no remaining users.
Add a "How to call functions in the executor" section to
llvm/docs/ORCv2.md describing Proxy, controller-interface descriptors
and sps::ProxySpec, how lookupAndApply and recordProxy resolve proxies,
and how to migrate from callSPSWrapper.
Clients calling these methods directly should migrate to Proxy; see "How
to call functions in the executor" in llvm/docs/ORCv2.md.
Commit: 10cd57a6f616dc4836ef572399410d62b16f701d
https://github.com/llvm/llvm-project/commit/10cd57a6f616dc4836ef572399410d62b16f701d
Author: Fangrui Song <i at maskray.me>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M llvm/include/llvm/CGData/CodeGenData.h
M llvm/include/llvm/CGData/CodeGenDataReader.h
M llvm/lib/CGData/CodeGenData.cpp
M llvm/lib/CGData/CodeGenDataReader.cpp
M llvm/lib/LTO/LTO.cpp
M llvm/tools/llvm-cgdata/llvm-cgdata.cpp
Log Message:
-----------
[CGData] Stop exporting cl::opts. NFC (#226861)
LTO reads `-codegen-data-thinlto-two-rounds` through
`extern cl::opt<bool> CodeGenDataThinLTOTwoRounds`, and llvm-cgdata
assigns
`IndexedCodeGenDataLazyLoading`, exported from CodeGenDataReader.h. Add
`cgdata::thinLTOTwoRounds()` for LTO, and pass lazy loading to
`CodeGenDataReader::create` as a parameter, so that the options can be
file-local.
Aided by Opus 5.5
Commit: 4362da25049882128f50a0f6b4fb69c1a0f8fd57
https://github.com/llvm/llvm-project/commit/4362da25049882128f50a0f6b4fb69c1a0f8fd57
Author: Pankaj Dwivedi <pankajkumar.divedi at amd.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
M llvm/lib/Target/AMDGPU/GCNHazardRecognizer.h
M llvm/test/CodeGen/AMDGPU/mai-hazards-gfx90a.mir
M llvm/test/CodeGen/AMDGPU/mai-hazards-gfx942.mir
Log Message:
-----------
[AMDGPU] Add wait states between different MFMAs sharing an accumulator (#218363)
A full-register src2/C read after an MFMA write emits no wait states,
relying on accumulator forwarding that only works while the chain stays
on one MFMA. Two different MFMAs sharing an accumulator instead need the
wait states of a partial overlap: on gfx950, v_mfma_f32_16x16x32_f16
then
v_mfma_f32_16x16x16_f16 on the same tuple needs 5 and got none. Compare
canonicalized opcodes so mac and register-bank forms still match.
Assisted-by: Claude Opus 5
Commit: 7a931b5ec3f305a51f702cb0702d2a07f7e74c0b
https://github.com/llvm/llvm-project/commit/7a931b5ec3f305a51f702cb0702d2a07f7e74c0b
Author: Kiroo (Chanung) <ung at zlfn.space>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
Log Message:
-----------
[GlobalISel] Use getCmpLibcallReturnType() for FCMP libcalls (NFC) (#226813)
The GCC soft-float comparison routines return `CMPtype`, not always
`i32`.
https://gcc.gnu.org/onlinedocs/gccint/Soft-float-library-routines.html#Comparison-functions-1
> 3.2.3 Comparison functions
> There are two sets of basic comparison functions.
> ...
> Runtime Function: CMPtype __unordsf2 (float a, float b)
> Runtime Function: CMPtype __unorddf2 (double a, double b)
> Runtime Function: CMPtype __unordtf2 (long double a, long double b)
> ...
The FCMP libcall result was hardcoded to i32. Use
`getCmpLibcallReturnType()`, as SelectionDAG does.
NFC for in-tree targets.
Co-authored-by: Thorbjørn Ravn Andersen <tra at ravnand.dk>
Commit: 8fe3fdd6630e04b48dd8253894a8d4ba429e4663
https://github.com/llvm/llvm-project/commit/8fe3fdd6630e04b48dd8253894a8d4ba429e4663
Author: Oliver Hunt <oliver at apple.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M llvm/lib/IR/Verifier.cpp
M llvm/lib/Transforms/Utils/CodeExtractor.cpp
A llvm/test/Assembler/invalid-diexpression-arg-negative.ll
A llvm/test/DebugInfo/AArch64/dbg-value-arg-index-out-of-range.ll
A llvm/test/Transforms/HotColdSplit/split-out-dbg-val-arglist.ll
A llvm/test/Verifier/dbg-record-expression-arg-out-of-range.ll
Log Message:
-----------
[CodeExtractor][Verifier] Fix OoB read when a DIExpression is used multiple times (#226857)
#224360 made fixupDebugInfoPostExtraction reuse the existing
DIExpression, but this is not sound if the expression is referenced
multiple times, as occurs with cold/hot code splitting.
This PR is the trivial fix of restricting this change to only apply if
there is a single user of the expression.
I've also added an additional verifier guard to capture these failures.
Fixes #226848
AI usage: Claude used to find a way to construct
dbg-value-arg-index-out-of-range.ll so that I could add a verifier guard
that bypassed the other existing verifier guards.
Commit: cb9ee31ad93d35af0ee9172cd368dd537546a8d6
https://github.com/llvm/llvm-project/commit/cb9ee31ad93d35af0ee9172cd368dd537546a8d6
Author: jeanPerier <jperier at nvidia.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M flang/include/flang/Optimizer/Transforms/Passes.td
M flang/lib/Optimizer/Transforms/CMakeLists.txt
M flang/lib/Optimizer/Transforms/LoopInvariantCodeMotion.cpp
A flang/test/Transforms/licm-acc-captured-ref.fir
A flang/test/Transforms/licm-acc-compute-only.fir
A flang/test/Transforms/licm-scope.fir
Log Message:
-----------
Reland [flang] Support scoped LICM and OpenACC capture provenance (#225401) (#226909)
Follow compute-region capture operands when checking whether scalar and
scalar-descriptor loads are safe to speculate. Preserve the existing
optional, array-element, and loop-modification safety checks.
Add an optional only-inside operation-name selector while retaining
function-scoped alias analysis. Resolve the name once per function and
compare interned operation names during ancestor traversal. The default
continues to select all loops. An explicit name selects loops with a
matching ancestor within the function, including the function itself.
Cover capture safety, host exclusion, non-OpenACC and nested scopes,
loop boundaries, unmatched names, and the function boundary.
The motivation for this is to allow running LICM only on device relevant
loop at O0.
Reland #225401 with CMakeFiles.txt change to fix shared library builds.
Commit: 084a4e6002a9b718adb31dd906b233cafd3a9814
https://github.com/llvm/llvm-project/commit/084a4e6002a9b718adb31dd906b233cafd3a9814
Author: Steffen Larsen <sholstla at amd.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenBuiltinAMDGPU.cpp
M clang/test/CIR/CodeGenHIP/builtins-amdgcn-gfx10.hip
Log Message:
-----------
[CIR][AMDGPU] Implement __builtin_amdgcn_*_dpp* builtins (#226469)
This commit implements the `__builtin_amdgcn_update_dpp`,
`__builtin_amdgcn_mov_dpp`, and `__builtin_amdgcn_mov_dpp8` builtins in
CIR, closely matching the implementation in
CodeGenFunction::EmitAMDGPUBuiltinExpr from OGCG.
Assisted-by: Claude Sonnet 5
Signed-off-by: Steffen Holst Larsen <sholstla at amd.com>
Commit: 44d86afe24ce107f76141ae45f6fe44c44675bbe
https://github.com/llvm/llvm-project/commit/44d86afe24ce107f76141ae45f6fe44c44675bbe
Author: Kane Wang <wangqiang1 at kylinos.cn>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M llvm/unittests/CodeGen/GlobalISel/LegalizerHelperTest.cpp
Log Message:
-----------
[GlobalISel][NFC] Restore the extended LLT flag to its saved value in tests (#224897)
AArch64GISelMITest's setUp() constructs an AArch64TargetMachine, which
unconditionally enables the process-global extended LLT flag. Ending the
ExtLLT tests with setUseExtended(false) therefore disables the flag for
every test that runs afterwards in the same process.
Save the flag's value on entry and restore it on exit instead.
Commit: 310cf744bd0c1af7b07377a8fa5a6c2fd72ef4a3
https://github.com/llvm/llvm-project/commit/310cf744bd0c1af7b07377a8fa5a6c2fd72ef4a3
Author: Luke Lau <luke at igalia.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
Log Message:
-----------
[VPlan] Remove (X && Y) | (X && !Y) -> X combine. NFC (#219368)
We have smaller combines that can take care of this now that we process
recipes in a worklist after #213900
Commit: 6ee306ddac89f9cbfc8815e8956240f0bf832dcb
https://github.com/llvm/llvm-project/commit/6ee306ddac89f9cbfc8815e8956240f0bf832dcb
Author: Chris Kennelly <ckennelly at ckennelly.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
A llvm/test/CodeGen/X86/bzhi-standalone-mask.ll
Log Message:
-----------
[X86] Select standalone ~(-1 << n) masks as BZHI (#226158)
InstCombine canonicalizes (1 << n) - 1 to xor (shl -1, n), -1. When that
mask feeds an AND, X86DAGToDAGISel::matchBitExtract folds the whole
expression into BZHI, and the add form is selected as BZHI even on its
own because Select enters matchBitExtract from ISD::ADD. The xor form on
its own is not: a mask that is returned, stored, or consumed by anything
but AND is selected as mov -1; shlx; not.
Enter matchBitExtract from ISD::XOR too under BMI2, so the standalone
mask becomes mov -1; bzhi. That is one instruction shorter and avoids
the shlx+not dependency chain. BMI1-only targets keep the shift form,
since BEXTR would need the count moved into bits 15:8 first.
Assisted-by: Claude Code
Commit: 3804292c4c3adcd4b8505dc78aed73e211b44752
https://github.com/llvm/llvm-project/commit/3804292c4c3adcd4b8505dc78aed73e211b44752
Author: David Spickett <david.spickett at arm.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M lldb/unittests/ObjectContainer/ObjectContainerClangOffloadBundleTest.cpp
Log Message:
-----------
[lldb] Fix offload bundle unit tests on 32-bit systems (#226922)
DataExtractor::GetByteSize returns uint64_t for reasons I don't yet
understand. I might change it to size_t but let's unblock the build for
now.
Fixes #222362 / 08ee0ef5da10d27d5776df1e1ff81c46a38d9b5c.
Commit: 2a96d5737524012839e786699a0b327f22d1cfee
https://github.com/llvm/llvm-project/commit/2a96d5737524012839e786699a0b327f22d1cfee
Author: ioana ghiban <ioana.ghiban at arm.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M mlir/include/mlir/Dialect/Utils/StaticValueUtils.h
M mlir/lib/Dialect/GPU/CMakeLists.txt
M mlir/lib/Dialect/GPU/Transforms/DecomposeMemRefs.cpp
M mlir/lib/Dialect/MemRef/IR/MemRefOps.cpp
M mlir/lib/Dialect/MemRef/Transforms/ExpandStridedMetadata.cpp
M mlir/lib/Dialect/Utils/StaticValueUtils.cpp
M mlir/lib/IR/BuiltinTypes.cpp
M mlir/test/Conversion/MemRefToSPIRV/memref-to-spirv.mlir
M mlir/test/Dialect/GPU/decompose-memrefs.mlir
M mlir/test/Dialect/MemRef/canonicalize.mlir
M mlir/test/Dialect/MemRef/elide-reinterpret-cast-load.mlir
M mlir/test/Dialect/MemRef/expand-strided-metadata.mlir
M mlir/test/Dialect/MemRef/ops.mlir
Log Message:
-----------
[mlir][memref] Enforce consistent reinterpret_cast metadata (#217338)
This PR implements [[RFC] Clarify `memref.reinterpret_cast` Verification
of Dynamic
Metadata](https://discourse.llvm.org/t/rfc-clarify-memref-reinterpret-cast-verification-of-dynamic-metadata).
## Context
`memref.reinterpret_cast` describes its result through both its mixed
offset/size/stride metadata and its result `MemRefType`. Currently,
verification allowed a dynamic result-type correspond to static
operation metadata, introducing inconsistent descriptors.
For example, the verifier permits:
```mlir
%r = memref.reinterpret_cast %base
to offset: [0], sizes: [%n, 2], strides: [%s, 1] : memref<f32>
to memref<?x?xf32, strided<[?, ?], offset: ?>>
```
where the operation constructs a descriptor with a statically known
second size and stride, but the result type does not expose those facts.
## Changes
This PR consolidates the verifier to require `reinterpret_cast` result
type’s sizes, offset, and strides to exactly match the static/dynamic
representation and values of the operation metadata.
Transforms that create `memref.reinterpret_cast`, including GPU memref
decomposition and strided-metadata expansion for `subview` and
`collapse_shape`, now derive the result type from the final, potentially
folded descriptor instead of inheriting the original operation’s result
type.
When this descriptor-derived type differs from the original result type,
the rewrite inserts a `memref.cast` back to the original type. These
rewrites are not type-conversion patterns, so their existing
users—including function returns and calls—must retain their original
types. Identity stride layouts are canonicalized when possible to avoid
unnecessary explicit layouts and casts.
Tests are updated to use result types consistent with their
`reinterpret_cast` metadata. In the SPIR-V tests, the size `10` is
represented by an SSA value because those cases intentionally remain
dynamically shaped and lower to element pointers; making the size static
would change the SPIR-V pointee type and prevent the existing
`reinterpret_cast` lowering from applying.
A regression test also verifies that folded `subview` offsets and
strides are reflected in the generated `reinterpret_cast` type.
---
Assisted-by: Codex (refine implementation + tests). I reviewed all code
and tests before submission.
Commit: fe5ace607b587df1d46174846c40e3afe2c0a4a3
https://github.com/llvm/llvm-project/commit/fe5ace607b587df1d46174846c40e3afe2c0a4a3
Author: Yuvaraj Venkatesh <yuvaraj.venkatesh at arm.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M mlir/include/mlir/Dialect/Tosa/IR/TosaOps.td
M mlir/test/Conversion/TosaToSPIRVTosa/graph-constant-mark.mlir
M mlir/test/Dialect/Tosa/canonicalize.mlir
M mlir/test/Dialect/Tosa/constant_folding.mlir
M mlir/test/Dialect/Tosa/ops.mlir
M mlir/test/Dialect/Tosa/tosa-arith-const-to-tosa-const.mlir
M mlir/test/Dialect/Tosa/tosa-convert-integer-type-to-signless.mlir
M mlir/test/Dialect/Tosa/tosa-decompose-depthwise.mlir
M mlir/test/Dialect/Tosa/tosa-decompose-transpose-conv.mlir
M mlir/test/Dialect/Tosa/tosa-gather-scatter-hardening.mlir
M mlir/test/Dialect/Tosa/tosa-infer-shapes.mlir
M mlir/test/Dialect/Tosa/tosa-layerwise-constant-fold-dense-resource.mlir
M mlir/test/Dialect/Tosa/tosa-layerwise-constant-fold.mlir
M mlir/test/Dialect/Tosa/tosa-narrow-f32-to-f16-aggressive.mlir
M mlir/test/Dialect/Tosa/tosa-narrow-f32-to-f16.mlir
M mlir/test/Dialect/Tosa/tosa-narrow-f64-to-f32-aggressive.mlir
M mlir/test/Dialect/Tosa/tosa-narrow-f64-to-f32.mlir
M mlir/test/Dialect/Tosa/tosa-narrow-i64-to-i32-aggressive.mlir
M mlir/test/Dialect/Tosa/tosa-narrow-i64-to-i32.mlir
M mlir/test/Dialect/Tosa/tosa-reduce-transposes.mlir
Log Message:
-----------
[mlir][tosa] Add assembly format for CONST (#226147)
This commit adds an assembly format for the TOSA CONST operation.
Previously, the generic assembly format was used while all other
operations had a custom format. It takes advantage of the incoming
textual format changes in #217291, to minimise impact to downstream
consumers.
Commit: 9fdcf6a0cafba6af912da2acb58f19addeb7722c
https://github.com/llvm/llvm-project/commit/9fdcf6a0cafba6af912da2acb58f19addeb7722c
Author: Momchil Velikov <momchil.velikov at arm.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M llvm/include/llvm/Transforms/Scalar/GVN.h
M llvm/lib/Transforms/Scalar/GVN.cpp
Log Message:
-----------
[GVN] Decouple GVNValueTable and GVNPass (NFC) (#226232)
This is a first patch in series with the ultimate goal to move `GVNPass`
out of `GVN.h` and into `GVN.cpp`.
This is not straightforward because because of the rather tangled
dependencies between `GVNPass`, `GVNHoistPass`, `ValueTable`, and
`LeaderMap`.
The `GVNHoistPass` pass references `GVNPass::ValueTable`, by peeking
into `GVNPass`, resp. including `GVN.h`. Since `GVNHoistPass` does not
actually depend on `GVNPass` itself, but only on the `ValueTable` it
contains, it would make more sense to move `ValueTable` out of `GVN.h`
to its own header file, to be included by both `GVN.h` and
`GVNHoist.cpp.`
That's not entirely straightforward either since `ValueTable` has
several member functions taking a `GVNPass` reference as an argument.
This prevents moving `GVNPass` out of `GVN.h` and into an anonymous
namespace in `GVN.cpp`.
These `GVNPass` (in `ValueTable`) references are only used to access the
`LeaderMap`. Consequently, `LeaderMap` can be moved out of `GVNPass` and
into the `llvm` namespace and forward declared for its uses by
`ValueTable` (when `ValueTable` gets its own header).
This patch moves the `LeaderMap` out of `GVNPass`, into the `llvm`
namespace, and renames it to `GVNLeaderMap`.
Commit: be2eb0a91356ae3a1910d8226137b54db480166d
https://github.com/llvm/llvm-project/commit/be2eb0a91356ae3a1910d8226137b54db480166d
Author: Mariusz Sikora <mariusz.sikora at amd.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/test/MC/AMDGPU/gfx13_asm_vop3-fake16.s
M llvm/test/MC/AMDGPU/gfx13_asm_vop3.s
A llvm/test/MC/AMDGPU/gfx13_asm_vop3_from_vop1_err-fake16.s
A llvm/test/MC/AMDGPU/gfx13_asm_vop3_from_vop1_err.s
Log Message:
-----------
[AMDGPU] Add gfx13 MC support for exclusive scan instructions (#226077)
Commit: f1de563a490b486738e65a6fef040e0e40d1bb21
https://github.com/llvm/llvm-project/commit/f1de563a490b486738e65a6fef040e0e40d1bb21
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M llvm/test/Transforms/SLPVectorizer/X86/runtime-alias-checks.ll
Log Message:
-----------
[SLP][NFC]Add a test with the missing runtime checks for vectorization, NFC
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/226947
Commit: 4c31d2c7641e180c2c9098e466b2247bb470fc25
https://github.com/llvm/llvm-project/commit/4c31d2c7641e180c2c9098e466b2247bb470fc25
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
A llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-spill-multi-store-codegen.ll
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-spill-multi-store.ll
Log Message:
-----------
AMDGPU: Make rewrite-vgpr-mfma-to-agpr-spill-multi-store.ll less allocator sensitive (#226913)
This test is sensitive to the exact split and spills which occur, and disappeared under
a future upstream improvement. Use basic RA with a fixed occupancy since it more
stably produces the spill pattern.
Also add a codegen reference test for the same kernel, so future codegen
improvements are visible.
Co-authored-by: Claude Opus 5 <noreply at anthropic.com>
Commit: c44450f30d17c64005fc74c506a01c373ddf702c
https://github.com/llvm/llvm-project/commit/c44450f30d17c64005fc74c506a01c373ddf702c
Author: Weiwen He <60433849+he-weiwen at users.noreply.github.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/cmp-shiftX-maskX.ll
A llvm/test/CodeGen/X86/cmp-shrink-unsigned.ll
Log Message:
-----------
[X86] Shrink i32 unsigned compares to i8/i16 when high bits are zero (#197801)
Shrink i32 compares to 8 or 16 bit for non-constant operands when high
bits are zero, following the precedent of i64 -> i32 case.
Fixes the cases in #196827 where both sides of the compare are
non-constants, as this allows the `and(X, mask) `to be eliminated
downstream in DAGCombine.
I believe we can extend to constant operands as long as the length
changing prefix problem for i16 immediates is accounted for - however:
1. it's not sufficient to fix the remaining cases in the motivating
issue alone: when the rhs is constant, InstCombine clear the bits in the
mask that does not affect the comparison result (`icmp (and X, 255),
123` -> `icmp (and X, 252), 123`), so the mask does not fill the full
width of the truncated type, making the analysis trickier.
2. it leads to a lot of check line drifts, i'm not sure if it's worth
the effort to account for all of them, even if most don't look like
regressions.
Commit: a945adae2eb9236392fbbfe1ab5181f8c073d6f8
https://github.com/llvm/llvm-project/commit/a945adae2eb9236392fbbfe1ab5181f8c073d6f8
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M llvm/lib/Analysis/ScalarEvolution.cpp
Log Message:
-----------
[SCEV] Use makeExactNoWrapRegion for constant operands. (NFC) (#223973)
Use makeExactNoWrapRegion when constant is available.
Together with https://github.com/llvm/llvm-project/pull/223969, this
reduces compile-time in SCEV heavy workloads:
stage1-O3: -0.10%
stage1-ReleaseThinLTO: -0.0.9%
stage1-ReleaseLTO-g: -0.08%
stage1-aarch64-O3: -0.09%
stage2-O3: -0.07%
https://llvm-compile-time-tracker.com/compare.php?from=016fa12d18058b83c528f2af859e45df4548034f&to=e2efeaf6a19ac8c53170f2a2b196f3d38268fd32&stat=instructions:u
PR: https://github.com/llvm/llvm-project/pull/223973
Commit: 7f133e72828d68cbd8ce06bf64ea0fe8b8528c06
https://github.com/llvm/llvm-project/commit/7f133e72828d68cbd8ce06bf64ea0fe8b8528c06
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M llvm/include/llvm/AsmParser/LLParser.h
M llvm/lib/AsmParser/LLParser.cpp
M llvm/test/Bitcode/upgrade-tbaa.ll
A llvm/test/Bitcode/upgrade-tbaa.ll.bc
M polly/test/CodeGen/OpenMP/single_loop_with_loop_invariant_baseptr.ll
Log Message:
-----------
[AsmParser] Remove TBAA auto-upgrade in IR parser (#226914)
At this point, the struct path TBAA format is more than a decade old, so
remove support for upgrading from the old format in the textual IR
parser. Bitcode upgrade support is retained, as bitcode is backwards
compatible.
This avoids introduction of new tests using the old format. Existing
tests were migrated in https://github.com/llvm/llvm-project/pull/226051.
Commit: 82aa78850bb1c90df3d747062555b2f34b0466c5
https://github.com/llvm/llvm-project/commit/82aa78850bb1c90df3d747062555b2f34b0466c5
Author: Ramkumar Ramachandra <artagnon at tenstorrent.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M llvm/include/llvm/Analysis/ScalarEvolution.h
M llvm/lib/Analysis/ScalarEvolution.cpp
Log Message:
-----------
[SCEV] Rename SCEVFlags -> SCEVFlagsPair (NFC) (#226935)
Make it clear that it's a pair of no-wrap flags, and free up the
SCEVFlags name for renaming SCEVNoWrapFlags to it.
Commit: c786529445a1ecb3e8618eba4d68132e40c2e40f
https://github.com/llvm/llvm-project/commit/c786529445a1ecb3e8618eba4d68132e40c2e40f
Author: Mian Miftah <mmiftah.duna at gmail.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Utils/SimplifyCFG.cpp
M llvm/test/Transforms/SimplifyCFG/hoist-common-skip.ll
Log Message:
-----------
[SimplifyCFG] Drop UB-implying attributes when hoisting speculatively (#226746)
`hoistCommonCodeFromSuccessors()` can hoist identical instructions past
non-identical ones that it skips. If a skipped instruction may throw or
not return, the hoisted instruction is speculated, but it keeps its
UB-implying attributes and metadata, like `noundef`. Drop them in that
case, as SimplifyCFG already does when it speculates.
Commit: bc4c516f6e324d147eaeea1bd7d58eb57d03a671
https://github.com/llvm/llvm-project/commit/bc4c516f6e324d147eaeea1bd7d58eb57d03a671
Author: David Spickett <david.spickett at arm.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M lldb/test/API/functionalities/scripted_frame_provider/thread_filter/TestFrameProviderThreadFilter.py
Log Message:
-----------
[lldb][test] Enable TestFrameProviderThreadFilter.py on Arm (#226953)
Fixes #191855. I do not know why, but this test no longer crashes on
Arm.
Commit: 17b078d0b68d8d081e5add811b0d6cd91b374160
https://github.com/llvm/llvm-project/commit/17b078d0b68d8d081e5add811b0d6cd91b374160
Author: Tomas Matheson <Tomas.Matheson at arm.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Utils/BuildLibCalls.cpp
M llvm/test/Transforms/InferFunctionAttrs/annotate.ll
Log Message:
-----------
[BuildLibCalls] Infer attributes for posix_memalign (#226943)
Handle posix_memalign in inferNonMandatoryLibFuncAttrs.
Commit: 3123f219c9a536a586df1d253d13ec49ab95ca38
https://github.com/llvm/llvm-project/commit/3123f219c9a536a586df1d253d13ec49ab95ca38
Author: Mian Miftah <mmiftah.duna at gmail.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M llvm/lib/Transforms/IPO/MergeFunctions.cpp
A llvm/test/Transforms/MergeFunc/redirect-call-debug-loc.ll
Log Message:
-----------
[MergeFunctions] Add debug locations to redirected calls (#225625)
A call to a function without debug info does not need a debug location,
even in a function with debug info. If MergeFunctions redirects such a
call to an equivalent function that has debug info, the verifier fails:
```
inlinable function call in a function with debug info must have a !dbg location
```
Before redirecting such a call, give it a line 0 location in the scope
of the caller, as `DwarfEHPrepare` does for the call to the rewind
function. This covers both ways calls are redirected:
`replaceDirectCallers()`, and `replaceAllUsesWith()` for `unnamed_addr`
functions.
Commit: 380d489bcd2a4e4dbe877f9518ee696348f419ea
https://github.com/llvm/llvm-project/commit/380d489bcd2a4e4dbe877f9518ee696348f419ea
Author: David Spickett <david.spickett at arm.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M lldb/test/API/api/multiple-debuggers/multi-process-driver.cpp
Log Message:
-----------
[lldb][test] Fix undefined behaviour in multi process driver (#226949)
This code was using strcmp on function names. Function names can be null
(see SBFrame::GetFunctionName), and passing null to strcmp is UB.
Commit: ccd2a3f748d7a4898fe2850491796f01603e8d72
https://github.com/llvm/llvm-project/commit/ccd2a3f748d7a4898fe2850491796f01603e8d72
Author: Dávid Bolvanský <david.bolvansky at gmail.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M llvm/lib/Analysis/BasicAliasAnalysis.cpp
Log Message:
-----------
[BasicAA] Compute minimal access extents lazily (#226931)
`aliasCheck` computes the minimal extent of an access before calling
`isObjectSmallerThan`, even though the latter immediately returns false
when the other pointer is not an identified object.
Move the extent computation behind the existing `isIdentifiedObject`
check. This preserves the result: whenever the extent can affect the
answer, the same value is computed and used as before; otherwise only
unused work is skipped.
Commit: 4df13761d078a2f3c10c4ed7fab033df116b6cdc
https://github.com/llvm/llvm-project/commit/4df13761d078a2f3c10c4ed7fab033df116b6cdc
Author: Tim Besard <tim.besard at gmail.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
A llvm/test/Transforms/SLPVectorizer/X86/strength-reducible-address.ll
Log Message:
-----------
[SLP] Add tests for affine loop address computations (NFC) (#226907)
Precommit tests for #226220: related affine address recurrences in a
loop whose index arithmetic SLP currently vectorizes and extracts per
lane for scalar loads and stores, which LSR would otherwise turn into
pointer increments.
`X86/strength-reducible-address.ll` has Haswell and skylake-avx512 RUN
lines. It covers strided loads, constant-offset GEPs, and a load/store
at the same address. The negative cases are loop-loaded offsets,
escaping addresses, and offsets computed in the preheader. The checks
are generated with current main.
Commit: eac59201583b098cbd6b4b4619d165e90f50937d
https://github.com/llvm/llvm-project/commit/eac59201583b098cbd6b4b4619d165e90f50937d
Author: Vikash Gupta <Vikash.Gupta at amd.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
A llvm/test/CodeGen/AArch64/GlobalISel/knownbits-freeze.mir
M llvm/test/CodeGen/AArch64/GlobalISel/knownfpclass-ops.mir
Log Message:
-----------
[GlobalISel] Support GISelValueTracking for G_FREEZE. (#223696)
Port the SDAG FREEZE handling to GlobalISel. Look through G_FREEZE in
computeKnownBits, computeNumSignBits, and computeKnownFPClass when the
source is guaranteed not undef or poison.
Part of #150515.
---------
Co-authored-by: Matt Arsenault <arsenm2 at gmail.com>
Commit: 71cbaace075d39f87063afa9d0da165ee04345b3
https://github.com/llvm/llvm-project/commit/71cbaace075d39f87063afa9d0da165ee04345b3
Author: David Green <david.green at arm.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/test/CodeGen/AArch64/binopshuffles.ll
M llvm/test/CodeGen/AArch64/fp-intrinsics-vector.ll
M llvm/test/CodeGen/AArch64/neon-truncstore.ll
M llvm/test/CodeGen/AArch64/store.ll
M llvm/test/CodeGen/AArch64/sve-extract-vector-to-predicate-store.ll
M llvm/test/CodeGen/AArch64/vec3-loads-ext-trunc-stores.ll
Log Message:
-----------
[AArch64] Combine truncate(buildvector) -> buildvector (#223787)
If late in the pipeline we are left with truncate(buildvector), we can
generate the buildvector directly. This helps remove the xtn and can
lead to other simplification.
Commit: ca1b270af6e567ae7caa50cd2b3ede418b7cde5f
https://github.com/llvm/llvm-project/commit/ca1b270af6e567ae7caa50cd2b3ede418b7cde5f
Author: Abhina Sree <Abhina.Sreeskantharajan at ibm.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M clang/tools/clang-ssaf-src-edit-merge/SrcEditMerge.cpp
Log Message:
-----------
[SystemZ][z/OS] Open text files as text (#226518)
This patch fixes lit regressions in clang-ssaf-src-edit-merge by opening
text files as text.
Commit: 6861b01646bd770523e94f3efe572f598cfdcc53
https://github.com/llvm/llvm-project/commit/6861b01646bd770523e94f3efe572f598cfdcc53
Author: Igor Wodiany <igor.wodiany at amd.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M llvm/lib/ObjectYAML/DWARFEmitter.cpp
Log Message:
-----------
[DWARFYAML] Declare `OffsetEntryCount` as `uint64_t` (#224631)
This prevents a potential multiplication overflow when `OffsetsSize` is
calculated and fixes an issue reported by a CodeQL scan.
Commit: 141ad3d5e3312eccc977b20af18c978e46fd9b40
https://github.com/llvm/llvm-project/commit/141ad3d5e3312eccc977b20af18c978e46fd9b40
Author: Dhairyashil R G <dhairyashil25 at gmail.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
M mlir/test/Dialect/LLVMIR/nvvm_check_target_sm.mlir
Log Message:
-----------
[MLIR][NVVM] Add SM version requirements to mbarrier Ops (#224105)
The mbarrier Ops had no `NVVMRequiresSM` trait, so a `gpu.module`
targeting an older chip (e.g. `sm_75`) accepted them, and the error only
showed up later. This adds the trait to all 13 of them, same as #192257
and `mbarrier.check_layout` in #217252.
| floor | Ops |
|---|---|
| `sm_80` | `init`, `inval`, `arrive`, `arrive_drop`,
`arrive.nocomplete`, `arrive_drop.nocomplete`, `test.wait` |
| `sm_90` | `expect_tx`, `complete_tx`, `arrive.expect_tx`,
`arrive_drop.expect_tx`, `try_wait`, `try_wait.parity` |
The floors come from the Target ISA Notes in the [PTX ISA
8.5](https://docs.nvidia.com/cuda/pdf/ptx_isa_8.5.pdf) (section
9.7.12.15), and they match the backend: every Op that lowers to an
intrinsic fails to compile one arch below its floor and compiles at it.
`arrive_drop` at sm_80 relies on #222916.
Since the trait is per Op, some settings that need sm_90 still get
through on sm_80: an explicit `count`, `scope = cluster`, a
`shared::cluster` pointer, `relaxed = true`, or `layout` on `init`.
Catching those would mean the Ops implementing `getRequiredMinSMVersion`
themselves, which no Op does yet. Happy to add that if you'd like. PTX
version isn't covered either (#69448).
One behaviour change: `gpu-lower-to-nvvm-pipeline` and
`nvvm-attach-target` default to `sm_75`, so using mbarrier Ops with that
default now fails earlier, with a clear message. `verifyTarget = false`
turns the check off.
Tests are in `nvvm_check_target_sm.mlir`: one failing case per Op just
below its floor, plus passing cases at the floor, above it, and on
`sm_90a`.
Assisted-by: Claude
Commit: 3eb90f564e8b3c8bc93c1f139589ebad30f09b9e
https://github.com/llvm/llvm-project/commit/3eb90f564e8b3c8bc93c1f139589ebad30f09b9e
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
M llvm/test/Transforms/LoopVectorize/VPlan/execution-frequencies-match-bfi.ll
M llvm/test/Transforms/LoopVectorize/X86/predicated-instruction-cost.ll
M llvm/test/Transforms/LoopVectorize/replicate-region-branch-weights.ll
Log Message:
-----------
[VPlan] Distribute execution frequencies with BlockFrequencyInfo's code. (#226841)
Instead of hand-rolling frequency propagating, manually construct BFI
and use BFI::distributeMass.
Adds a final step where frequencies are rounded up to at least one, to
distinguish between unreachable and almost never executed blocks. This
matches BFI behavior.
Note that we need to still track whether frequencies are from edges with
unknown profile info.
PR: https://github.com/llvm/llvm-project/pull/226841
Commit: d8b7da91eb8d8c2232c58a9f8b9f2136861da343
https://github.com/llvm/llvm-project/commit/d8b7da91eb8d8c2232c58a9f8b9f2136861da343
Author: Will Hawkins <hawkinsw at obs.cr>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M llvm/include/llvm-c/DebugInfo.h
M llvm/include/llvm/BinaryFormat/Dwarf.def
M llvm/include/llvm/BinaryFormat/Dwarf.h
M llvm/lib/BinaryFormat/Dwarf.cpp
A llvm/test/DebugInfo/Generic/compileunit-source-language-name-roc.ll
Log Message:
-----------
[DWARF] Support Roc Language (#225631)
The Roc language has been assigned language codes for DWARF v5 and v6.
See [DWARF Issue 260821.1](https://dwarfstd.org/issues/260828.1.html).
Commit: cf5a39d92984abb7e6e2bac57af6dd9c0abba21a
https://github.com/llvm/llvm-project/commit/cf5a39d92984abb7e6e2bac57af6dd9c0abba21a
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M llvm/lib/Frontend/OpenMP/OMPDescriptors.inc
Log Message:
-----------
[OpenMP] Add/update descriptors for extension clauses (#226509)
Commit: 5d8b5942fa5924d1bf1920fe63623d8e50c58d9a
https://github.com/llvm/llvm-project/commit/5d8b5942fa5924d1bf1920fe63623d8e50c58d9a
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M llvm/lib/Frontend/OpenMP/OMPDescriptors.inc
Log Message:
-----------
[OpenMP] Update modifier set properties on some clauses (#226508)
The modifier sets on DEPEND, NUM_TEAMS and REDUCTION in 6.1 only have
the exclusive property.
Commit: 8af4ce85a25634994ebd19223dac15213b1a7dbc
https://github.com/llvm/llvm-project/commit/8af4ce85a25634994ebd19223dac15213b1a7dbc
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M clang/include/clang/CIR/Dialect/IR/CIRAttrs.td
M clang/include/clang/CIR/Dialect/IR/CIRDialect.td
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/lib/CIR/CodeGen/CIRGenExprCXX.cpp
M clang/lib/CIR/Dialect/Transforms/CXXABILowering.cpp
M clang/test/CIR/Analysis/alias-analysis-modref.cir
M clang/test/CIR/Analysis/alias-analysis-underlying-object.cir
M clang/test/CIR/CodeGen/alignment.c
M clang/test/CIR/CodeGen/atomic.c
M clang/test/CIR/CodeGen/bitint-memory.c
M clang/test/CIR/CodeGen/bitint-record-layout.c
M clang/test/CIR/CodeGen/bitint-wide-be.c
M clang/test/CIR/CodeGen/bitint-wide.c
M clang/test/CIR/CodeGen/bitint.c
M clang/test/CIR/CodeGen/builtin-call.cpp
M clang/test/CIR/CodeGen/compound_literal.c
M clang/test/CIR/CodeGen/delete-array-aligned.cpp
M clang/test/CIR/CodeGen/delete-array-overaligned-cookie.cpp
M clang/test/CIR/CodeGen/delete-array-throwing-dtor.cpp
M clang/test/CIR/CodeGen/delete-array-unsized-dtor.cpp
M clang/test/CIR/CodeGen/delete-array.cpp
M clang/test/CIR/CodeGen/empty-union.cpp
M clang/test/CIR/CodeGen/fixed-point-literal.c
M clang/test/CIR/CodeGen/fp-contract.c
M clang/test/CIR/CodeGen/global-const-alignment.cpp
M clang/test/CIR/CodeGen/global-init-fenv.cpp
M clang/test/CIR/CodeGen/global-section.c
M clang/test/CIR/CodeGen/global-tls-dyn-init.cpp
M clang/test/CIR/CodeGen/globals.cpp
M clang/test/CIR/CodeGen/lambda.cpp
M clang/test/CIR/CodeGen/local-const-aggregate-name-clash.cpp
M clang/test/CIR/CodeGen/no-odr-use.cpp
M clang/test/CIR/CodeGen/non-odr-use-non-ref.cpp
M clang/test/CIR/CodeGen/nonzeroinit-struct.cpp
M clang/test/CIR/CodeGen/paren-list-agg-init.cpp
M clang/test/CIR/CodeGen/pointer-to-data-member-indirect-field.cpp
M clang/test/CIR/CodeGen/pointer-width-32bit.cpp
M clang/test/CIR/CodeGen/pragma-fenv_access.c
M clang/test/CIR/CodeGen/predefined-expr.c
M clang/test/CIR/CodeGen/source-loc.cpp
M clang/test/CIR/CodeGen/static-local-in-ctor.cpp
M clang/test/CIR/CodeGen/static-local-info.cpp
M clang/test/CIR/CodeGen/tls-model.cpp
M clang/test/CIR/CodeGen/union-agg-init.c
M clang/test/CIR/CodeGen/vbase.cpp
M clang/test/CIR/CodeGen/vector-strict-fp.cpp
M clang/test/CIR/CodeGen/vtt.cpp
M clang/test/CIR/CodeGenCUDA/address-spaces.cu
M clang/test/CIR/CodeGenCUDA/device-stub.cu
M clang/test/CIR/CodeGenCUDA/kernel-call.cu
M clang/test/CIR/CodeGenCXX/global-refs.cpp
M clang/test/CIR/CodeGenCXX/init-priority-attr.cpp
M clang/test/CIR/CodeGenCXX/vtable-linkage.cpp
M clang/test/CIR/CodeGenCXX/zero_init_bases.cpp
M clang/test/CIR/IR/attribute-visibility.cir
M clang/test/CIR/IR/fenv.cir
M clang/test/CIR/IR/global.cir
M clang/test/CIR/IR/invalid-cast.cir
M clang/test/CIR/IR/invalid-cmp.cir
M clang/test/CIR/IR/invalid-delete-array.cir
M clang/test/CIR/IR/invalid-static-local-info.cir
M clang/test/CIR/IR/invalid-static-local.cir
M clang/test/CIR/IR/invalid-tls.cir
M clang/test/CIR/IR/invalid-vtable.cir
M clang/test/CIR/IR/static-local-info.cir
M clang/test/CIR/IR/static-local.cir
M clang/test/CIR/IR/string-trailing-zeros.cir
M clang/test/CIR/IR/var-registration.cir
M clang/test/CIR/IR/vtable-addrpt.cir
M clang/test/CIR/IR/vtable-attr.cir
M clang/test/CIR/IR/vtt-addrpoint.cir
M clang/test/CIR/Lowering/call-llvm-intrinsic.cir
M clang/test/CIR/Lowering/fenv.cir
M clang/test/CIR/Lowering/vtt-addrpoint.cir
M clang/test/CIR/Transforms/vector-cmp-fold.cir
M clang/unittests/CIR/FenvOpTest.cpp
Log Message:
-----------
Make CIR assembly formats strict properties compatible (#226600)
Bind inherent attributes explicitly in CIR operation formats and update
assembly tests for the resulting syntax.
Assisted-by: Codex
Commit: 2fa97ac9671c00e8ddff5cc85a82ff84cebaf392
https://github.com/llvm/llvm-project/commit/2fa97ac9671c00e8ddff5cc85a82ff84cebaf392
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M clang/lib/AST/ByteCode/ByteCodeEmitter.h
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ByteCode/Context.cpp
M clang/lib/AST/ByteCode/Disasm.cpp
M clang/lib/AST/ByteCode/EvalEmitter.cpp
M clang/lib/AST/ByteCode/EvalEmitter.h
M clang/lib/AST/ByteCode/EvaluationResult.cpp
M clang/lib/AST/ByteCode/EvaluationResult.h
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/InterpBuiltinObjectSize.cpp
M clang/lib/AST/ByteCode/Pointer.cpp
M clang/lib/AST/ByteCode/Pointer.h
M clang/lib/AST/ExprConstShared.h
M clang/lib/AST/ExprConstant.cpp
M clang/test/AST/ByteCode/builtin-functions.cpp
M clang/test/AST/ByteCode/codegen-constexpr-unknown.cpp
M clang/test/AST/ByteCode/references.cpp
M clang/test/CodeGenCXX/global-init.cpp
M clang/test/SemaCXX/PR19955.cpp
M clang/test/SemaCXX/cxx2c-expansion-stmts.cpp
Log Message:
-----------
Reapply "[clang][bytecode] Stop relying on `CheckEvaluationResult()` … (#226879)
…(… (#226637)
This reverts commit e0316c1b4762263caa49e3c41ddde752a2b6b775.
This time we also check `Pointee.isInitialized()` in
`PtrView::isInitialized()` to catch cases where we call `invokeDtor()`
on a Block.
Commit: b5cae89e8463dd397960f8a37bb877a06306c0f4
https://github.com/llvm/llvm-project/commit/b5cae89e8463dd397960f8a37bb877a06306c0f4
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M llvm/include/llvm/Transforms/Vectorize/SLPVectorizer.h
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/PhaseOrdering/AArch64/reassociate-fma-pairs.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/extracts-folded-into-fmul-users-no-credit.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/fadd-with-gathered-fmul-operands.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/fma-candidates-after-store-chains.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/fma-chain-no-alt-node-reduction.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/fmul-constant-lane-fmuladd-combine.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/hor-fp-reduction-instcount.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/loop-accumulator-reduction.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/reduction-root-multi-use-fma.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/vec3-reorder-reshuffle.ll
M llvm/test/Transforms/SLPVectorizer/AMDGPU/cross-block-fmul-fadd.ll
M llvm/test/Transforms/SLPVectorizer/NVPTX/ordered-reduction-fma-fusion.ll
M llvm/test/Transforms/SLPVectorizer/X86/fmul-fused-into-scalar-fadd.ll
M llvm/test/Transforms/SLPVectorizer/X86/fsub-fmul-rhs-combine.ll
M llvm/test/Transforms/SLPVectorizer/X86/slp-fma-loss-ordered.ll
M llvm/test/Transforms/SLPVectorizer/consecutive-access.ll
Log Message:
-----------
[SLP]Fix fmul/fadd fusion costs and retry FMA seeds after all blocks
Fix the cost for the scalar of fmul+fadd pairs: fused fmul lanes add
the full fmul cost, fadd lanes with gathered fmuls were costed as
fmuladd, and the FMulAdd combine missed fmuls in the second operand,
c - a*b and constant lanes. Cost fused fmul lanes at (fmuladd - fadd),
such fadd lanes at (fmuladd - fmul), form the combine for either
operand, and treat a multi-use reduction root as fused. Extract nodes
take no credit for extracts the target folds into their users.
Reviewers: RKSimon, bababuck, MrSidims
Pull Request: https://github.com/llvm/llvm-project/pull/226117
Commit: 74f859b9d46e480fe43d7b904b1e80efb8a331a2
https://github.com/llvm/llvm-project/commit/74f859b9d46e480fe43d7b904b1e80efb8a331a2
Author: Aayush Mainali <aayushmainali.codes at gmail.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M clang-tools-extra/clang-tidy/readability/TrailingCommaCheck.cpp
M clang-tools-extra/docs/ReleaseNotes.md
M clang-tools-extra/test/clang-tidy/checkers/readability/trailing-comma-cxx11.cpp
M clang-tools-extra/test/clang-tidy/checkers/readability/trailing-comma.cpp
Log Message:
-----------
[clang-tidy] Fix readability-trailing-comma false positive on #endif (#219634)
The `readability-trailing-comma` check looks at the token immediately
before an enum's closing brace to decide whether a trailing comma is
present. When the last enumerators are wrapped in `#ifdef` / `#else` /
`#endif`, that token is the directive identifier `endif`, so the check
reports a missing comma and `-fix` inserts `,` after `#endif`. That is
outside the enumerator list and corrupts the source even when every
enumerator already has a trailing comma.
Skip the diagnostic when the token before `}` is a preprocessor
directive (`#` or a token preceded by `#`). An enumerator whose name
happens to be `endif` is still diagnosed, because it is not preceded by
`#`.
Fixes #218957
Commit: d789b97789e1a220d3e8b58c76bdd0cb495c3736
https://github.com/llvm/llvm-project/commit/d789b97789e1a220d3e8b58c76bdd0cb495c3736
Author: Haohai Wen <haohai.wen at intel.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M llvm/include/llvm/ObjectYAML/COFFYAML.h
M llvm/lib/ObjectYAML/COFFEmitter.cpp
M llvm/lib/ObjectYAML/COFFYAML.cpp
A llvm/test/tools/yaml2obj/COFF/bb-addr-map-pgo-analysis-map.yaml
A llvm/test/tools/yaml2obj/COFF/bb-addr-map.yaml
A llvm/test/tools/yaml2obj/COFF/section-semantic-content.yaml
Log Message:
-----------
[yaml2obj][COFF] Add BBAddrMap support to yaml2coff (#224504)
Commit: b3f84790c4e5092745b22525bd249146ccf2ebad
https://github.com/llvm/llvm-project/commit/b3f84790c4e5092745b22525bd249146ccf2ebad
Author: Haohai Wen <haohai.wen at intel.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
Log Message:
-----------
[yaml2obj][COFF] Add BBAddrMap support to yaml2coff (#224504)
Teach yaml2coff to emit .llvm_bb_addr_map sections using the same
BBAddrMap YAML schema as yaml2elf.
Treat Entries as the complete section payload and reject its use with
SectionData, StructuredData, or SizeOfRawData.
Commit: 30ffad255bbde381abe1146446a6974d0b27ff37
https://github.com/llvm/llvm-project/commit/30ffad255bbde381abe1146446a6974d0b27ff37
Author: forking-google-bazel-bot[bot] <265904573+forking-google-bazel-bot[bot]@users.noreply.github.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[Bazel] Fixes 2a96d57 (#226932)
This fixes 2a96d5737524012839e786699a0b327f22d1cfee (#217338).
Buildkite error link:
https://buildkite.com/llvm-project/upstream-bazel/builds?commit=2a96d5737524012839e786699a0b327f22d1cfee
Co-authored-by: Google Bazel Bot <google-bazel-bot at google.com>
Commit: 271cb24b4d3831c719bc8282748f8266d3d08598
https://github.com/llvm/llvm-project/commit/271cb24b4d3831c719bc8282748f8266d3d08598
Author: Mirko Brkušanin <Mirko.Brkusanin at amd.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
M llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
M llvm/lib/Target/AMDGPU/GCNSubtarget.cpp
M llvm/test/CodeGen/AMDGPU/dvgpr-vgpr-count-propagation-direct-chain.ll
M llvm/test/CodeGen/AMDGPU/dvgpr-vgpr-count-propagation.ll
A llvm/test/CodeGen/AMDGPU/dynamic-vgpr-entry-register-pressure.ll
A llvm/test/CodeGen/AMDGPU/dynamic-vgpr-entry-vgpr-limit.ll
M llvm/test/CodeGen/AMDGPU/dynamic-vgpr-reserve-stack-for-cwsr.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-vgpr-ratio.ll
Log Message:
-----------
[AMDGPU] Limit DVGPR entry function max VGPRs to block size (#226242)
AMDGPUPromoteAlloca.cpp has its own version of `getMaxVGPRs` so limit is
enforced in two places.
Co-Authored-By: Claude
Commit: 20913cfb73ee109c0ad4e9cb298e2c1a0595fb0b
https://github.com/llvm/llvm-project/commit/20913cfb73ee109c0ad4e9cb298e2c1a0595fb0b
Author: Igor Wodiany <igor.wodiany at amd.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M llvm/lib/DebugInfo/PDB/Native/LinePrinter.cpp
Log Message:
-----------
[PDB] Prevent potential overflow when calculating `Base` in `formatMsfStreamData` (#224662)
The `Base` is calculated as a product of two 32-bits number but the
results is assigned to a 64-bit value. By casting one of the operands to
64-bit, the multiplication is done using the whole width of the `Base`
variable, preventing a potential overflow. This fixes an issue reported
by a CodeQL scan.
Commit: 26f6f833e6b11db16003fe6033049b9a6f615019
https://github.com/llvm/llvm-project/commit/26f6f833e6b11db16003fe6033049b9a6f615019
Author: David Green <david.green at arm.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/test/CodeGen/AArch64/add.ll
M llvm/test/CodeGen/AArch64/andorxor.ll
M llvm/test/CodeGen/AArch64/arm64-rev.ll
M llvm/test/CodeGen/AArch64/arm64-storebytesmerge.ll
M llvm/test/CodeGen/AArch64/bitcast.ll
M llvm/test/CodeGen/AArch64/ctlz.ll
M llvm/test/CodeGen/AArch64/ctpop.ll
M llvm/test/CodeGen/AArch64/cttz.ll
M llvm/test/CodeGen/AArch64/ldst-opt.ll
M llvm/test/CodeGen/AArch64/lowmaskedlanes.ll
M llvm/test/CodeGen/AArch64/mul.ll
M llvm/test/CodeGen/AArch64/neon-rshrn.ll
M llvm/test/CodeGen/AArch64/neon-truncstore.ll
M llvm/test/CodeGen/AArch64/sadd_sat_vec.ll
M llvm/test/CodeGen/AArch64/shufflevector.ll
M llvm/test/CodeGen/AArch64/ssub_sat_vec.ll
M llvm/test/CodeGen/AArch64/store.ll
M llvm/test/CodeGen/AArch64/sub.ll
M llvm/test/CodeGen/AArch64/uadd_sat_vec.ll
M llvm/test/CodeGen/AArch64/usub_sat_vec.ll
M llvm/test/CodeGen/AArch64/vec3-loads-ext-trunc-stores.ll
Log Message:
-----------
[AArch64] Add custom v2i32->v2i16 store lowering. (#223659)
This extends the existing v4i16->v4i8 lowering to handle v2i32->v2i16
stores too, which in general helps keep the number of instructions down.
Commit: 21277fd5587ad8055b47d5684d6a313e09860325
https://github.com/llvm/llvm-project/commit/21277fd5587ad8055b47d5684d6a313e09860325
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M libcxx/test/benchmarks/containers/string.bench.cpp
Log Message:
-----------
[libc++] Add a benchmark for string::append (#226559)
Commit: 83c3a2d69a927491bf9785ad5012a8db6eeb7e1a
https://github.com/llvm/llvm-project/commit/83c3a2d69a927491bf9785ad5012a8db6eeb7e1a
Author: Alex Duran <alejandro.duran at intel.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M offload/plugins-nextgen/level_zero/src/L0Program.cpp
A offload/test/offloading/shared_lib_global_var.c
Log Message:
-----------
[offload][l0] Execute dynamic linking for all formats (#226980)
Also do dynamic linking when necessary for Offload Binaries and SPIR-V
images and not just for the old ELF format.
Commit: 7eb87fc1e1126c6c064731c6e476ffccc6e5c490
https://github.com/llvm/llvm-project/commit/7eb87fc1e1126c6c064731c6e476ffccc6e5c490
Author: David Spickett <david.spickett at arm.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M lldb/test/API/api/multithreaded/common.h
Log Message:
-----------
[lldb][test] Simplify multithreaded_queue (#226979)
This makes it easier to see how the timeout is applied in pop.
push now releases the mutex before notifying, where before the watchers
would have to wait for push to return. Likely not going to make anything
much faster, but it makes a bit more sense. Finish adding the new item,
then notify.
Commit: 3eda2aebadd430199a1d588b6b22c966af5356d5
https://github.com/llvm/llvm-project/commit/3eda2aebadd430199a1d588b6b22c966af5356d5
Author: Raphael Isemann <rise at apple.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M lldb/test/API/python_api/event/TestEvents.py
Log Message:
-----------
[lldb][test] Disable TestEvents.py (#226486)
This test is flaky on Linux, macOS and Windows. The usual failure on
macOS is as follows:
```
FAIL: test_shadow_listener (TestEvents.EventAPITestCase)
----------------------------------------------------------------------
Traceback (most recent call last):
llvm-project/lldb/packages/Python/lldbsuite/test/decorators.py", line 801, in wrapper
func(*args, **kwargs)
llvm-project/lldb/test/API/python_api/event/TestEvents.py", line 485, in test_shadow_listener
state, restarted = self.wait_for_next_event(None, False)
llvm-project/lldb/test/API/python_api/event/TestEvents.py", line 346, in wait_for_next_event
self.assertEqual(
>>> AssertionError: 2 != 3 : matching stop hook
Config=arm64-/Users/ec2-user/jenkins/workspace/llvm.org/lldb-cmake-matrix/lldb-build/bin/clang
----------------------------------------------------------------------
```
The test is already skipped on all platforms except macOS. This patch
skips it on all platforms.
Commit: e3cf33561946626500b3a3684430ce5da61d2882
https://github.com/llvm/llvm-project/commit/e3cf33561946626500b3a3684430ce5da61d2882
Author: Andreas Jonson <andjo403 at hotmail.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
A llvm/test/Transforms/InstCombine/pr226504-commuted.ll
A llvm/test/Transforms/InstCombine/pr226504.ll
Log Message:
-----------
[InstCombine] Fix miscompilation in sinkNotIntoOtherHandOfLogicalOp (#226783)
Consider the following: `or X, (not (not X))`
sinkNotIntoOtherHandOfLogicalOp calls `freelyInvert(X)` but as X is used
in the not this call result in the new instruction is `and (not X), (not
(not X)) -> and (not X), X` instead of the expected `and (not X), (not
X)`
fixes https://github.com/llvm/llvm-project/issues/226504
Commit: b5a51c5b670728f0b3bcb3d31bc063821cbcfb4b
https://github.com/llvm/llvm-project/commit/b5a51c5b670728f0b3bcb3d31bc063821cbcfb4b
Author: Alexey Samsonov <vonosmas at gmail.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M libc/include/fcntl.yaml
M libc/include/llvm-libc-macros/linux/fcntl-macros.h
Log Message:
-----------
[libc] Add a few missing fcntl.h macro. (#226810)
* Add a few POSIX-specified symbolic constants to `<fcntl.h>`:
`O_RSYNC`,
`AT_SYMLINK_FOLLOW`, and `F_DUPFD_CLOEXEC`.
* Don't add `_CLOFORK` variants, since those are not supported by Linux.
* List the constants in the `fcntl.yaml` file for posterity.
Commit: c226f8dec63924b6fef645f5818eb42f52ffd1fe
https://github.com/llvm/llvm-project/commit/c226f8dec63924b6fef645f5818eb42f52ffd1fe
Author: MMS IT GmbH <info at mms-it.ch>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M llvm/lib/Target/SystemZ/SystemZFrameLowering.cpp
A llvm/test/CodeGen/SystemZ/zos-frame-callee-saved.ll
M llvm/test/CodeGen/SystemZ/zos-frameaddr.ll
M llvm/test/CodeGen/SystemZ/zos-ret-addr.ll
Log Message:
-----------
[SystemZ][z/OS] Allocate a stack frame when callee-saved registers are saved (#226681)
On z/OS (XPLINK64), a function without calls and without stack objects
that uses callee-saved registers got a stack size of 0. No stack frame
was allocated, so `STMG` stored the registers relative to the unchanged
stack pointer, i.e. into the register save area of the caller's DSA,
overwriting the caller's saved return address. Only skip the frame when
there is nothing to save.
Two existing tests (`zos-ret-addr.ll`, `zos-frameaddr.ll`) encoded this
store into the caller's frame and are updated; the values returned by
`llvm.returnaddress`/`llvm.frameaddress` are unchanged (the old stack
pointer is still read from offset 2048 of the current frame). New test
`zos-frame-callee-saved.ll`.
Found with GMP 6.3.0 on z/OS 3.1 (`mpn_mul_1`): code after the call ran
twice, then S0C4/S0C6. With this change GMP works.
Tests: `llvm-lit test/CodeGen/SystemZ test/MC/SystemZ test/MC/GOFF`
passes (1304 passed, 19 unsupported).
Fixes #226657.
Assisted-by: Claude Code (Anthropic)
🤖 Generated with [Claude Code](https://claude.com/claude-code)
Commit: b4bccce2099984c74e5b29d767b586cb7b6e8dd6
https://github.com/llvm/llvm-project/commit/b4bccce2099984c74e5b29d767b586cb7b6e8dd6
Author: Alex Strelnikov <strel at google.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M libc/src/__support/printf_core/float_dec_converter.h
M libc/src/__support/printf_core/float_dec_converter_limited.h
M libc/src/__support/printf_core/float_hex_converter.h
M libc/src/__support/printf_core/float_inf_nan_converter.h
M libc/src/stdlib/str_from_util.h
M libc/src/stdlib/strfromd.cpp
M libc/src/stdlib/strfromf.cpp
M libc/src/stdlib/strfroml.cpp
M libc/test/src/stdlib/strfromf_test.cpp
Log Message:
-----------
[libc] Fix strfromf handling inf/nan. (#225805)
The root cause of #217708 is primarily in
libc/src/stdlib/str_from_util.h, which splits the utilities into
1. `parse_from_format()` which takes in a floating point and returns a
`FormatSection`, and
2. `strfromfloat_convert()`, which takes in the `FormatSection` and not
the floating point value.
`parse_from_format()` [does special case
handling](https://github.com/llvm/llvm-project/blob/35fe7e14ecb4e50182fe93123e1876824d14bb94/libc/src/stdlib/str_from_util.h#L41-L49)
for `float`: it must place a `double` into `FormatSection::conv_val_raw`
when working with `%a` or `%A`. `strfromfloat_convert()` extracts the
bits from `conv_val_raw` to create `fputil::FPBits<T>`, but it [always
uses the template
type](https://github.com/llvm/llvm-project/blob/35fe7e14ecb4e50182fe93123e1876824d14bb94/libc/src/stdlib/str_from_util.h#L115),
effectively creating type confusion when those bits are passed to
`convert_float_hex_exp()`.
An additional challenge in strfrom* functions is that the format string
naturally does not need or support a length modifier as in printf
functions. This is mostly a non-issue as `strfromfloat_convert()` is
templated on floating point type, and calls the "typed" conversion
functions. However, there are no templated / typed versions of
`convert_float_hex_exp()` or `convert_inf_nan()`. These two functions
currently depend on the value of `FormatSection::length_modifier` to
extract the correct type out of `FormatSection::conv_val_raw`:
[`convert_float_hex_exp()`](https://github.com/llvm/llvm-project/blob/35fe7e14ecb4e50182fe93123e1876824d14bb94/libc/src/__support/printf_core/float_hex_converter.h#L70-L86)
and
[`convert_inf_nan()`](https://github.com/llvm/llvm-project/blob/35fe7e14ecb4e50182fe93123e1876824d14bb94/libc/src/__support/printf_core/float_inf_nan_converter.h#L46-L60).
This coupling interacts with the type confusion created in
`strfromfloat_convert()`, and forces the implementation of `strfroml()`
to [manually set the
`length_modifier`](https://github.com/llvm/llvm-project/blob/35fe7e14ecb4e50182fe93123e1876824d14bb94/libc/src/stdlib/strfroml.cpp#L26-L28).
The fix in this PR:
1. Merges the two str_from_float.h utility functions to remove the type
confusion.
2. Lifts the dependency on `FormatSection::length_modifier` and
`conv_val_raw` out of `convert_float_hex_exp()` and `convert_inf_nan()`;
similarly to how the "typed" conversion functions currently work, but
without templating on float point.
3. Updates some conversion function names to mark which ones only handle
finite floating point values.
This allows `strfroml()` to not manually set the length modifier. It
also enables `strfromf128()` to be added in a straightforward
implementation, because it will not need to depend on the existence of
`LengthModifier::Q`, controlled in part by
`LIBC_COPT_PRINTF_NO_CONVERT_FLOAT128`. In the future, it may be good
to separate `conv_val_raw` out of `FormatSection` to be its own argument
to non-typed functions.
Fixes #217708.
Commit: 18763d854a42a4db9c49a1434c4f48e6467714ed
https://github.com/llvm/llvm-project/commit/18763d854a42a4db9c49a1434c4f48e6467714ed
Author: aokblast <aokblast at FreeBSD.org>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
A llvm/test/tools/llvm-strings/chunk-boundary.test
M llvm/tools/llvm-strings/llvm-strings.cpp
Log Message:
-----------
[llvm-strings] Use small buffer instead of reading whole file (#163073)
Commit: 5961b1283fab21a6836be87cbc693c8c81089b83
https://github.com/llvm/llvm-project/commit/5961b1283fab21a6836be87cbc693c8c81089b83
Author: Alex MacLean <amaclean at nvidia.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M clang/lib/CodeGen/TargetBuiltins/NVPTX.cpp
M clang/test/CodeGen/builtins-nvptx.c
M llvm/include/llvm/IR/IntrinsicsNVVM.td
M llvm/lib/IR/AutoUpgrade.cpp
M llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
M llvm/test/Assembler/auto_upgrade_nvvm_intrinsics.ll
M llvm/test/CodeGen/NVPTX/mulhi-intrins.ll
Log Message:
-----------
[NVPTX] Auto-upgrade NVVM mulhi intrinsics to generic mulh (#226578)
Commit: e721bde41d23ee1bc8c6f0413c1f7da8af388171
https://github.com/llvm/llvm-project/commit/e721bde41d23ee1bc8c6f0413c1f7da8af388171
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/arm64-callingconv-ios.ll
M llvm/test/CodeGen/AArch64/GlobalISel/arm64-callingconv.ll
M llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-switch.ll
M llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
M llvm/test/CodeGen/AArch64/GlobalISel/arm64-this-return.ll
M llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-alias.ll
M llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-ifunc.ll
M llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-signext.ll
M llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-sret-demotion.ll
M llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-vectors.ll
M llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-zeroext.ll
M llvm/test/CodeGen/AArch64/GlobalISel/call-translator-tail-call-sret.ll
M llvm/test/CodeGen/AArch64/GlobalISel/call-translator-tail-call-weak.ll
M llvm/test/CodeGen/AArch64/GlobalISel/call-translator-tail-call.ll
M llvm/test/CodeGen/AArch64/GlobalISel/call-translator.ll
M llvm/test/CodeGen/AArch64/GlobalISel/combiner-load-store-indexing.ll
M llvm/test/CodeGen/AArch64/GlobalISel/integration-shuffle-vector.ll
M llvm/test/CodeGen/AArch64/GlobalISel/invoke-region.ll
M llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-arguments.ll
M llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-delayed-stack-protector.ll
M llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-exceptions.ll
M llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-hoisted-constants.ll
M llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-localescape.ll
M llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-stack-protector-trap-unreachable.ll
M llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-unreachable.ll
M llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-unwind-inline-asm.ll
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-atan2.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-bzero.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-exceptions.ll
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-exp.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-fexp2.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-fmaxnum.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-fminnum.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-fpenv.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-fpmode.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-memcpy-et-al.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-memlib-debug-loc.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-modf.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-pow.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-rem.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-s128-div.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-sin.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-sinh.mir
Log Message:
-----------
AArch64: Mark the LR def of GlobalISel calls dead (#226256)
In SelectionDAG InstrEmitter would have marked this dead.
Co-authored-by: Claude Opus 5 <noreply at anthropic.com>
Commit: 47d9dee08242cb69c284fa47a642e4af978f911f
https://github.com/llvm/llvm-project/commit/47d9dee08242cb69c284fa47a642e4af978f911f
Author: David Spickett <david.spickett at arm.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M lldb/test/API/api/multithreaded/common.h
M lldb/test/API/api/multithreaded/test_listener_event_description.cpp
M lldb/test/API/api/multithreaded/test_listener_event_process_state.cpp
M lldb/test/API/api/multithreaded/test_listener_resume.cpp
Log Message:
-----------
[lldb][test][NFC] Set multithreaded_queue pop timeout in one place (#226988)
All callers of pop were passing 5 seconds. I don't forsee us needing to
change it per caller either, so just hardcode it in pop().
Commit: 63cb4e37ce2caf24426c08cf54c11e44f80d1fb0
https://github.com/llvm/llvm-project/commit/63cb4e37ce2caf24426c08cf54c11e44f80d1fb0
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M .github/workflows/libcxx-benchmark-commit.yml
A .github/workflows/libcxx-benchmark-libstdcxx.yml
M libcxx/utils/ci/lnt/README.md
M libcxx/utils/ci/lnt/machines.json
A libcxx/utils/ci/lnt/run-libstdcxx-benchmarks
R libcxx/utils/ci/lnt/schema.yaml
A libcxx/utils/ci/lnt/schemas/libcxx.yaml
A libcxx/utils/ci/lnt/schemas/libstdcxx.yaml
Log Message:
-----------
[libc++] Use a self-contained job to run libstdc++ benchmarks (#226985)
After trying to retrofit libstdc++ benchmarking into our existing libc++
pipeline, I am giving up and setting up a self-contained job to do it
instead. It's much simpler as we can just run exactly what we need
instead of fighting to decouple libc++ specific logic from the libc++
benchmarking pipeline.
Various parts can still be extracted (e.g. gathering hardware
information for LNT reports, reading machines.json, etc) and will be
extracted in future iterations.
Also, add the corresponding libstdcxx LNT test suite schema so we can
start submitting results to it.
Commit: 0d429d44791ec27e40f08b3e9d51b743ee7fd870
https://github.com/llvm/llvm-project/commit/0d429d44791ec27e40f08b3e9d51b743ee7fd870
Author: Andrey Grabezhnoy <andrey.grabezhnoy at intel.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Scalar/LICM.cpp
M llvm/test/Transforms/LICM/hoist-binop.ll
Log Message:
-----------
[LICM] Preserve nsw when reassociating integer adds (#221210)
When LICM reassociates (LV + C1) + C2 into LV + (C1 + C2), it currently
drops nsw unless both original additions also have nuw.
After applying the usual OverflowTracking flags, set nsw directly on
both generated additions when both original additions have nsw and value
tracking proves that C1 + C2 cannot overflow in signed arithmetic. This
enables hoistAdd() later in the same LICM run.
Tests cover constant operands, scalar and vector operands proven safe
through known bits, operands constrained by dominating assumptions, and
the case where only the outer addition has nsw.
[Alive2 proof](https://alive2.llvm.org/ce/z/DC2dWY) of the
reassociation. The llvm.assume models the separately established fact
that C1 + C2 cannot overflow in signed arithmetic. The public example
uses i8 to finish quickly; the same proof also succeeds locally with
i32.
Fixes #220897
Commit: 92c62f30ec4a9d9ec9786aa403922fad7d536ae2
https://github.com/llvm/llvm-project/commit/92c62f30ec4a9d9ec9786aa403922fad7d536ae2
Author: Pedro da Rosa Pinheiro <pedarosa04 at gmail.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenOpenMPClause.cpp
M clang/lib/CIR/CodeGen/CIRGenOpenMPClause.h
M clang/lib/CIR/CodeGen/CIRGenStmtOpenMP.cpp
M clang/test/CIR/CodeGenOpenMP/parallel.c
Log Message:
-----------
[CIR][OpenMP] Implement lowering for the 'num_threads' clause for 'parallel' directive (#202466)
Implementing the emission of the "single-dimension" `num_threads` clause
for the `#pragma omp parallel` directive. The clause just accepts an
integer value and creates the `numThreadsVars` `llvm::SmallVector` with
that single value (representing a single num_thread dimension).
Based myself off of PR #172501 that implements the lowering for the
`proc_bind` clause.
Following this, I'll work on a PR to adapt CIR to deal with the
"dimensions" modifier introduced in openmp 6.1 (as also tackled by PR
#171767).
### Evidence:
Output of: `python3 build/bin/llvm-lit -sv
clang/test/CIR/CodeGenOpenMP/parallel.c`
```
llvm-lit: /home/pedro/dev/projects/my-llvm-project/llvm/utils/lit/lit/llvm/config.py:569: note: using clang: /home/pedro/dev/projects/my-llvm-project/build/bin/clang
Testing Time: 0.09s
Total Discovered Tests: 1
Passed: 1 (100.00%)
```
Commit: df11f86c50a1399c7af2816facd330988c19b32b
https://github.com/llvm/llvm-project/commit/df11f86c50a1399c7af2816facd330988c19b32b
Author: aokblast <aokblast at FreeBSD.org>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
Log Message:
-----------
[llvm-strings] Use small buffer instead of reading whole file (#163073)
To prevent large memory footprint, we use small buffer and a seperated
string to print. This can largely reduce the memory consumption when
processing.
In the following example, the test file is a clang-24 debug build
binary. Each runs with three rounds and use the median number as a
result.
reading from stdin:
blast at localhost ~/o/l/build (main)> time cat ./bin/clang-24 |
./bin/llvm-strings > /dev/null
Executed in 3.94 secs fish external
usr time 3.03 secs 2.27 millis 3.03 secs
sys time 1.43 secs 0.00 millis 1.43 secs
Memory usage is 3.784 GB from valgrind massif.
reading from file:
blast at localhost ~/o/l/build (main)> time ./bin/llvm-strings
./bin/clang-24 > /dev/null
Executed in 2.99 secs fish external
usr time 2.91 secs 1.14 millis 2.91 secs
sys time 0.08 secs 0.00 millis 0.08 secs
Memory usage is 1.802 GB from valgrind massif.
This patch:
reading from stdin:
blast at localhost ~/o/l/build (strings/fix_oom)> time cat ./bin/clang-24 |
./bin/llvm-strings > /dev/null
Executed in 2.53 secs fish external
usr time 2.28 secs 0.00 millis 2.28 secs
sys time 0.34 secs 1.33 millis 0.33 secs
Memory usage is 78.03 KB from valgrind massif.
reading from file:
blast at localhost ~/o/l/build (strings/fix_oom)> time ./bin/llvm-strings
./bin/clang-24 > /dev/null
Executed in 2.57 secs fish external
usr time 2.37 secs 641.00 micros 2.37 secs
sys time 0.20 secs 206.00 micros 0.20 secs
Memory usage is 78.13 KB from valgrind massif.
Commit: fdcab03ed53bfa5842f6af464d3ffd50a19e3188
https://github.com/llvm/llvm-project/commit/fdcab03ed53bfa5842f6af464d3ffd50a19e3188
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M .github/workflows/libcxx-benchmark-libstdcxx.yml
Log Message:
-----------
[libc++] Update GHA pins in libcxx-benchmark-libstdcxx.yml (#227003)
This workflow landed with older versions of actions/checkout and
actions/setup-python than the (recently updated) versions used by other
workflows.
Commit: e1941f8db3ab710e4ff3eb6b6fb32d4c8eb79b82
https://github.com/llvm/llvm-project/commit/e1941f8db3ab710e4ff3eb6b6fb32d4c8eb79b82
Author: Jackson Stogel <jtstogel at gmail.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/libc_build_rules.bzl
Log Message:
-----------
[bazel][libc] Refactor to allow copts under full-build mode (#226851)
This PR moves away from having sets of predefined groups of `copts` to
just directly listing `copts` for each target. The idea behind
[`copt_sets`](https://github.com/llvm/llvm-project/blob/dbde1428562362792d85cb9bbb58415f1b21cb48/utils/bazel/llvm-project-overlay/libc/libc_build_rules.bzl#L80)
in `_libc_library` was to restrict the different ways `copts` could be
defined, since `libc_release_library` doesn't respect `copts` and in
general having fewer combinations of `copts` allows for using fewer
`cc_library` targets. This PR allows `copts` to only be configurable if
the target is full-build only, so at least overlay libc function are
still more restricted.
Commit: a401e6562a56a21c6c8f0844d8b8bf9f270bf827
https://github.com/llvm/llvm-project/commit/a401e6562a56a21c6c8f0844d8b8bf9f270bf827
Author: Jackson Stogel <jtstogel at gmail.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/startup/linux/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/startup/linux/x86_64/BUILD.bazel
Log Message:
-----------
[bazel] Port 4faf0ae, 15cff90, 9028ff14, 4057f8e4 (#226853)
Commit: d5275610d14e0911000246139dd537890f30831b
https://github.com/llvm/llvm-project/commit/d5275610d14e0911000246139dd537890f30831b
Author: Jiaxun Yang <jiaxun.yang at flygoat.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M llvm/lib/Target/Mips/MipsSEISelLowering.cpp
A llvm/test/CodeGen/Mips/msa/f16vec-shuffle.ll
Log Message:
-----------
[Mips] Promote MSA half-vector shuffles to integer vectors (#226105)
Promote v8f16 VECTOR_SHUFFLE operations to v8i16 to avoid expanding them
through EXTRACT_VECTOR_ELT and BUILD_VECTOR with an illegal scalar f16
type.
Fixes: #223618
Assisted-by: Codex # Tests
Commit: eb7f12adf832667a08debc0cdc65f762f615a99d
https://github.com/llvm/llvm-project/commit/eb7f12adf832667a08debc0cdc65f762f615a99d
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
A llvm/test/Transforms/SLPVectorizer/X86/narrowed-reduction-minbw-root.ll
Log Message:
-----------
[SLP]Fix narrowed leaf masks for demoted reduction root
The root of the narrowed-leaf reduction may be demoted and resized to the
reduction bitwidth of the wide reduction operations, while the masks are
built for the narrow leaves type, causes the crash.
Fixes https://github.com/llvm/llvm-project/pull/224919#issuecomment-5869787812
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/227009
Commit: 19b0091751d8c786c92e749a2d3404595edd359b
https://github.com/llvm/llvm-project/commit/19b0091751d8c786c92e749a2d3404595edd359b
Author: Jackson Stogel <jtstogel at gmail.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M .github/workflows/bazel-checks.yml
Log Message:
-----------
[Github] Add LLVM-libc's full-build to Bazel Checks workflow (#224749)
Adds a job to run LLVM-libc's full build test suite in Bazel via
`bazelisk test -- at llvm-project//libc:build_mode=full
@llvm-project//libc/...`. It is part of an effort to support LLVM-libc's
full build functionality in Bazel.
Commit: d87df4a9c352b275d89ef62f549c9225c0e51a51
https://github.com/llvm/llvm-project/commit/d87df4a9c352b275d89ef62f549c9225c0e51a51
Author: Will Hawkins <hawkinsw at obs.cr>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M llvm/lib/MC/MCDwarf.cpp
Log Message:
-----------
[MC][Dwarf] Support DWARF Version 6 in CIE (#226997)
According to the latest draft (as of 9/28/2026) of the V6 specification
of DWARF, section 8.24 states
"The value of the CIE version number is 4."
(PDF of the draft as of 9/28/2026 available at
https://snapshots.sourceware.org/dwarfstd/dwarf-spec/latest/dwarf6-20260920-2248.pdf).
Fixes #226994.
Commit: 9e34a621d761e73eeb7e4a1c62070d4fd5ce1d0a
https://github.com/llvm/llvm-project/commit/9e34a621d761e73eeb7e4a1c62070d4fd5ce1d0a
Author: Alex Duran <alejandro.duran at intel.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M offload/test/offloading/shared_lib_global_var.c
Log Message:
-----------
[offload][omp] Mark shlib_global_var test unsupported for AMD (#227008)
The shared library test introduced in #226980 seems to fail with the AMD
builbot so mark it unsupported for AMD GPUs.
Commit: c472da0034ee42666d626b57e026b54013649f8f
https://github.com/llvm/llvm-project/commit/c472da0034ee42666d626b57e026b54013649f8f
Author: Erich Keane <ekeane at nvidia.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M clang/lib/Sema/SemaOpenACCAtomic.cpp
M clang/test/SemaOpenACC/atomic-construct.cpp
Log Message:
-----------
[OpenACC] Fix diagnostic for atomic assignment (#227004)
Not sure how this escaped having code coverage, but a mis-placed closing
paren caused this to go very wrong :) This patch fixes it and adds the
original test case.
Fixes: #226905
Commit: f37b81afe94a1625ccd2b949d3bbfde78d612db9
https://github.com/llvm/llvm-project/commit/f37b81afe94a1625ccd2b949d3bbfde78d612db9
Author: Tuomas Kärnä <tuomas.karna at intel.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M mlir/include/mlir/Dialect/Linalg/TransformOps/LinalgTransformOps.td
M mlir/lib/Dialect/Linalg/TransformOps/LinalgTransformOps.cpp
M mlir/test/Dialect/Linalg/erase-unused-operands-and-results.mlir
M mlir/test/Dialect/Linalg/swap-extract-slice-with-fill.mlir
A mlir/test/Dialect/Linalg/td/erase-unused-operands-and-results.mlir
A mlir/test/Dialect/Linalg/td/swap-extract-slice-with-fill.mlir
R mlir/test/Dialect/Linalg/transform-op-swap-extract-slice-with-fill.mlir
M mlir/test/python/dialects/transform.py
Log Message:
-----------
[mlir][transform] add ApplyEraseUnusedOperandsAndResultsPatternsOp transform op (#225864)
The existing pattern
`mlir::linalg::populateEraseUnusedOperandsAndResultsPatterns` can remove
unused linalg op operands and/or results. At the moment, this pattern is
however only applicable via the `linalg-fuse-elementwise-ops` pass. This
PR exposes this pattern via a standalone transform dialect op.
Following the naming convention, the transform op is called
`transform.apply_patterns.linalg.erase_unused_operands_and_results`. The
the Python bindings expose it as
`transform.structured.apply_patterns_linalg_erase_unused_operands_and_results()`.
Assisted-by: Claude
Commit: 6e3c393f4a4dcf07b16df1f442883dcecf8bd011
https://github.com/llvm/llvm-project/commit/6e3c393f4a4dcf07b16df1f442883dcecf8bd011
Author: Phoebe Linck <phoebe.linck at hpe.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/lib/Semantics/check-omp-structure.cpp
R flang/test/Lower/OpenMP/Todo/taskwait-nowait.f90
A flang/test/Semantics/OpenMP/taskwait-nowait.f90
M llvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h
M llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
M mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
M mlir/test/Target/LLVMIR/openmp-taskwait-depend.mlir
M mlir/test/Target/LLVMIR/openmp-todo.mlir
Log Message:
-----------
[Flang][OpenMP] Support 'nowait' clause on taskwait (#219247)
No longer errors when a `nowait` clause is present on a `taskwait`, and
passes the info along to the runtime call `__kmpc_omp_taskwait_deps_51`.
Note that the runtime doesn't appear to use the `has_no_wait` parameter
at the moment, so `taskwait depend(...) nowait` will still block on
tasks it is dependent on. This should match the current Clang behavior.
Commit: 0203bc81f2869a8cf7e0d78759d2e40878d9afae
https://github.com/llvm/llvm-project/commit/0203bc81f2869a8cf7e0d78759d2e40878d9afae
Author: Charles Zablit <c_zablit at apple.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M lldb/packages/Python/lldbsuite/test/lldbinline.py
Log Message:
-----------
[lldb][test] Let inline tests opt into PDB debug info (#227001)
`MakeInlineTest` builds the test class with `type()`, so
`LLDBTestCaseFactory` only sees the attributes passed in that call.
Setting `TEST_WITH_PDB_DEBUG_INFO=True` on the returned class is too
late: the debug info variants have already been generated without pdb.
This patch adds a `test_with_pdb_debug_info` keyword argument that is
forwarded as the class attribute. It defaults to `False`, so existing
inline tests are unchanged.
rdar://188590558
Commit: 357a253eedf18fc8e113731a5e816741cdea20d9
https://github.com/llvm/llvm-project/commit/357a253eedf18fc8e113731a5e816741cdea20d9
Author: Charles Zablit <c_zablit at apple.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M lldb/packages/Python/lldbsuite/test/lldbtest.py
Log Message:
-----------
[lldb][test] Rename session logs through their extended-length path (#226976)
On Windows, renaming `Incomplete.log` to `<Prefix>_<test-name>.log`
makes the destination longer than the source, so it can cross `MAX_PATH`
where the source did not. `os.rename` then fails with `WinError 3` on a
file that exists, and a test that behaved correctly is reported as
unresolved:
```
FileNotFoundError: [WinError 3] The system cannot find the path specified:
'...\Incomplete.log' -> '...\ExpectedFailure_test_implementation_only_import_main_executable_resilient_no_library_module_dwarf_clang_swift.log'
```
Address the destination through `lldbutil.get_extended_windows_path`,
including the existence check and removal above it.
Commit: 5c20fe98552af8fdbcd7ce714c1fad1f1e731a65
https://github.com/llvm/llvm-project/commit/5c20fe98552af8fdbcd7ce714c1fad1f1e731a65
Author: Aditya Sinha <155882262+AdityaSinha149 at users.noreply.github.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M clang/include/clang/CodeGen/CodeGenAction.h
M clang/include/clang/Interpreter/Interpreter.h
M clang/lib/CodeGen/BackendConsumer.h
M clang/lib/CodeGen/CodeGenAction.cpp
M clang/lib/Interpreter/CMakeLists.txt
M clang/lib/Interpreter/DeviceOffload.cpp
M clang/lib/Interpreter/DeviceOffload.h
M clang/lib/Interpreter/Interpreter.cpp
M clang/unittests/Basic/CMakeLists.txt
A clang/unittests/Basic/TargetIDTest.cpp
Log Message:
-----------
releand "[clang-repl] Implement IncrementalHIPDeviceParser for HIP device compilation" (#226930)
This PR implements the IncrementalHIPDeviceParser. It takes each
incremental statement's device code and lowers it all the way to a
loadable HIP fat binary: linking the ROCm device libraries, running the
AMDGPU optimization/codegen pipeline, producing a .hsaco code object,
and embedding it as __hip_fatbin for the host runtime to register and
launch.
This PR only adds the parser class, wiring it into `Interpreter.cpp`;
the end-to-end tests will come in a follow-up.
Reland of #218337 (reverted in #226679 due to buildbot failures): the
original hit a build race where `DeviceOffload.cpp` could be compiled
before the tablegen-generated `AMDGPUTargetParserDef.inc` existed. Fixed
by adding `target_parser_gen `to `clang/lib/Interpreter/CMakeLists.txt`.
Assisted by Claude Opus 4.8
Commit: b550208f48a83a889910e50456003438fc81cd76
https://github.com/llvm/llvm-project/commit/b550208f48a83a889910e50456003438fc81cd76
Author: Folkert de Vries <folkert at folkertdev.nl>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M llvm/lib/Target/Mips/MipsMSAInstrInfo.td
M llvm/test/CodeGen/Mips/msa/bitcast.ll
Log Message:
-----------
[MIPS] add f16 vector bitcast patterns (#226287)
came across this failure
https://godbolt.org/z/YPK78ea76
```llvm
; -O0 -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=+msa,+fp64
define <4 x float> @f(<8 x half> %a) {
%b = bitcast <8 x half> %a to <4 x float>
ret <4 x float> %b
}
```
Gives
```
LLVM ERROR: Cannot select: 0x3b4ac900: v8f16 = bitcast 0x3b4acf90
0x3b4acf90: v4i32 = insert_vector_elt 0x3b4aceb0, 0x3b4ac5f0, Constant:i32<3>
0x3b4aceb0: v4i32 = insert_vector_elt 0x3b4acdd0, 0x3b4ac510, Constant:i32<2>
0x3b4acdd0: v4i32 = insert_vector_elt 0x3b4accf0, 0x3b4ac3c0, Constant:i32<1>
0x3b4accf0: v4i32 = insert_vector_elt undef:v4i32, 0x3b4ac2e0, Constant:i32<0>
0x3b4ac2e0: i32,ch = CopyFromReg 0x3b3c7b88, Register:i32 %1
0x3b4ac3c0: i32,ch = CopyFromReg 0x3b3c7b88, Register:i32 %2
0x3b4ac510: i32,ch = load<(load (s32) from %fixed-stack.1)> 0x3b3c7b88, FrameIndex:i32<-1>, poison:i32
0x3b4ac5f0: i32,ch = load<(load (s32) from %fixed-stack.0)> 0x3b3c7b88, FrameIndex:i32<-2>, poison:i32
In function: f
```
Just adding the patterns fixes that, and seems straightforward enough.
I'm using `fexupl` in the tests to force the bitcast, otherwise the
bitcast just gets optimized out (and just a store of the input vector
type happens).
This test should maybe start using the automatic update script?
Commit: 28acf4e5adf67b336b6ac86cf3db0f1088b140b9
https://github.com/llvm/llvm-project/commit/28acf4e5adf67b336b6ac86cf3db0f1088b140b9
Author: Charles Zablit <c_zablit at apple.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M .ci/green-dragon/lldb-windows.groovy
Log Message:
-----------
[lldb][Windows][CI] remove in process plugin testing (#226989)
lldb-server is now the default on Windows, stop testing the in process
plugin.
Commit: d9495236da19d3f11d6e00ad13f15281e879c61f
https://github.com/llvm/llvm-project/commit/d9495236da19d3f11d6e00ad13f15281e879c61f
Author: Evgenii Kudriashov <evgenii.kudriashov at intel.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
A llvm/test/CodeGen/X86/apx/ccmp-flag-source.ll
Log Message:
-----------
[X86] Add tests for CCMP chain leaves with a folded flag source (#226797)
Tests for #217682
Assisted-by: Claude Code
Commit: d359e9d80b4baaa2699ed5fc613533a6a147e188
https://github.com/llvm/llvm-project/commit/d359e9d80b4baaa2699ed5fc613533a6a147e188
Author: Vladimir Shiryaev <w at tagolog.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M llvm/lib/Support/raw_socket_stream.cpp
M llvm/unittests/Support/raw_socket_stream_test.cpp
Log Message:
-----------
[llvm][Support] Use ::closesocket for native sockets on Windows (#226613)
Calling ::close on a Windows SOCKET that has not been converted with
_open_osfhandle crashes and aborts the process with 0xC0000409 instead
of returning an error.
Use ::closesocket on Windows for those sockets, and keep ::close on
POSIX.
Commit: 33eb30d7b79d79558afcf65186d2b97dfb000efe
https://github.com/llvm/llvm-project/commit/33eb30d7b79d79558afcf65186d2b97dfb000efe
Author: 陈子昂 <2802328816 at qq.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M clang/include/clang/Basic/BuiltinsRISCV.td
M clang/lib/CodeGen/TargetBuiltins/RISCV.cpp
M clang/lib/Headers/riscv_packed_simd.h
M clang/test/CodeGen/RISCV/rvp-intrinsics.c
M cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c
M llvm/include/llvm/IR/IntrinsicsRISCV.td
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoP.td
A llvm/test/CodeGen/RISCV/rvp-widening-shift.ll
Log Message:
-----------
[Clang][RISCV] Add packed widening shift intrinsics (#224790)
This PR adds support for the Packed Widening Shift intrinsics:
- `__riscv_pwsll_s_u16x4`
- `__riscv_pwsll_s_u32x2`
- `__riscv_pwsla_s_i16x4`
- `__riscv_pwsla_s_i32x2`
Commit: 517839bdb319b9a604087909c1af9a699884df24
https://github.com/llvm/llvm-project/commit/517839bdb319b9a604087909c1af9a699884df24
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M llvm/lib/Analysis/VectorUtils.cpp
M llvm/test/Transforms/LoopVectorize/intrinsic.ll
Log Message:
-----------
[VectorUtils] Allow trivial vectorization of llvm.pdep and llvm.pext intrinsics (#227019)
Commit: 0767e7c6bace2f7df6d13601b021280b569d371a
https://github.com/llvm/llvm-project/commit/0767e7c6bace2f7df6d13601b021280b569d371a
Author: Charles Zablit <c_zablit at apple.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M lldb/packages/Python/lldbsuite/test/lldbtest.py
Log Message:
-----------
[lldb][test] Don't add pdb to explicitly tagged debug info categories (#226999)
`LLDBTestCaseFactory` appends `"pdb"` to `dbginfo_categories` whenever
the class sets `TEST_WITH_PDB_DEBUG_INFO=True`. When a test method is
tagged with explicit debug info categories
(`@add_test_categories(["dwarf"])`), `dbginfo_categories` is the set
intersection of the method's categories and the known debug info
categories, not a list, so the class failed to load with
```
AttributeError: 'set' object has no attribute 'append'
```
and dotest reported the whole file as UNRESOLVED.
Only add "pdb" when the method is not tagged, which is also the only
case where the default categories are used.
rdar://188589961
Commit: a0f704dc2dbdc0a77e7cc100c640eb63f80028c7
https://github.com/llvm/llvm-project/commit/a0f704dc2dbdc0a77e7cc100c640eb63f80028c7
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M llvm/lib/Analysis/ScalarEvolution.cpp
Log Message:
-----------
[SCEV] Skip invalidation with empty ValueExprMap (NFC). (#226845)
forgetLoop, forgetValue and forgetValues walk the def-use chains from
the forgotten instructions and erase each visited value's SCEV. This can
be expensive.
If ValueExprMap is empty, there's nothing to forget and skipping the
walk reduces compile-time a bit:
stage1-O3: -0.05%
stage1-ReleaseThinLTO: -0.05%
stage1-ReleaseLTO-g: -0.03%
stage1-aarch64-O3: -0.04%
stage2-O3: -0.05%
stage2-clang: -0.01%
https://llvm-compile-time-tracker.com/compare.php?from=899d817c7950c997402cd229935cd822acf45b08&to=c43f92b9840b62f75ab8a45b7379188d78d81135&stat=instructions:u
PR: https://github.com/llvm/llvm-project/pull/226845
Commit: 221fe115600f4051c7d3a92614da15e183073afa
https://github.com/llvm/llvm-project/commit/221fe115600f4051c7d3a92614da15e183073afa
Author: Farzon Lotfi <farzonlotfi at microsoft.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M clang/include/clang/AST/ASTContext.h
M clang/include/clang/AST/MatrixUtils.h
M clang/include/clang/AST/PropertiesBase.td
M clang/include/clang/AST/TypeBase.h
M clang/include/clang/AST/TypeProperties.td
M clang/include/clang/Sema/SemaHLSL.h
M clang/lib/AST/ASTContext.cpp
M clang/lib/AST/ASTImporter.cpp
M clang/lib/AST/Type.cpp
M clang/lib/CodeGen/CGExpr.cpp
M clang/lib/CodeGen/CGExprScalar.cpp
M clang/lib/CodeGen/CGHLSLBuiltins.cpp
M clang/lib/CodeGen/CodeGenTypes.cpp
M clang/lib/Sema/SemaExpr.cpp
M clang/lib/Sema/SemaHLSL.cpp
M clang/lib/Sema/SemaStmt.cpp
M clang/lib/Sema/SemaType.cpp
M clang/lib/Sema/TreeTransform.h
M clang/test/AST/HLSL/matrix_layout_attr.hlsl
M clang/test/CodeGen/matrix-type-indexing.c
M clang/test/CodeGenHLSL/BasicFeatures/MatrixElementTypeCast.hlsl
M clang/test/CodeGenHLSL/BasicFeatures/MatrixExplicitTruncation.hlsl
M clang/test/CodeGenHLSL/BasicFeatures/MatrixImplicitTruncation.hlsl
M clang/test/CodeGenHLSL/BasicFeatures/MatrixInitializerListOrder.hlsl
M clang/test/CodeGenHLSL/BasicFeatures/MatrixToAndFromVectorConstructors.hlsl
M clang/test/CodeGenHLSL/BasicFeatures/VectorElementwiseCast.hlsl
M clang/test/CodeGenHLSL/BasicFeatures/matrix-type-indexing.hlsl
M clang/test/CodeGenHLSL/builtins/mul.hlsl
M clang/test/CodeGenHLSL/builtins/transpose.hlsl
M clang/test/CodeGenHLSL/matrix-layout-attr-overrides-default.hlsl
A clang/test/CodeGenHLSL/matrix-layout-register-representation.hlsl
M clang/test/CodeGenHLSL/resources/MatrixElement_cbuffer.hlsl
M clang/test/SemaHLSL/matrix_layout_attr.hlsl
Log Message:
-----------
[HLSL] Preserve matrix layout as AST storage metadata (#225519)
fixes #213996
fixes #211977
fixes https://godbolt.org/z/rhTYx1KGf
Keep matrix layout metadata on noncanonical matrix types without
affecting type identity, overload resolution, deduction, or mangling.
Normalize matrix values to column-major register representation when
loading from memory, and convert them back to the destination layout
when storing. Preserve layout metadata through typedefs, arrays,
records, resources, serialization, AST import, and template
substitution.
This change also starts the reversal of encoding row\column major via
indexing changes in codegen and instead ops for a stable index but
transpose intrinsics for swapping matrix majorness.
Commit: 81cdde2cef226f50fcd7db798b5ee5e22dcb1dba
https://github.com/llvm/llvm-project/commit/81cdde2cef226f50fcd7db798b5ee5e22dcb1dba
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/select-sadde.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-saddo.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-ssube.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-ssubo.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-uadde.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-uaddo.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-usube.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-usubo.mir
Log Message:
-----------
AArch64: Mark the NZCV def dead for unused overflow results (#227018)
Avoid implicitly depending on later recomputed dead flags.
Co-authored-by: Claude Opus 5 <noreply at anthropic.com>
Commit: 8ece76768f67c9a5ff67a45db38dee7bb700dc20
https://github.com/llvm/llvm-project/commit/8ece76768f67c9a5ff67a45db38dee7bb700dc20
Author: Kazu Hirata <kazu at google.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M llvm/include/llvm/ADT/DenseMap.h
Log Message:
-----------
[ADT] Extract SmallDenseMapStorage from SmallDenseMap (NFC) (#226882)
This patch extracts the inline and heap bucket and occupancy storage
management from SmallDenseMap into a new helper class,
densemap::detail::SmallDenseMapStorage, and updates SmallDenseMap to
use it via composition.
This is part of the effort to replace CRTP in DenseMapBase with
composition (see #168255 and #226664). With both DenseMapStorage and
SmallDenseMapStorage in place, the next patch will remove CRTP from
DenseMapBase.
Assisted-by: Antigravity
Commit: 4fce7d6bfb18abfd20021e679f8fce489a6ed898
https://github.com/llvm/llvm-project/commit/4fce7d6bfb18abfd20021e679f8fce489a6ed898
Author: Nico Weber <thakis at chromium.org>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M clang/include/clang/AST/ASTContext.h
M clang/lib/AST/ASTContext.cpp
Log Message:
-----------
[clang] Add one-entry cache for ASTContext::getDeclAttrs() (#226610)
In libc++, almost every decl has attributes, so ASTContext::DeclAttrs
has 50k-150k entries when using libc++. But attributes are often queried
several times in a row for the same decl (e.g. `D->hasAttr<A>() ||
D->hasAttr<B>()`). Numbers for some Chromium TUs:
getDeclAttrs() same Decl as table
calls previous call size
blink logical_box_fragment.cc 19.6M 88.4% 156132
glic_webui_contents_manager.cc 16.0M 86.1% 144545
tflite kernels/conv.cc 6.1M 91.2% 52623
So add a one-element cache. AttrVecs are allocated separately, so
keeping a pointer to the result is safe.
Build time for 60 random Chromium TUs drawn with probability
proportional to their compile time:
CPU time: 240.3 s => 237.4 s, -1.20%
instructions: 2489.0e9 => 2452.9e9, -1.45%
(To check noise level, running this with the same binary twice: +-0.04%
CPU time, +-0.01% instructions.)
Every one of the 60 TUs improves, by 0.98% to 2.26% in instructions.
No behavior change.
Commit: fc1e244c970c1ab169fb1b43c06797a931fe7082
https://github.com/llvm/llvm-project/commit/fc1e244c970c1ab169fb1b43c06797a931fe7082
Author: Kazu Hirata <kazu at google.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
Log Message:
-----------
[ADT] Extract SmallDenseMapStorage from SmallDenseMap (NFC) (#226882)
This patch extracts the inline and heap bucket and occupancy storage
management from SmallDenseMap into a new helper class,
densemap::detail::SmallDenseMapStorage, and updates SmallDenseMap to
use it via composition.
This is part of the effort to replace CRTP in DenseMapBase with
composition (see #168255 and #226664). With both DenseMapStorage and
SmallDenseMapStorage in place, the next patch will remove CRTP from
DenseMapBase.
Assisted-by: Antigravity
Commit: f4c1a20178107dd75e0b38ff875bcb0a1b48d6a0
https://github.com/llvm/llvm-project/commit/f4c1a20178107dd75e0b38ff875bcb0a1b48d6a0
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/fp-intrinsics-flags.ll
A llvm/test/CodeGen/X86/fpcw-dead-eflags.ll
Log Message:
-----------
X86: Mark EFLAGS dead on the FP control word OR (#227017)
Fix custom inserters to add dead flags.
Co-authored-by: Claude Opus 5 <noreply at anthropic.com>
Commit: 99667ddd5e99f3cf2dfe3e12912e1ae37626f3ba
https://github.com/llvm/llvm-project/commit/99667ddd5e99f3cf2dfe3e12912e1ae37626f3ba
Author: Evgenii Kudriashov <evgenii.kudriashov at intel.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
A llvm/test/CodeGen/X86/apx/bls-egpr.ll
Log Message:
-----------
[X86][APX] Precommit test for BLSI/BLSMSK i8 patterns with EGPR (NFC) (#226793)
The i8 BLSI/BLSMSK patterns always select the VEX forms, so when only
extended GPRs (r16-r31) are available the operands get spilled instead
of using the EVEX forms.
Tests for #226796
Assisted-by: Claude Code
Co-authored-by: Claude Opus 5.5 (1M context) <noreply at anthropic.com>
Commit: 1306e151f1b7874b0dee2e8b037a5a117e6e809b
https://github.com/llvm/llvm-project/commit/1306e151f1b7874b0dee2e8b037a5a117e6e809b
Author: Nico Weber <thakis at chromium.org>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M clang/lib/Analysis/UnsafeBufferUsage.cpp
Log Message:
-----------
[-Wunsafe-buffer-usage] Speed up warning a bit (#226605)
Checking a type is faster than calling ignoreUnsafeBufferIn...(). The
latter has to get the Stmt's begin loc, look up diagnostic state and
suppression, etc. And the type check lets us skip most Stmts cheaply, so
do that first.
In a sampling profile of 48 Chromium TUs (which are built with
-Wunsafe-buffer-usage), UnsafeBufferUsageReporter's
ignoreUnsafeBufferInLibcCall() and ignoreUnsafeBufferInContainer() were
1.35% and 1.29% of the total compile time, and 3.75% for
checkUnsafeBufferUsage() as a whole.
For 60 random Chromium TUs drawn with probability proportional to their
compile time, sum over all TUs:
CPU time: 242.9 s => 237.5 s, -2.2%
instructions: 2452.6e9 => 2371.8e9, -3.3%
No behavior change.
Commit: 82f8753b9c1e2574ad979cf2a9e4adfb4b19c224
https://github.com/llvm/llvm-project/commit/82f8753b9c1e2574ad979cf2a9e4adfb4b19c224
Author: Ross Burton <ross.burton at arm.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M llvm/examples/Kaleidoscope/MCJIT/cached/genk-timing.py
M llvm/examples/Kaleidoscope/MCJIT/cached/split-lib.py
M llvm/examples/Kaleidoscope/MCJIT/complete/genk-timing.py
M llvm/examples/Kaleidoscope/MCJIT/complete/split-lib.py
M llvm/examples/Kaleidoscope/MCJIT/lazy/genk-timing.py
M llvm/test/DebugInfo/Inputs/check-fake-use.py
M llvm/test/Other/opt-bisect-helper.py
M llvm/test/TableGen/JSON-check.py
M llvm/test/tools/llvm-reduce/Inputs/sleep-and-check-stores.py
M llvm/tools/opt-viewer/extract-reproducers.py
M llvm/tools/opt-viewer/opt-diff.py
M llvm/tools/opt-viewer/opt-stats.py
M llvm/tools/opt-viewer/opt-viewer.py
M llvm/tools/opt-viewer/optrecord.py
M llvm/utils/DSAclean.py
M llvm/utils/DSAextract.py
M llvm/utils/Misc/zkill
M llvm/utils/Target/ARM/analyze-match-table.py
M llvm/utils/abtest.py
M llvm/utils/bisect
M llvm/utils/chunk-print-before-all.py
M llvm/utils/clang-parse-diagnostics-file
M llvm/utils/convert-constraint-log-to-z3.py
M llvm/utils/create_ladder_graph.py
M llvm/utils/docker/scripts/llvm_checksum/llvm_checksum.py
M llvm/utils/extract-section.py
M llvm/utils/extract_symbols.py
M llvm/utils/extract_vplan.py
M llvm/utils/indirect_calls.py
M llvm/utils/lint/common_lint.py
M llvm/utils/lint/cpp_lint.py
M llvm/utils/lint/generic_lint.py
M llvm/utils/lit/lit/ProgressBar.py
M llvm/utils/lit/tests/Inputs/check_path.py
M llvm/utils/lit/tests/Inputs/fake-externals/cd
M llvm/utils/lit/tests/Inputs/fake-externals/diff
M llvm/utils/lit/tests/Inputs/fake-externals/env
M llvm/utils/lit/tests/Inputs/fake-externals/export
M llvm/utils/lit/tests/Inputs/fake-externals/mkdir
M llvm/utils/lit/tests/Inputs/fake-externals/rm
M llvm/utils/lit/tests/Inputs/googletest-crash/DummySubDir/OneTest.py
M llvm/utils/lit/tests/Inputs/googletest-detect-duplicate/DummySubDir/OneTest.py
M llvm/utils/lit/tests/Inputs/googletest-discovery-failed/subdir/OneTest.py
M llvm/utils/lit/tests/Inputs/googletest-format-respect-gtest-sharding-env-vars/DummySubDir/OneTest.py
M llvm/utils/lit/tests/Inputs/googletest-format/DummySubDir/OneTest.py
M llvm/utils/lit/tests/Inputs/googletest-no-sharding/DummySubDir/OneTest.py
M llvm/utils/lit/tests/Inputs/googletest-prefix/DummySubDir/test_one.py
M llvm/utils/lit/tests/Inputs/googletest-sanitizer-error/DummySubDir/OneTest.py
M llvm/utils/lit/tests/Inputs/googletest-timeout/DummySubDir/OneTest.py
M llvm/utils/lit/tests/Inputs/shtest-format/write-bad-encoding.py
M llvm/utils/lit/tests/Inputs/shtest-format/write-control-chars.py
M llvm/utils/lit/tests/Inputs/shtest-not-posix/fail-signal.py
M llvm/utils/lit/tests/Inputs/shtest-not/fail.py
M llvm/utils/lit/tests/Inputs/shtest-not/fail2.py
M llvm/utils/lit/tests/Inputs/shtest-not/pass.py
M llvm/utils/lit/tests/Inputs/shtest-output-printing/write-a-lot.py
M llvm/utils/lit/tests/Inputs/shtest-shell/check_args.py
M llvm/utils/lit/tests/Inputs/shtest-shell/write-to-stderr.py
M llvm/utils/lit/tests/Inputs/shtest-shell/write-to-stdout-and-stderr.py
M llvm/utils/lit/tests/check-tested-lit-timeout-ability
M llvm/utils/llvm-gisel-cov.py
M llvm/utils/llvm-original-di-preservation.py
M llvm/utils/merge-json.py
M llvm/utils/release/findRegressions-nightly.py
M llvm/utils/release/findRegressions-simple.py
M llvm/utils/remote-exec.py
M llvm/utils/schedcover.py
M llvm/utils/shuffle_fuzz.py
M llvm/utils/shuffle_select_fuzz_tester.py
M llvm/utils/sort_includes.py
M llvm/utils/testgen/mc-bundling-x86-gen.py
M llvm/utils/unicode-case-fold.py
M llvm/utils/wciia.py
Log Message:
-----------
[llvm] Unify python shebangs (#187255)
As per PEP-0394[1], there is no real concensus over what binary names
Python has, specifically 'python' could be Python 3, Python 2, or not
exist.
However, everyone has a python3 interpreter and the scripts are all
written for Python 3. Unify the shebangs so that the ~50% of shebangs
that use python now use python3.
[1] https://peps.python.org/pep-0394/
Commit: 2d254ab1e39a31dd7a4afc03e782d371e0d83b13
https://github.com/llvm/llvm-project/commit/2d254ab1e39a31dd7a4afc03e782d371e0d83b13
Author: Kareem Ergawy <kergawy at nvidia.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M flang/include/flang/Lower/PFTBuilder.h
M flang/include/flang/Lower/PFTDefs.h
M flang/lib/Lower/PFTBuilder.cpp
M flang/test/Lower/assigned-goto-labeled-end.f90
M flang/test/Lower/ifconvert.f90
A flang/test/Lower/pre-fir-tree-incoming-branches.f90
M flang/test/Lower/trailing-cycle.f90
Log Message:
-----------
[flang] Record the evaluations that branch to each evaluation (#225755)
The PFT records where each branch goes, but not where it comes from, so
asking whether anything branches into a construct means walking the
whole procedure.
Record the reverse edges beside the forward ones, and print them in PFT
dumps so both directions of the branch graph are visible.
Commit: a3cf6f45fb686ec4d80d59d274132bbe95a06790
https://github.com/llvm/llvm-project/commit/a3cf6f45fb686ec4d80d59d274132bbe95a06790
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp
M llvm/test/CodeGen/AMDGPU/wqm.mir
Log Message:
-----------
AMDGPU: Mark SCC def dead in kill/demote lowering (#227024)
Co-authored-by: Claude Opus 5 <noreply at anthropic.com>
Commit: dbe2ac32c9e6791a635479ee0137feb722ef47ce
https://github.com/llvm/llvm-project/commit/dbe2ac32c9e6791a635479ee0137feb722ef47ce
Author: hidekisaito <hidekido at amd.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/test/CodeGen/AMDGPU/coexec-sched-flavor-classification.mir
Log Message:
-----------
[AMDGPU] Make GFX1250VALUBlockingCycles a feature. (#226314)
Included (intentional) behavior change: gfx1251 (w/ FullRate64Ops) does
not have GFX1250VALUBlockingCycles feature --- table is only partially usable for
gfx1251.
Commit: 9fcdae44a6465714fd53acf90a356cc2cca96ddd
https://github.com/llvm/llvm-project/commit/9fcdae44a6465714fd53acf90a356cc2cca96ddd
Author: Nikhil Kotikalapudi <nak00001 at outlook.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPURewriteAGPRCopyMFMA.cpp
M llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
Log Message:
-----------
[CodeGen] Re-land reverted PR (#216510): "Use RegisterClassInfo for remaining allocation-order users" (#222450)
Re-land PR #216510 which was reverted in #221749 and fixed by @mhalk in
#221849.
Additionally addresses the comment in the reversion PR to fix
`/llvm/test/CodeGen/AArch64/wineh-try-catch.ll` with -regalloc=pbqp by
refreshing RCI with updateReservedRegs from my previous PR.
Edit: Removed PBQP related items from this PR.
Assisted by composer 2.5
Commit: 9073f2403eac0845d72eb806bab6d0d6aced13f6
https://github.com/llvm/llvm-project/commit/9073f2403eac0845d72eb806bab6d0d6aced13f6
Author: Keith Smiley <keithbsmiley at gmail.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M lld/test/Unit/lit.cfg.py
M lld/unittests/AsLibELF/CMakeLists.txt
M lld/unittests/AsLibELF/OutputStream.cpp
M lld/unittests/AsLibELF/ROCm.cpp
Log Message:
-----------
Revert "[lld][test] Use LLVM helpers for input file discovery" (#227045)
Reverts llvm/llvm-project#220404
Based on post merge comments on that change
Commit: f974015a10cfa86855b8e11e59a2b14079a4b8eb
https://github.com/llvm/llvm-project/commit/f974015a10cfa86855b8e11e59a2b14079a4b8eb
Author: lzcnt <lzcunt at rawr.fun>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M clang/lib/Basic/Targets/OSTargets.h
M clang/test/Preprocessor/init.c
M llvm/include/llvm/TargetParser/Triple.h
Log Message:
-----------
[clang][mlibc] Predefine `__mlibc__` for mlibc targets (#225654)
Pretty much all users of mlibc targets currently vendor this or similar
patches and having it upstream would be useful.
Commit: 1abae183ec2d58bd9fba2ec713266ad29175705f
https://github.com/llvm/llvm-project/commit/1abae183ec2d58bd9fba2ec713266ad29175705f
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
M llvm/test/CodeGen/SPIRV/llvm-intrinsics/ldexp.ll
Log Message:
-----------
[SPIR-V] Fix ldexp exponent splat for vectors wider than four elements (#225617)
The shared createVirtualRegister helper sets the full vector LLT, which
does not match the 128-bit vector register classes and trips a size
assert
Commit: d306fc59fcffc2779d1710c7dea8bc7699b5950a
https://github.com/llvm/llvm-project/commit/d306fc59fcffc2779d1710c7dea8bc7699b5950a
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
Log Message:
-----------
AMDGPU: Mark SCC defs dead in the indirect addressing expansion (#227012)
The exec manipulation and index offset computations clobber SCC but
never use it.
Co-authored-by: Claude Opus 5 <noreply at anthropic.com>
Commit: 2ad73e6250f656aca147f024c0fe00d411f1c5c0
https://github.com/llvm/llvm-project/commit/2ad73e6250f656aca147f024c0fe00d411f1c5c0
Author: Jeremy Kun <jkun at google.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M mlir/lib/Target/Cpp/TranslateToCpp.cpp
M mlir/test/Target/Cpp/expressions.mlir
Log Message:
-----------
Give emitc.member_call_opaque operator precedence (#226349)
The original problem here is that member_call_opaque could not be used
inside an emitc.expression. When I added the op to the precedence table,
I noticed that the emitter was generating spurious parentheses (e.g.,
`(v).at(i)`), and so, with AI help, I forwarded emitc::LoadOp operands
in CppEmitter::emitOperand when evaluating sub-expressions, so
lvalue-to-rvalue loads do not introduce spurious parentheses around
receiver variables.
---------
Co-authored-by: ioana ghiban <ioana.ghiban at arm.com>
Commit: 5abc636bed3f5b8938cbbf626e881c194a284267
https://github.com/llvm/llvm-project/commit/5abc636bed3f5b8938cbbf626e881c194a284267
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Log Message:
-----------
DAG: Use poison for some vector element folds (#225406)
Commit: f2eddce184a57aff4265d0f3ee3a7d4b0f1f6162
https://github.com/llvm/llvm-project/commit/f2eddce184a57aff4265d0f3ee3a7d4b0f1f6162
Author: Amr Hesham <amr96 at programmer.net>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenExpr.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
M clang/lib/CIR/Lowering/LoweringHelpers.cpp
M clang/test/CIR/CodeGen/matrix.cpp
Log Message:
-----------
[CIR] Support load & store for builtin matrix type (#226259)
Implement support for the load and store built-in matrix type
Issue #221772
Commit: 2190e84833b8f8ae1fa235dc2868bd13112d0c05
https://github.com/llvm/llvm-project/commit/2190e84833b8f8ae1fa235dc2868bd13112d0c05
Author: Zeyi Xu <zeyi2 at nekoarch.cc>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
A clang-tools-extra/docs/clang-tidy/checks/readability/redundant-lambda-parameter-list.md
R clang-tools-extra/docs/clang-tidy/checks/readability/redundant-lambda-parameter-list.rst
A clang-tools-extra/docs/clang-tidy/checks/readability/redundant-member-init.md
R clang-tools-extra/docs/clang-tidy/checks/readability/redundant-member-init.rst
A clang-tools-extra/docs/clang-tidy/checks/readability/redundant-nested-if.md
R clang-tools-extra/docs/clang-tidy/checks/readability/redundant-nested-if.rst
A clang-tools-extra/docs/clang-tidy/checks/readability/redundant-parentheses.md
R clang-tools-extra/docs/clang-tidy/checks/readability/redundant-parentheses.rst
A clang-tools-extra/docs/clang-tidy/checks/readability/redundant-preprocessor.md
R clang-tools-extra/docs/clang-tidy/checks/readability/redundant-preprocessor.rst
A clang-tools-extra/docs/clang-tidy/checks/readability/redundant-qualified-alias.md
R clang-tools-extra/docs/clang-tidy/checks/readability/redundant-qualified-alias.rst
A clang-tools-extra/docs/clang-tidy/checks/readability/redundant-string-init.md
R clang-tools-extra/docs/clang-tidy/checks/readability/redundant-string-init.rst
A clang-tools-extra/docs/clang-tidy/checks/readability/redundant-typename.md
R clang-tools-extra/docs/clang-tidy/checks/readability/redundant-typename.rst
A clang-tools-extra/docs/clang-tidy/checks/readability/reference-to-constructed-temporary.md
R clang-tools-extra/docs/clang-tidy/checks/readability/reference-to-constructed-temporary.rst
A clang-tools-extra/docs/clang-tidy/checks/readability/simplify-boolean-expr.md
R clang-tools-extra/docs/clang-tidy/checks/readability/simplify-boolean-expr.rst
Log Message:
-----------
[clang-tidy][docs] Rename readability check docs to Markdown [4/5] (#221640)
Tracking issue: #201242
See the [migration guide] for more information.
[migration guide]:
https://llvm.org/docs/SphinxQuickstartTemplate.html#markdown-migration-guidelines
This is the fourth part of the mechanical rename of the check
documentations in readability module.
The rewrite is provided by the next PR in this stack.
Commit: 0d59780b887782c21274868dbc8eb6d5c83e8e12
https://github.com/llvm/llvm-project/commit/0d59780b887782c21274868dbc8eb6d5c83e8e12
Author: Zeyi Xu <zeyi2 at nekoarch.cc>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M clang-tools-extra/docs/clang-tidy/checks/readability/redundant-lambda-parameter-list.md
M clang-tools-extra/docs/clang-tidy/checks/readability/redundant-member-init.md
M clang-tools-extra/docs/clang-tidy/checks/readability/redundant-nested-if.md
M clang-tools-extra/docs/clang-tidy/checks/readability/redundant-parentheses.md
M clang-tools-extra/docs/clang-tidy/checks/readability/redundant-preprocessor.md
M clang-tools-extra/docs/clang-tidy/checks/readability/redundant-qualified-alias.md
M clang-tools-extra/docs/clang-tidy/checks/readability/redundant-string-init.md
M clang-tools-extra/docs/clang-tidy/checks/readability/redundant-typename.md
M clang-tools-extra/docs/clang-tidy/checks/readability/reference-to-constructed-temporary.md
M clang-tools-extra/docs/clang-tidy/checks/readability/simplify-boolean-expr.md
Log Message:
-----------
[clang-tidy][docs] Rewrite readability check docs to Markdown [4/5] (#221641)
Tracking issue: #201242
See the [migration guide] for more information.
[migration guide]:
https://llvm.org/docs/SphinxQuickstartTemplate.html#markdown-migration-guidelines
This is the fourth part of rewriting check documentations in readability
module from reST to MyST Markdown.
AI Usage: This was prepared with rnk's fork of rst2myst and
GPT5.6-assisted (both Codex and AmpCode) cleanup.
I manually verified that the documentation renders as expected.
Preview site:
https://broken.life/llvm-staging/readability-markdown-port/index.html
---------
Co-authored-by: Amp <amp at ampcode.com>
Commit: 5d23afa97db69773dc705ffda8a44a380e04ef57
https://github.com/llvm/llvm-project/commit/5d23afa97db69773dc705ffda8a44a380e04ef57
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp
M llvm/test/CodeGen/AMDGPU/licm-wwm.mir
M llvm/test/CodeGen/AMDGPU/si-init-whole-wave.mir
M llvm/test/CodeGen/AMDGPU/wqm-debug-instr-terminator.mir
M llvm/test/CodeGen/AMDGPU/wqm-debug-instr.mir
M llvm/test/CodeGen/AMDGPU/wqm-propagate-for-execz-side-effect.mir
M llvm/test/CodeGen/AMDGPU/wqm-terminators.mir
M llvm/test/CodeGen/AMDGPU/wqm.mir
Log Message:
-----------
AMDGPU: Mark SCC defs dead in SIWholeQuadMode state transitions (#227015)
Co-authored-by: Claude Opus 5 <noreply at anthropic.com>
Commit: 03cb1db40787ab170cd2e4588840fe8b5ecf8fcf
https://github.com/llvm/llvm-project/commit/03cb1db40787ab170cd2e4588840fe8b5ecf8fcf
Author: Ivan Butygin <ivan.butygin at gmail.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M mlir/include/mlir/IR/SymbolTable.h
M mlir/lib/IR/SymbolTable.cpp
M mlir/lib/Transforms/RemoveDeadValues.cpp
A mlir/test/Transforms/remove-dead-values-symbol-scope.mlir
M mlir/unittests/IR/SymbolTableTest.cpp
Log Message:
-----------
[mlir] `remove-dead-values`: properly handle symbol users outside of a pass root. (#225355)
Follow up to the
https://github.com/llvm/llvm-project/pull/224831#pullrequestreview-5262450200
comment.
Add `areAllUsesVisible` query to the `SymbolUserMap` to check is all
users are visible and use it in `remove-dead-values`.
Commit: c4c1cbbcf2147ce18e4a0ad654a695719f253b66
https://github.com/llvm/llvm-project/commit/c4c1cbbcf2147ce18e4a0ad654a695719f253b66
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
Log Message:
-----------
[X86][NVPTX] Use `m_Value(N, Pattern)` overload to simplify matching. (#226621)
Replace the `m_AllOf(Pattern, m_Value(N))` idiom (match-and-bind) with
the `m_Value(N, Pattern)` overload.
Commit: 407f8a1f7d1edf096cb9e9ca868916599ad52b4e
https://github.com/llvm/llvm-project/commit/407f8a1f7d1edf096cb9e9ca868916599ad52b4e
Author: Brian Cain <brian.cain at oss.qualcomm.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M clang/lib/Driver/ToolChains/Hexagon.cpp
A clang/test/Driver/hexagon-eh-frame-pic.c
A llvm/test/MC/Hexagon/eh-frame.s
Log Message:
-----------
[Hexagon][Driver] Tell llvm-mc about PIC under -fno-integrated-as (#213821)
Hexagon picks the .eh_frame FDE pointer encoding from whether the code
is position independent: DW_EH_PE_pcrel if so, DW_EH_PE_absptr otherwise
(MCObjectFileInfo::initELFMCObjectFileInfo). Unlike most targets,
Hexagon uses llvm-mc rather than GNU as for -fno-integrated-as, and the
driver was not passing the PIC setting along. llvm-mc defaults to
non-PIC, so the same source assembled the two ways produced different
unwind tables: the integrated assembler emitted R_HEX_32_PCREL, while
-fno-integrated-as emitted R_HEX_32 with an absptr CIE augmentation.
hexagon-unknown-linux-musl defaults to PIC, so it was the default config
that diverged.
Pass -position-independent to llvm-mc when the relocation model is PIC.
Non-PIC keeps DW_EH_PE_absptr, unchanged.
Commit: dee78e33993c9275a0cdd3dc22a0b21958a42ef4
https://github.com/llvm/llvm-project/commit/dee78e33993c9275a0cdd3dc22a0b21958a42ef4
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M clang/test/CodeGen/msp430-register-names.c
M llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp
M llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-inline-asm.ll
M llvm/test/CodeGen/AArch64/aarch64-sme2-asm.ll
M llvm/test/CodeGen/AArch64/aarch64-za-clobber.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-inline-asm.ll
M llvm/test/CodeGen/PowerPC/pr47155-47156.ll
M llvm/test/CodeGen/RISCV/GlobalISel/irtranslator-inline-asm.ll
M llvm/test/CodeGen/X86/cfi-xmm.ll
M llvm/test/CodeGen/X86/inline-asm-avx512f-x-constraint.ll
M llvm/test/CodeGen/X86/inline-asm-default-clobbers.ll
M llvm/test/CodeGen/X86/tail-dup-asm-goto.ll
Log Message:
-----------
CodeGen: Mark inline asm clobber defs dead (#227026)
A clobber operand has no value associated with it, so the def is always
dead. Set the flag where the INLINEASM is built instead of relying on
later inference.
Co-authored-by: Claude Opus 5 <noreply at anthropic.com>
Commit: f32a45cfd8c688fcd002295ebcedac054b81e0bf
https://github.com/llvm/llvm-project/commit/f32a45cfd8c688fcd002295ebcedac054b81e0bf
Author: Andrzej Warzyński <andrzej.warzynski at arm.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M clang/test/CodeGen/AArch64/sve/dup.c
M clang/test/CodeGen/AArch64/sve/len.c
Log Message:
-----------
[clang][CIR] Add missing return stmt in tests (#226534)
This PR makes sure that tests in:
* clang/test/CodeGen/AArch64/sve/
follow the format previously establised in:
* clang/test/CodeGen/AArch64/sve-intrinsics/
Commit: 26033a3b66ed79f44524065c6004a7a809616b49
https://github.com/llvm/llvm-project/commit/26033a3b66ed79f44524065c6004a7a809616b49
Author: gallopruss-sie <russell.gallop at sony.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M clang/test/Driver/riscv32-toolchain-extra.c
M clang/test/Driver/riscv64-toolchain-extra.c
Log Message:
-----------
[clang][test] Pass -resource-dir in riscv*-toolchain-extra.c tests (#226952)
Fixes issue reported in
https://github.com/llvm/llvm-project/pull/216996#issuecomment-5846218483
These tests check that, with no GCC installation, the driver finds the
linker, crt0 and sysroot relative to its own bin/ directory. The
compiler-rt paths come from the resource directory, which the tests did
not specify, so they relied on the build's CLANG_RESOURCE_DIR placing it
within the fake toolchain tree.
With a relative CLANG_RESOURCE_DIR containing several "..", e.g.
../../../../lib/clang/24 as used by Gentoo, the resource directory
resolves outside of the test tree. This previously passed only because
the unnormalized path still contained "riscv64-nogcc/". Since
99988429d395 removed the dots from the path, the checks fail.
Pass an explicit -resource-dir within the test tree so the tests don't
depend on the build configuration.
Claude Code helped with this.
Commit: e40e0bc36b14d296df5798c52792f662c715b445
https://github.com/llvm/llvm-project/commit/e40e0bc36b14d296df5798c52792f662c715b445
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
A llvm/test/tools/llubi/intr_speculative_load.ll
A llvm/test/tools/llubi/intr_speculative_load_ub.ll
M llvm/tools/llubi/lib/Interpreter.cpp
Log Message:
-----------
[llubi] Add support for llvm.speculative.load. (#226839)
Implement the direct form of llvm.speculative.load, where the number of
accessible bytes N is passed as an i64. Only the N accessible bytes are
read from memory and they must be in bounds of the underlying object;
all other bytes are poison. With from_end, the accessible bytes are the
last N bytes of the loaded value. It is UB if N is poison or exceeds the
size of the loaded type.
Support for the oracle form will be added as follow-up.
PR: https://github.com/llvm/llvm-project/pull/226839
Commit: d1133c1d71ae87e6f77cf188b01ac976265f1363
https://github.com/llvm/llvm-project/commit/d1133c1d71ae87e6f77cf188b01ac976265f1363
Author: Raphael Isemann <rise at apple.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M lldb/source/Plugins/TypeSystem/CMakeLists.txt
A lldb/source/Plugins/TypeSystem/Clike/CMakeLists.txt
A lldb/source/Plugins/TypeSystem/Clike/TypeSystemClike.cpp
A lldb/source/Plugins/TypeSystem/Clike/TypeSystemClike.h
Log Message:
-----------
[lldb][Clike][NFC] Add the TypeSystemClike plugin skeleton (#222611)
Introduces an empty TypeSystem plugin infrastructure for the new
TypeSystemClike.
For the RFC with more information and background, see
https://discourse.llvm.org/t/rfc-a-faster-more-reliable-type-system-for-c-languages/91459
and #225371
assisted-by: claude
Commit: 111f1d4940427c04718fd038726da5d1860b94e3
https://github.com/llvm/llvm-project/commit/111f1d4940427c04718fd038726da5d1860b94e3
Author: Kazu Hirata <kazu at google.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M clang/include/clang/AST/ASTConcept.h
M clang/lib/Sema/SemaConcept.cpp
Log Message:
-----------
[clang] Migrate away from PointerUnion::dyn_cast (NFC) (#226653)
Note that PointerUnion::dyn_cast has been soft deprecated in
PointerUnion.h:
// FIXME: Replace the uses of is(), get() and dyn_cast() with
// isa<T>, cast<T> and the llvm::dyn_cast<T>
Literal migration would result in dyn_cast_if_present (see the
definition of PointerUnion::dyn_cast), but this patch uses dyn_cast on
UnsatisfiedConstraintRecord because it is always nonnull.
Specifically, ConstraintSatisfaction::Details only receives nonnull
pointers in the following places:
- ASTNodeImporter::ImportConstraintSatisfaction
- ConstraintSatisfactionChecker::consumeSFINAEFailure
- ConstraintSatisfactionChecker::EvaluateSlow
- ConstraintSatisfactionChecker::Evaluate
- readConstraintSatisfaction
Assisted-by: Antigravity
Commit: 869989ee3450903263300b247e127d1495f5e893
https://github.com/llvm/llvm-project/commit/869989ee3450903263300b247e127d1495f5e893
Author: Ilia Kuklin <ikuklin at accesssoftek.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M lldb/docs/dil-expr-lang.ebnf
M lldb/source/ValueObject/DILParser.cpp
Log Message:
-----------
[lldb][NFC] Add missing composite assignments to DIL grammar (#226558)
Commit: 4f70f183ac0e57c83dc470e12490a244e0570210
https://github.com/llvm/llvm-project/commit/4f70f183ac0e57c83dc470e12490a244e0570210
Author: David Green <david.green at arm.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M llvm/test/Analysis/CostModel/AArch64/cast.ll
M llvm/test/Analysis/CostModel/AArch64/sve-cast.ll
Log Message:
-----------
[AArch64] Add extra bitcast cost coverage. NFC (#227048)
Commit: c04cc6bcceeb34add319b1dcf0c066bfc033d85b
https://github.com/llvm/llvm-project/commit/c04cc6bcceeb34add319b1dcf0c066bfc033d85b
Author: Kazu Hirata <kazu at google.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M llvm/include/llvm/ProfileData/SampleProf.h
M llvm/include/llvm/ProfileData/SampleProfWriter.h
M llvm/lib/ProfileData/SampleProfWriter.cpp
M llvm/test/tools/llvm-profdata/profile-symbol-list.test
M llvm/unittests/ProfileData/SampleProfTest.cpp
Log Message:
-----------
[ProfileData] Support merging MD5-based ProfileSymbolList (#226594)
This patch supports merging MD5-based ProfileSymbolList instances and
writing the merged result to an extensible binary profile.
#210235 introduced the MD5-based ProfileSymbolList section in the
Eytzinger layout, where profile merging was initially supported only
from strings to an MD5-based Eytzinger array.
This patch adds DenseSet<uint64_t> GUIDs to ProfileSymbolList to
accumulate 64-bit MD5 hashes when merging MD5-based symbol lists,
while keeping ColdGUIDTable (EytzingerTableSpan) for zero-copy lookups
during compilation. collectGUIDs, contains, and size are updated to
query GUIDs when populated.
RFC:
https://discourse.llvm.org/t/rfc-faster-sample-profile-loading/90957/7
Assisted-by: Antigravity
Commit: 31ac095ef1ccbda0b37c55c718478a38609b30ae
https://github.com/llvm/llvm-project/commit/31ac095ef1ccbda0b37c55c718478a38609b30ae
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M llvm/lib/IR/ConstantRange.cpp
M llvm/unittests/IR/ConstantRangeTest.cpp
Log Message:
-----------
[ConstantRange] Compute exact no-wrap region w/o materializing CR. (#223969)
Inline logic into makeExactNoWrapRegion() so we do not need to construct
temporary constant ranges.
Together with using makeExecuteNoWrapRegion in SCEV, this improves
compile-time on SCEV-heavy workloads.
Analysis aided by Opus 5.
PR: https://github.com/llvm/llvm-project/pull/223969
Commit: f7f538b7ecf2baede19b86eca567f14095235b3a
https://github.com/llvm/llvm-project/commit/f7f538b7ecf2baede19b86eca567f14095235b3a
Author: Keith Smiley <keithbsmiley at gmail.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
A utils/bazel/llvm-project-overlay/lld/unittests/BUILD.bazel
Log Message:
-----------
[bazel] Run lld unittests (#220340)
Commit: 73014a8d08f4b205fd1f09bc0eb3e0cba7c5eff0
https://github.com/llvm/llvm-project/commit/73014a8d08f4b205fd1f09bc0eb3e0cba7c5eff0
Author: Akash Manna <akash.manna.mymail at gmail.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M clang/docs/ReleaseNotes.md
M clang/lib/Sema/TreeTransform.h
M clang/test/SemaTemplate/matrix-type.cpp
Log Message:
-----------
[Clang] Fix assertion when instantiating a matrix type with an invalid element type (#224331)
Fixes #202744
`Sema::BuildMatrixType` skips the element type check while the element
type is dependent, so `template <typename Y> using matrix_5_5 = Y
__attribute__((matrix_type(5, 5)));` gives a `ConstantMatrixType` whose
element is still unchecked. On instantiation,
`TreeTransform::RebuildConstantMatrixType` called
`ASTContext::getConstantMatrixType` directly, so nothing ever validated
the substituted type. `matrix_5_5<matrix_5_5<float>>` then hit the "need
a valid element type" assertion. The dependent-dimension case
(`matrix_type(R, C)`) was fine because `RebuildDependentSizedMatrixType`
already goes through `BuildMatrixType`.
`RebuildConstantMatrixType` now goes through `Sema::BuildMatrixType` as
well, the same way `RebuildExtVectorType` does for vectors: it takes the
attribute location and wraps the dimensions in integer literals. An
invalid instantiated element type now gets the usual `invalid matrix
element type` error instead of crashing, and the `_BitInt` element check
that this path also skipped is applied too.
Commit: 04032854901d949ca4a1b8e57c62fb53969a6ffc
https://github.com/llvm/llvm-project/commit/04032854901d949ca4a1b8e57c62fb53969a6ffc
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M llvm/lib/Target/X86/X86FastISel.cpp
A llvm/test/CodeGen/X86/fast-isel-divrem-dead-defs.ll
Log Message:
-----------
X86: Mark the unused defs of FastISel selected div/rem dead (#227053)
The DIV/IDIV instructions define the quotient, the remainder and the
flags, but X86FastISel::X86SelectDivRem only reads one of the quotient
and remainder. Mark the rest dead when building the instruction instead
of relying on later recomputatios.
Co-authored-by: Claude Opus 5 <noreply at anthropic.com>
Commit: c069c0e16445cd954146807451f1067f75a61f6c
https://github.com/llvm/llvm-project/commit/c069c0e16445cd954146807451f1067f75a61f6c
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M clang/lib/CodeGen/CGHLSLBuiltins.cpp
Log Message:
-----------
[HLSL] Fix -Wunused-variable in #225519 (#227059)
Inline the variable names given the variable names don't add much
clarity and they aren't used anywhere outside of asserts.
Commit: 15d2ca3ced8c18dcbc0b666f4de5067d4586e857
https://github.com/llvm/llvm-project/commit/15d2ca3ced8c18dcbc0b666f4de5067d4586e857
Author: Ilia Kuklin <ikuklin at accesssoftek.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M lldb/include/lldb/API/SBBreakpoint.h
M lldb/include/lldb/Breakpoint/Breakpoint.h
M lldb/include/lldb/Breakpoint/BreakpointLocation.h
M lldb/include/lldb/Breakpoint/StopCondition.h
M lldb/include/lldb/Interpreter/CommandOptionArgumentTable.h
M lldb/include/lldb/Target/Target.h
M lldb/include/lldb/lldb-enumerations.h
M lldb/source/API/SBBreakpoint.cpp
M lldb/source/Breakpoint/Breakpoint.cpp
M lldb/source/Breakpoint/BreakpointLocation.cpp
M lldb/source/Commands/CommandObjectBreakpoint.cpp
M lldb/source/Commands/Options.td
M lldb/source/Target/Target.cpp
M lldb/source/Target/TargetProperties.td
M lldb/test/API/functionalities/breakpoint/breakpoint_conditions/TestBreakpointConditions.py
Log Message:
-----------
[lldb] Speed up evaluating breakpoint conditions by using DIL (#224740)
The goal of this patch is to speed up the evaluation of breakpoint
conditions. Similar to how UserExpression is used to evaluate the
condition expression, DIL lexes and parses the expression once, and then
only evaluates the AST tree on every breakpoint location hit. If DIL
fails at any step, the evaluation falls back to UserExpression, and DIL
doesn't make any new attempts on subsequent breakpoint hits. The
breakpoint default evaluation mode (DIL, UserExpression or DWIM) can be
changed by `target.breakpoints-condition-mode` setting. The mode can
also be changed separately for a specific breakpoint via command line
option `-Z (--condition-mode)` or by SB API
`SBBreakpoint::SetConditionMode`.
Commit: aecdab8027a023de337992d47c4e9a8bb768beba
https://github.com/llvm/llvm-project/commit/aecdab8027a023de337992d47c4e9a8bb768beba
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M llvm/lib/Target/X86/X86FastISel.cpp
A llvm/test/CodeGen/X86/fast-isel-sext-dead-eflags.ll
Log Message:
-----------
X86: Mark EFLAGS dead on the NEG8r for sext from i1 in fast isel (#227058)
Co-authored-by: Claude Opus 5 <noreply at anthropic.com>
Commit: 8959ec064109a202c05cf0e1751cc953a7634f63
https://github.com/llvm/llvm-project/commit/8959ec064109a202c05cf0e1751cc953a7634f63
Author: Sam Clegg <sbc at chromium.org>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M lld/test/wasm/check-arch-32-in-64.test
M lld/test/wasm/check-arch-64-in-32.test
M lld/test/wasm/dylink.s
M lld/test/wasm/emit-relocs.s
M lld/test/wasm/locals-duplicate.test
M lld/test/wasm/lto/relocatable-undefined.ll
M lld/test/wasm/pie.s
M lld/test/wasm/relocatable.ll
M lld/test/wasm/rpath.s
M lld/test/wasm/shared-needed.s
M lld/test/wasm/shared-weak-undefined.s
M lld/test/wasm/shared.s
M lld/test/wasm/shared64.s
M lld/test/wasm/signature-mismatch-relocatable.s
M lld/test/wasm/signature-mismatch.s
M lld/test/wasm/stack-pointer.s
M lld/test/wasm/tls-export.s
M lld/test/wasm/weak-alias.s
M lld/wasm/InputFiles.cpp
M lld/wasm/SyntheticSections.cpp
M llvm/include/llvm/BinaryFormat/Wasm.h
M llvm/include/llvm/ObjectYAML/WasmYAML.h
M llvm/lib/MC/WasmObjectWriter.cpp
M llvm/lib/Object/WasmObjectFile.cpp
M llvm/lib/ObjectYAML/WasmEmitter.cpp
M llvm/lib/ObjectYAML/WasmYAML.cpp
M llvm/test/CodeGen/WebAssembly/profile.ll
M llvm/test/MC/WebAssembly/assembler-binary.ll
M llvm/test/MC/WebAssembly/call-indirect-relocs.s
M llvm/test/MC/WebAssembly/comdat.ll
M llvm/test/MC/WebAssembly/common.s
M llvm/test/MC/WebAssembly/custom-sections.ll
M llvm/test/MC/WebAssembly/data-section.s
M llvm/test/MC/WebAssembly/debug-info.ll
M llvm/test/MC/WebAssembly/debug-info64.ll
M llvm/test/MC/WebAssembly/export-name.s
M llvm/test/MC/WebAssembly/function-sections.ll
M llvm/test/MC/WebAssembly/global-ctor-dtor.ll
M llvm/test/MC/WebAssembly/globals.s
M llvm/test/MC/WebAssembly/init-array-label.s
M llvm/test/MC/WebAssembly/init-array.s
M llvm/test/MC/WebAssembly/reloc-pic.s
M llvm/test/MC/WebAssembly/reloc-pic64.s
M llvm/test/MC/WebAssembly/tables.s
M llvm/test/MC/WebAssembly/tag-section.s
M llvm/test/MC/WebAssembly/tls.s
M llvm/test/MC/WebAssembly/tls64.s
M llvm/test/MC/WebAssembly/type-index.s
M llvm/test/MC/WebAssembly/unnamed-data.ll
M llvm/test/MC/WebAssembly/wasm64.s
M llvm/test/MC/WebAssembly/weak-alias.s
M llvm/test/ObjectYAML/wasm/dylink_section.yaml
M llvm/test/ObjectYAML/wasm/linking_section.yaml
M llvm/tools/obj2yaml/wasm2yaml.cpp
Log Message:
-----------
[WebAssembly] Add target architecture to object file format (#225979)
Store the target architecture string (`wasm32` or `wasm64`) in a new
`WASM_TARGET_ARCH` subsection in the `linking` custom section and in a
new `WASM_DYLINK_TARGET_ARCH` subsection in the `dylink.0` custom
section.
Previously, architecture detection for object files and shared libraries
relied on heuristics (such as whether memory64 was imported/defined or
presence of 64-bit relocations). For modules that do not access memory,
this resulted in wasm64 objects/shared libraries being incorrectly
detected as wasm32.
With this change:
- `WasmObjectWriter` emits the `WASM_TARGET_ARCH` subsection in
`linking`.
- `wasm-ld` emits `WASM_DYLINK_TARGET_ARCH` when generating shared
libraries and `WASM_TARGET_ARCH` when generating relocatable output
(`-r`).
- `WasmObjectFile::getArch()` checks these subsections first before
falling back to the `HasMemory64` heuristic.
- `SharedFile` in `lld` now checks the object architecture via
`checkArch()`.
- Added support to `obj2yaml` and `yaml2obj`.
Fixes: #98778
Commit: 156ba8d3015afb36aa16831dfcac1ea229db85aa
https://github.com/llvm/llvm-project/commit/156ba8d3015afb36aa16831dfcac1ea229db85aa
Author: Akash Manna <akash.manna.mymail at gmail.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
M llvm/test/CodeGen/AArch64/ldexp.ll
M llvm/test/CodeGen/X86/ldexp-avx512.ll
M llvm/test/CodeGen/X86/ldexp.ll
Log Message:
-----------
[SelectionDAG] Fix crash scalarizing `FLDEXP` with a legal `<1 x i1>` exponent (#224809)
Fixes #219695
When the result of an `FLDEXP` node is scalarized, we went through the
generic `ScalarizeVecRes_BinOp` handler, which asks for the scalarized
form of both operands. That only works when both operands share the
result's type action. `ldexp` is not a true binop: its exponent has its
own integer vector type, and under AVX-512 `<1 x i1>` is a legal mask
type. It was never scalarized, so it never made it into the table, and
the lookup hit `TableId should be non-zero`. It isn't specific to i1
either: on AArch64, `ldexp <1 x half>, <1 x i32>` hits the same assert
because `v1f16` is scalarized while `v1i32` is widened.
`FLDEXP` now has its own scalarization handler. The FP operand is
scalarized as before, while the exponent is legalized according to its
own type action: its scalarized value is used when one exists, otherwise
the single element is extracted from the vector. This is the same
approach `ScalarizeVecRes_UnaryOp` and `ScalarizeVecRes_SETCC` already
take for operands that don't need scalarizing, and mirrors what
`SplitVecRes_FPOp_MultiType` does for the split case.
Commit: 374c5e71b89783a84693140f9e69536e748b1f3f
https://github.com/llvm/llvm-project/commit/374c5e71b89783a84693140f9e69536e748b1f3f
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
A llvm/test/Transforms/SLPVectorizer/AArch64/trimmed-subtree-schedule-operands.ll
Log Message:
-----------
[SLP][NFC]Add a test with the regression after disabling scheduling of instructions, NFC
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/227080
Commit: d3429a751155c803e03fa4521ffe42c4868bfe7c
https://github.com/llvm/llvm-project/commit/d3429a751155c803e03fa4521ffe42c4868bfe7c
Author: Yian Su <yiansu.developer at gmail.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M mlir/lib/Dialect/OpenACC/Transforms/ACCCGToGPU.cpp
M mlir/test/Dialect/OpenACC/acc-cg-to-gpu-thread-private-storage-remark.mlir
Log Message:
-----------
[mlir][openacc] Update remark for privates (#227074)
Update the "thread-private" term to use "Local memory or registers" for
privates remark printing.
Co-authored-by: Yian Su <yians at nvidia.com>
Commit: 0408ea5cf54710e0db1b2492b1fbb03d4c0f5268
https://github.com/llvm/llvm-project/commit/0408ea5cf54710e0db1b2492b1fbb03d4c0f5268
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M llvm/lib/Target/X86/X86FastISel.cpp
A llvm/test/CodeGen/X86/fast-isel-shift.ll
Log Message:
-----------
X86: Mark the EFLAGS def of FastISel selected shifts dead (#227060)
Co-authored-by: Claude Opus 5 <noreply at anthropic.com>
Commit: 3f10d989c803cc2bbc4e0a1a741eb9408979b19b
https://github.com/llvm/llvm-project/commit/3f10d989c803cc2bbc4e0a1a741eb9408979b19b
Author: ahradwan2-public <ahmedwahab1997 at gmail.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
Log Message:
-----------
[InstCombine][NFC] Use uint64_t for ExtractIdx in vector_extract fold (#225156)
## Summary
This changes `ExtractIdx` from `unsigned` to `uint64_t` in the
`Intrinsic::vector_extract` case.
unsigned ExtractIdx = cast<ConstantInt>(Idx)->getZExtValue();
`ExtractIdx` is initialized from the extract index operand via
`getZExtValue()` , which returns `uint64_t`. In the
`get_active_lane_mask` sub-case, it is scaled and compared against the
mask's upper bound:
if (ExtractIdx * ScaleFactor >= ALMUpperBound->getZExtValue())
Here `ALMUpperBound->getZExtValue()` returns `uint64_t`, and
`ScaleFactor` is `unsigned`.
With `ExtractIdx` declared `unsigned`, the value from `getZExtValue()`
is truncated to 32 bits, and the product `ExtractIdx * ScaleFactor` is
computed in 32 bits before being widened to compare against the
`uint64_t` right-hand side. Declaring `ExtractIdx` as `uint64_t` removes
the truncation and performs the comparison in the same width as the RHS.
Assisted by: Cline
---------
Co-authored-by: Ahmed Radwan <ahradwan at amd.com>
Commit: c8ae6e04d629ee08b74248155143698e0e31e6d5
https://github.com/llvm/llvm-project/commit/c8ae6e04d629ee08b74248155143698e0e31e6d5
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/AArch64/lcssa-phi-extract-scale.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/trimmed-subtree-schedule-operands.ll
Log Message:
-----------
[SLP]Schedule instructions with calculated deps after trimming
Cancelling the bundles of the trimmed nodes clears all the dependencies
in the scheduling region, but they are recalculated only for the
remaining bundles, the trimmed scalars and their users. The
instructions, whose dependencies were calculated earlier (e.g. for the
bundles, failed to be scheduled), are not scheduled anymore and are
moved above all the scheduled instructions, breaking the original order.
Recalculate the dependencies for all such instructions.
Fixes the regression, reported in
https://github.com/llvm/llvm-project/pull/226268#issuecomment-5872192154
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/227083
Commit: f2b0119d0bb724ab31124ed84a51d36eb5fe1857
https://github.com/llvm/llvm-project/commit/f2b0119d0bb724ab31124ed84a51d36eb5fe1857
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/dereferenceable-declaration.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/dropped_debug_info_assert.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-assert-align.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-abi-attribute-hints.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-implicit-args.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-non-fixed.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-return-values.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-sret.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-indirect-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-sibling-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-call.ll
M llvm/test/CodeGen/AMDGPU/call-c-function.ll
M llvm/test/CodeGen/AMDGPU/call-defs-mode-register.ll
M llvm/test/CodeGen/AMDGPU/irtranslator-whole-wave-functions.ll
M llvm/test/CodeGen/AMDGPU/isel-amdgpu-cs-chain-cc.ll
M llvm/test/CodeGen/AMDGPU/isel-whole-wave-functions.ll
M llvm/test/CodeGen/AMDGPU/mmra.ll
Log Message:
-----------
AMDGPU: Mark the return address def of SI_CALL dead (#227062)
The call writes the return address but nothing in the local function
reads the new value. Avoid needing to recover the dead flag later.
Co-authored-by: Claude Opus 5 <noreply at anthropic.com>
Commit: b9c1e19ac6d105ccd98db107716f27e96695625d
https://github.com/llvm/llvm-project/commit/b9c1e19ac6d105ccd98db107716f27e96695625d
Author: Kunal Pathak <kunalspathak at hotmail.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopIdiomVectorize.cpp
A llvm/test/Transforms/LoopIdiom/AArch64/find-first-byte-nested.ll
Log Message:
-----------
[LoopIdiomVectorize] Don't add the match-index block to the parent loop when it exits (#225576)
`expandFindFirstByte` unconditionally adds BB4, the block that computes
the index of the match, to the parent loop. BB4 branches only to
ExitSucc. When the `find_first_of` idiom is nested inside another loop,
and a match exits that enclosing loop, BB4 always leaves the parent loop
and so is not part of it. `LoopInfo` is then inconsistent, and
`LoopBase::verifyLoop()` fails with `"Loop block has no in-loop
successors!"`.
A release build compiles that check out. It instead crashes later, in a
pass that consumes the stale analysis. IndVarSimplify is the one seen in
practice.
Only add BB4 to the parent loop when the parent loop contains ExitSucc.
The sibling `expandFindMismatch` is unaffected, because its success path
lands in a block split out of the preheader, which is inside the parent
loop already.
This is a regression from #101976. It reproduces from 21.1.0 through
main. It needs `+sve2` in practice, because the expansion is gated on
the cost of `llvm.experimental.vector.match`.
Fixes: https://github.com/llvm/llvm-project/issues/225571
Assisted-by: GPT-5.6
Commit: 2f5fba5abf122845eef6c485fed67bd5de1e2d11
https://github.com/llvm/llvm-project/commit/2f5fba5abf122845eef6c485fed67bd5de1e2d11
Author: janr-bay <jrehders at baylibre.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M llvm/lib/Target/ARM/ARMAsmPrinter.cpp
M llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
M llvm/lib/Target/ARM/ARMBlockPlacement.cpp
M llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
M llvm/lib/Target/ARM/ARMFixCortexA57AES1742098Pass.cpp
M llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
M llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
M llvm/lib/Target/ARM/MVETPAndVPTOptimisationsPass.cpp
M llvm/lib/Target/ARM/MVETailPredUtils.h
M llvm/lib/Target/ARM/Thumb1FrameLowering.cpp
M llvm/lib/Target/ARM/Thumb1InstrInfo.cpp
Log Message:
-----------
[ARM] Replace uses of ARM::NoRegister with Register() or isValid() NFC (#224083)
Same as https://github.com/llvm/llvm-project/pull/220227 but for the ARM
backend. This replaces remaining uses of ARM::NoRegister and unsigned
with the Register class in lib/Target/ARM.
Commit: 194c292ff93cf82be3064c94d405b9171d776164
https://github.com/llvm/llvm-project/commit/194c292ff93cf82be3064c94d405b9171d776164
Author: nvptm <pmathew at nvidia.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M mlir/include/mlir/Dialect/OpenACC/Transforms/Passes.td
M mlir/lib/Dialect/OpenACC/Transforms/ACCBindRoutine.cpp
A mlir/test/Dialect/OpenACC/acc-bind-routine-missing-materialization.mlir
M mlir/test/Dialect/OpenACC/acc-bind-routine.mlir
M mlir/test/Dialect/OpenACC/acc-cg-to-gpu-bound-routine-call.mlir
A mlir/test/Dialect/OpenACC/acc-materialize-routine-bind-targets-invalid.mlir
Log Message:
-----------
[mlir][OpenACC] Materialize routine bind targets before parallel call rewriting. (#227035)
Separate string-bound OpenACC routine target materialization from call
rewriting.
Add a module-level pass that creates declarations for string-bound
routine targets before the existing per-function ACCBindRoutine pass
rewrites calls. Run the new pass once on the outer module and once on
each GPU module. Remove declaration creation from ACCBindRoutine.
Extend coverage with two outer-module callers and two GPU callers that
reference the same bound routine, a GPU-module-local routine case, and
negative tests for missing materialization and invalid pass placement.
Update the pipeline test to verify ordering in both outer-module and
GPU-module pipelines.
Commit: e5b60e5dfcce8f985296a512a74386b722572b8a
https://github.com/llvm/llvm-project/commit/e5b60e5dfcce8f985296a512a74386b722572b8a
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M llvm/include/llvm/CodeGen/SDPatternMatch.h
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/unittests/CodeGen/SelectionDAGPatternMatchTest.cpp
Log Message:
-----------
[SDPatternMatch] Make m_SetCC work like m_ICmp from IR PatternMatch. (#226623)
The condition code is stored an operand, but we don't need to expose
that to the interface.
This adds 2 signatures of m_Setcc, one that takes 2 operands and matches
any condition code and one that takes the matched condition code by
reference. For m_SpecificCondCode cases, I've added m_SpecificSetCC.
Similar changes have been applied to m_SelectCC and m_SelectCCLike.
Out of tree targets will need to update to the new interface.
Assisted-by: Claude
Commit: 57012c694b24252493e0274c69e0d6471adfd337
https://github.com/llvm/llvm-project/commit/57012c694b24252493e0274c69e0d6471adfd337
Author: Jan Leyonberg <jan_sjodin at yahoo.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M clang/lib/CIR/Dialect/Transforms/TargetLowering/CIRABIRewriteContext.cpp
Log Message:
-----------
[CIR] Fix order of creation so that lit test will not fail (#226706)
This patch fixes the order of creation, otherwise the compiler may
evaluate one before the other and the lit test fail.
Commit: 844f9339a276cf18b7aac38c89f02a0d42e2339b
https://github.com/llvm/llvm-project/commit/844f9339a276cf18b7aac38c89f02a0d42e2339b
Author: Jeff Bailey <jbailey at raspberryginger.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M libc/config/linux/aarch64/entrypoints.txt
M libc/config/linux/arm/entrypoints.txt
M libc/config/linux/i386/entrypoints.txt
M libc/config/linux/riscv/entrypoints.txt
M libc/config/linux/x86_64/entrypoints.txt
M libc/include/pwd.yaml
M libc/src/__support/pwd/flat_file_db.h
M libc/src/pwd/CMakeLists.txt
A libc/src/pwd/getpwent_r.cpp
A libc/src/pwd/getpwent_r.h
M libc/src/pwd/pwd_utils.cpp
M libc/src/pwd/pwd_utils.h
M libc/test/src/pwd/CMakeLists.txt
A libc/test/src/pwd/getpwent_r_test.cpp
Log Message:
-----------
[libc] Add getpwent_r entrypoint (#226966)
Add the reentrant password database iteration entrypoint getpwent_r.
getpwent_r reads the next password database record from the stream into
the caller-supplied struct passwd and buffer, returning 0 on success,
ENOENT at end-of-file, or an error number (such as ERANGE) on failure.
When a record exceeds the caller buffer size, FlatFileDatabase::getnext
rewinds the stream to the beginning of that record so that a subsequent
retry with a larger buffer reads the same entry.
* Add getpwent_r entrypoint and pwd::read_next fixed-buffer overload
* Rewind stream on ERANGE in FlatFileDatabase::getnext(EntryType *,
span<char>)
* Define getpwent_r in include/pwd.yaml and Linux entrypoints.txt
* Add unit tests for getpwent_r
Assisted-by: Automated tooling, human reviewed.
Commit: d66a1931ed18ee715090b87fc778e619ec8e2a42
https://github.com/llvm/llvm-project/commit/d66a1931ed18ee715090b87fc778e619ec8e2a42
Author: Erich Keane <ekeane at nvidia.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenAtomic.cpp
M clang/test/CIR/CodeGen/atomic.c
Log Message:
-----------
[CIR] Correct 2 lowering bugs of atomic cmp-xchng builtins (#227054)
This patch fixese two bugs that showed up in a benchmark.
First; convertToAtomicIntPointer was zero-filling the source object
directly, rather than the temporary. The result was that anything that
would not be overwritten thanks to the power-of-2 write, would be
incorrect, and corrupted.
Second; emitAtomicCmpXchg didn't set the 'old' value back into the real
object. This ends up doing an additional argument on this function that
better matches classic-codegen.
Commit: 620ad7e90ade5051e34410496ab2a241223d28a6
https://github.com/llvm/llvm-project/commit/620ad7e90ade5051e34410496ab2a241223d28a6
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
M llvm/test/Transforms/InstCombine/truncating-saturate.ll
Log Message:
-----------
[InstCombine] Match swapped form of truncating saturation clamp (#226614)
Extend the fold added in #189703 to also handle the inverted select:
trunc (select (icmp ugt A, DestTy_umax), sext(icmp sgt A, 0), A) -->
trunc (smin (smax (0, A), DestTy_umax))
InstCombine canonicalizes (A & NegPow2) != 0 into the ult form with
swapped select operands, but if SCCP first rewrites the compare as
icmp uge A, C, InstCombine only turns it into icmp ugt and never swaps
the select, so the original fold is missed.
While here, match the compare constant with m_APInt instead of
m_Constant + getUniqueInteger, and build TruncatedMax directly with
APInt::getLowBitsSet. Comparing the constant against TruncatedMax + 1
or TruncatedMax makes the separate zero check unnecessary.
Co-Authored-By: Claude Opus 5.5 (1M context) <noreply at anthropic.com>
Commit: 5ab44c4cd1e9e414eb6f9277f243a2a9c8db7048
https://github.com/llvm/llvm-project/commit/5ab44c4cd1e9e414eb6f9277f243a2a9c8db7048
Author: Mariusz Sikora <mariusz.sikora at amd.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M clang/include/clang/Basic/BuiltinsAMDGPU.td
M clang/include/clang/Basic/BuiltinsAMDGPUDocs.td
M clang/lib/Sema/SemaAMDGPU.cpp
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx12-err.cl
A clang/test/CodeGenOpenCL/builtins-amdgcn-gfx13-err.cl
A clang/test/CodeGenOpenCL/builtins-amdgcn-gfx13-w32-err.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx13.cl
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scale.pk32.gfx13.ll
Log Message:
-----------
[AMDGPU] Add intrinsics and builtins for v_cvt_scale_pk32_* instructions (#222617)
Commit: 0a7dc5213f12d3acd69898efb2033f80530c785b
https://github.com/llvm/llvm-project/commit/0a7dc5213f12d3acd69898efb2033f80530c785b
Author: Kazu Hirata <kazu at google.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M llvm/include/llvm/ADT/DenseMap.h
Log Message:
-----------
[ADT] Remove CRTP from DenseMapBase (NFC) (#227063)
This patch removes CRTP from DenseMapBase by replacing DerivedT with
StorageT (DenseMapStorage or SmallDenseMapStorage).
DenseMapBase now owns the Storage member by composition and provides
the entire user-facing map interface -- from constructors, the
destructor, and operator= to find, try_emplace, and erase. DenseMap
and SmallDenseMap simply specialize DenseMapBase with their respective
storage types.
This completes the effort to replace CRTP in DenseMapBase with
composition (see #168255, #226664, and #226882).
Assisted-by: Antigravity
Commit: d8a24983fe52f8deb97eecfdad332499ac5253de
https://github.com/llvm/llvm-project/commit/d8a24983fe52f8deb97eecfdad332499ac5253de
Author: Abhay Kanhere <a_kanhere at apple.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M llvm/include/llvm/IR/Verifier.h
M llvm/lib/Analysis/TypeBasedAliasAnalysis.cpp
M llvm/lib/IR/Verifier.cpp
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-i16.ll
M llvm/test/Transforms/InstCombine/struct-assign-tbaa.ll
M llvm/test/Verifier/tbaa-struct.ll
Log Message:
-----------
[Verifier] Validate !tbaa.struct metadata (#225910)
Check that !tbaa.struct operands come in (offset, size, tag) triples
with constant offset and size.
Commit: 2aa363fb173680653fa2ba913011646361abcb08
https://github.com/llvm/llvm-project/commit/2aa363fb173680653fa2ba913011646361abcb08
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
M llvm/test/Transforms/LoopVectorize/VPlan/execution-frequencies-match-bfi.ll
Log Message:
-----------
[VPlan] Compute edge probabilities via getEdgeProbabilitiesFromWeights. (#226981)
Use getEdgeProbabilitiesFromWeights (added in
https://github.com/llvm/llvm-project/pull/226560) to compute edge
probabilities like BFI.
This makes sure the VPlan-based logic combines weights of parallel edges
like BFI.
PR: https://github.com/llvm/llvm-project/pull/226981
Commit: 8085363c87a0eee12e40a49ee1b860aa9bc019f3
https://github.com/llvm/llvm-project/commit/8085363c87a0eee12e40a49ee1b860aa9bc019f3
Author: Alex Duran <alejandro.duran at intel.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M offload/test/offloading/shared_lib_global_var.c
Log Message:
-----------
[offload][omp] Mark shlib_global_var test unsupported for NVIDIA (#227098)
The shared library test introduced in #226980 seems to fail with NVIDIA
backend. Marking it unsupported.
Commit: bf1009b31706708886bd15fb6b3b2a4f17de03b7
https://github.com/llvm/llvm-project/commit/bf1009b31706708886bd15fb6b3b2a4f17de03b7
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
M llvm/lib/Target/X86/X86FastISel.cpp
M llvm/utils/TableGen/FastISelEmitter.cpp
Log Message:
-----------
FastISel: Assert the emitted instruction defines the result (#226502)
The fallback path copied the result out of implicit_defs()[0], assuming
the first implicit physical register def is the result. That is an X86
assumption about MUL/IMUL, and it is unreachable for all but
fastEmitInst_r: FastISelEmitter skips any instruction whose first
operand is not an output register, so every opcode reaching these
helpers from generated code has an explicit def.
Co-authored-by: Claude Opus 5 <noreply at anthropic.com>
Commit: 16036fdccdbcc14b5ae6afb54529733bb9741b0f
https://github.com/llvm/llvm-project/commit/16036fdccdbcc14b5ae6afb54529733bb9741b0f
Author: Jeff Bailey <jbailey at raspberryginger.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M libc/config/linux/aarch64/entrypoints.txt
M libc/config/linux/arm/entrypoints.txt
M libc/config/linux/i386/entrypoints.txt
M libc/config/linux/riscv/entrypoints.txt
M libc/config/linux/x86_64/entrypoints.txt
M libc/include/grp.yaml
M libc/src/grp/CMakeLists.txt
A libc/src/grp/getgrouplist.cpp
A libc/src/grp/getgrouplist.h
M libc/src/grp/grp_utils.cpp
M libc/src/grp/grp_utils.h
M libc/test/src/grp/CMakeLists.txt
A libc/test/src/grp/getgrouplist_test.cpp
Log Message:
-----------
[libc] Add getgrouplist entrypoint (#226958)
Add the getgrouplist entrypoint from <grp.h> (BSD extension), which
scans the group database to obtain the list of groups to which a user
belongs.
The base group passed by the caller is included unconditionally, and
supplementary groups for the user are gathered with duplicate group IDs
suppressed. A small-buffer-optimised container avoids heap allocations
for users belonging to up to 32 groups, falling back to dynamic
allocation when more groups are present. Note that this fallback does
not use AllocChecker because it relies on realloc to grow the buffer.
The lookup uses a scoped database stream to avoid disturbing concurrent
iteration.
Assisted-by: Automated tooling, human reviewed.
Commit: 4f92dab3bff4c09d78ac3d4567633f2604320446
https://github.com/llvm/llvm-project/commit/4f92dab3bff4c09d78ac3d4567633f2604320446
Author: Daria Sukhonina <dariasukhonina at gmail.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M mlir/docs/Tools/mlir-reduce.md
M mlir/lib/Reducer/ReductionNode.cpp
M mlir/test/mlir-reduce/reduction-tree/doc-example.mlir
A mlir/test/mlir-reduce/reduction-tree/except-last.mlir
A mlir/test/mlir-reduce/script/except-last.sh
Log Message:
-----------
[MLIR] Fix mlir-reduce splitting smallest range instead of the largest one (#214738)
The function `max_element` expects comparison lambda function to return
true if first argument is **less** than the second one, which is the
opposite to the current code.
Commit: 348d23c3b238016836d84ba30aa573ba3a39649d
https://github.com/llvm/llvm-project/commit/348d23c3b238016836d84ba30aa573ba3a39649d
Author: Nick Desaulniers <ndesaulniers at google.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M libcxx/include/__chrono/convert_to_tm.h
Log Message:
-----------
[libc++][chrono] Initialize optional tm_zone member in __convert_to_tm (#220068)
Defensively initialize `struct tm`'s optional `tm_zone` member in
`__convert_to_tm` before passing it to `strftime` or `time_put`.
`tm_zone` is a BSD extension standardized in POSIX.1-2024, but is not
part
of standard C or C++ (and is absent on Windows). Instead of guarding
with
`#ifdef __GLIBC__`, use `if constexpr (requires ...)` so it is
initialized
on all platforms that provide it (such as Bionic, musl, macOS, and BSDs,
whether typed as `const char*` or `char*`).
Assisted-by: Gemini
Commit: 8d752fbc26fe62687b8005438c66e55191fb2db3
https://github.com/llvm/llvm-project/commit/8d752fbc26fe62687b8005438c66e55191fb2db3
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPCompatibilityAnalysis.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPMemoryUtils.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPShuffleAnalysis.h
M llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPUtils.cpp
Log Message:
-----------
[SLP][NFC]Broader use of filter/isa ranges
Most of loops of the form "for (...) { if (cond) continue; ... }"
become make_filter_range, and dyn_cast-and-skip loops become
make_isa_range.
Assisted-by: Cursor
Reviewers: bababuck
Pull Request: https://github.com/llvm/llvm-project/pull/226535
Commit: 385d0745697eb9ec81617eeaebe62bc5280cf3a0
https://github.com/llvm/llvm-project/commit/385d0745697eb9ec81617eeaebe62bc5280cf3a0
Author: Nico Weber <thakis at chromium.org>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M llvm/utils/gn/secondary/clang/unittests/Basic/BUILD.gn
Log Message:
-----------
[gn build] Port 5c20fe98552a (#227114)
Commit: cdbca60c7d5f41ec7f332341f97f16e4e2e221cb
https://github.com/llvm/llvm-project/commit/cdbca60c7d5f41ec7f332341f97f16e4e2e221cb
Author: Alex MacLean <amaclean at nvidia.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.h
M llvm/lib/Transforms/Scalar/InferAddressSpaces.cpp
M llvm/test/CodeGen/NVPTX/forward-ld-param.ll
A llvm/test/CodeGen/NVPTX/infer-volatile-address-spaces.ll
M llvm/test/CodeGen/NVPTX/local-stack-frame.ll
M llvm/test/CodeGen/NVPTX/lower-byval-args.ll
A llvm/test/Transforms/InferAddressSpaces/NVPTX/volatile.ll
Log Message:
-----------
[InferAddressSpaces] Check volatile support in the destination AS (#224702)
Perviously we nonsensically checked the old address space...
Avoid introducing a regression by adding ADDRESS_SPACE_SHARED_CLUSTER to
NVPTX hasVolatileVariant.
Commit: dc306a24fefef0e3cbde890bc25e30d4b753498f
https://github.com/llvm/llvm-project/commit/dc306a24fefef0e3cbde890bc25e30d4b753498f
Author: Farzon Lotfi <farzonlotfi at microsoft.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M clang/lib/CodeGen/CGExprScalar.cpp
M clang/test/CodeGenHLSL/BasicFeatures/MatrixElementTypeCast.hlsl
M clang/test/CodeGenHLSL/BasicFeatures/VectorElementwiseCast.hlsl
Log Message:
-----------
[HLSL] Build elementwise cast results from poison (#225591)
I noticed this unnecessary alloca while doing this pr:
https://github.com/llvm/llvm-project/pull/225519
The change is to initialize vector and matrix elementwise cast results
with poison instead of loading uninitialized temporary storage.
We do this because every result element is overwritten before use,
making the temporary allocation and load unnecessary.
Commit: c5f99a117bd799b43cd26880a9dccb96b33767ff
https://github.com/llvm/llvm-project/commit/c5f99a117bd799b43cd26880a9dccb96b33767ff
Author: Borys Perski <borys.perski at intel.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M clang/test/CodeGen/X86/sse41-builtins-constrained.c
M clang/test/CodeGen/X86/sse41-builtins.c
Log Message:
-----------
[clang][X86] Fix round builtins tests (#226708)
Fixed minor issues in round builtins tests. Noticed them while working on #215787.
Commit: a69848d73eb5134b86c56ed9937b6a91d84472f9
https://github.com/llvm/llvm-project/commit/a69848d73eb5134b86c56ed9937b6a91d84472f9
Author: Mircea Trofin <mtrofin at google.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M llvm/utils/profcheck-xfail.txt
Log Message:
-----------
[profcheck] Exclude find-first-byte-nested.ll (#227121)
We only fixed x86 for LoopIdiom. PR #225576 added a test that looks like
it's just exposing existing propagation issues.
Commit: 285a8656517a05596a91a8f104c9c6b592b8e144
https://github.com/llvm/llvm-project/commit/285a8656517a05596a91a8f104c9c6b592b8e144
Author: Nico Weber <thakis at chromium.org>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M llvm/utils/gn/build/BUILD.gn
M llvm/utils/gn/build/BUILDCONFIG.gn
M llvm/utils/gn/secondary/clang/tools/clang-repl/BUILD.gn
M llvm/utils/gn/secondary/clang/unittests/Interpreter/BUILD.gn
M llvm/utils/gn/secondary/llvm/tools/llc/BUILD.gn
M llvm/utils/gn/secondary/llvm/tools/lli/BUILD.gn
M llvm/utils/gn/secondary/llvm/tools/llvm-jitlink/BUILD.gn
M llvm/utils/gn/secondary/llvm/tools/opt/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/Analysis/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/CodeGen/CGPluginTest/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/ExecutionEngine/Orc/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/Passes/Plugins/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/Support/DynamicLibrary/BUILD.gn
M llvm/utils/gn/secondary/third-party/unittest/unittest.gni
Log Message:
-----------
[gn] Build executables without exported symbols on macOS (#227120)
Speeds up `clang --version` from 12 ms to 4 ms on my system. 8 ms faster
startup isn't a lot, but there's also no reason not to do it.
No intended behavior change.
Commit: a8debc5a8610b955b2756ea349630a00724450bc
https://github.com/llvm/llvm-project/commit/a8debc5a8610b955b2756ea349630a00724450bc
Author: Jeremy Kun <jkun at google.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M mlir/include/mlir/Target/Cpp/CppEmitter.h
Log Message:
-----------
Add registerToCppTranslation to CppEmmitter.h (#226337)
Currently if one wants to register `mlir-to-cpp` out of tree, they must
include `mlir/InitAllTranslations.h` and depend transitively on all
translation targets (in bazel, `@llvm-project//mlir:AllTranslations`).
This change adds the registration declaration to `CppEmitter.h` so that
one can depend just on the `MLIRTargetCpp` target (or
`@llvm-project//mlir:TargetCpp` in bazel).
This matches the organization of the SMTLib codegen registration in
`mlir/include/mlir/Target/SMTLIB/ExportSMTLIB.h` (though some other
targets like `IRDLToCpp` do it differently).
Commit: 6ab3be2e5efa370c8ca539b1f5a312d7e9b2fb65
https://github.com/llvm/llvm-project/commit/6ab3be2e5efa370c8ca539b1f5a312d7e9b2fb65
Author: Nico Weber <thakis at chromium.org>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M llvm/utils/gn/build/mac_sdk.gni
Log Message:
-----------
[gn] bump deployment target to macOS 13 (#227124)
macOS 13 is four years old by now.
This has the effect that lld starts defaulting to chained fixups with
this. Chained fixups reduces `clang --version` from 4 ms to 3.2 ms. (Not
that it matters.)
(Without #227120, chained fixups reduce `clang --version` from 12.5 ms
to 10.9 ms.)
No behavior change.
Commit: 4ca8a56ba3c579c01c3a9e30c6b972b8baaad208
https://github.com/llvm/llvm-project/commit/4ca8a56ba3c579c01c3a9e30c6b972b8baaad208
Author: Hugo Melder <service at hugomelder.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M clang/lib/CodeGen/CGObjCRuntime.cpp
A clang/test/CodeGenObjC/exceptions-seh.m
Log Message:
-----------
[ObjC][SEH] Fix clang crash when using finally statements (#176779)
When targeting a platform that does not have funclet-based EH, we push
the finally cleanup (normal edge) and catchall (unwind edge) onto the
EHStack _before_ pushing all catch handlers. The try statement is then
emitted and catch handlers popped from EHStack. Last, the finally
cleanup is popped from EHStack.
For funclet-based EH, we outline and push the finally funclet (of type
`NormalAndEHCleanup`) onto the EHStack _after_ pushing the catch
handlers and never pop it. This results in a crash during codegen when
we try to emit the catch handlers. Not popping the finally cleanup from
the EHStack results in incorrect calls to cleanup handlers in nested
try/catch/finally statements.
I fixed the two issues by:
1. Pushing the finally cleanup first, and
2. Popping it at the end of `CGObjCRuntime::EmitTryCatchStmt`.
Fixes #51899
Commit: c021bb407f8eb2e3dac57cae5760a258a4564f5c
https://github.com/llvm/llvm-project/commit/c021bb407f8eb2e3dac57cae5760a258a4564f5c
Author: Nico Weber <thakis at chromium.org>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
Log Message:
-----------
[gn] bump deployment target to macOS 13 (#227124)
macOS 13 is four years old by now.
This has the effect that lld starts defaulting to chained fixups with
this. Chained fixups reduces `clang --version` from 4 ms to 3.2 ms. (Not
that it matters.)
(Without #227120, chained fixups reduce `clang --version` from 12.5 ms
to 10.9 ms.)
No behavior change.
Commit: c87ad07c33661ca39ec512c834d01f17375673f4
https://github.com/llvm/llvm-project/commit/c87ad07c33661ca39ec512c834d01f17375673f4
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPMemoryUtils.cpp
Log Message:
-----------
[SLP][NFC]Fix build for MSVC compiler, NFC
Reported in https://lab.llvm.org/buildbot/#/builders/46/builds/42017
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/227129
Commit: 64907b6d3201f1755a149d029b3a65c4e0ee663f
https://github.com/llvm/llvm-project/commit/64907b6d3201f1755a149d029b3a65c4e0ee663f
Author: Joel Dice <joel.dice at akamai.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M libcxxabi/src/cxa_personality.cpp
M libunwind/include/unwind_wasm.h
M libunwind/src/Unwind-wasm.c
M llvm/include/llvm/IR/RuntimeLibcalls.td
M llvm/lib/CodeGen/WasmEHPrepare.cpp
M llvm/test/CodeGen/WebAssembly/eh-lsda.ll
M llvm/test/CodeGen/WebAssembly/exception-legacy.ll
M llvm/test/CodeGen/WebAssembly/exception.ll
M llvm/test/CodeGen/WebAssembly/wasm-eh-prepare.ll
Log Message:
-----------
fix Wasm exceptions + coop threading + shared libraries (#222747)
Prior to this commit, the combination of Wasm exception handling,
cooperative multithreading, and shared libraries was broken.
Specifically, the code generation in `WasmEHPrepare.cpp` involved
direct, cross-library access to `libunwind.so`'s thread-local
`__wasm_lpad_context` variable. However, the ABI used for cooperative
multithreading does not support cross-library access to thread-local
variables.
The solution used here is to add a new `_Unwind_GetWasmLPadContext`
function to `libunwind.so` and use that to get address of the
`__wasm_lpad_context` for the current thread, both in the code generated
by `WasmEHPrepare.cpp` and in the `__gxx_wasm_personality_v0` function
defined in `cxa_personality.cpp`. I've used this strategy
unconditionally for all targets, regardless of whether cooperative
multithreading and/or position-independent are enabled. If desired (e.g.
for performance or code complexity reasons), I could make it conditional
on both of those features being enabled and fall back to using
`__wasm_lpad_context` directly otherwise.
Co-authored-by: Derek Schuff <dschuff at chromium.org>
Commit: c6b15d38928d586064932c3cc26d8c777e104196
https://github.com/llvm/llvm-project/commit/c6b15d38928d586064932c3cc26d8c777e104196
Author: Sam Clegg <sbc at chromium.org>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M lld/test/wasm/check-arch-32-in-64.test
M lld/test/wasm/check-arch-64-in-32.test
M lld/wasm/InputFiles.cpp
Log Message:
-----------
[lld][WebAssembly] Fix error message when linking wasm64 file with -mwasm32 (#227091)
When `-mwasm32` is explicitly passed and a wasm64 object file is linked,
the error message previously stated:
"wasm32 object file can't be linked in wasm64 mode". Fix this to report
that the wasm64 object file cannot be linked in wasm32 mode.
Commit: 60f717946cb5ca911b6be22169b9bd646225c59f
https://github.com/llvm/llvm-project/commit/60f717946cb5ca911b6be22169b9bd646225c59f
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M .github/workflows/libcxx-pr-benchmark.yml
M .github/workflows/libcxx-pr-test-tools.yml
Log Message:
-----------
[libc++] Move test tools CI job back to k8s runner sets (#226564)
While the issue with k8s runners in #226230 is still not resolved, it is
better to target the k8s runners and get transient failures than to
target the old runners and have the jobs hang forever (there seems to be
no runners registered in llvm-premerge-libcxx-runners).
Co-authored-by: Aiden Grossman <aidengrossman at google.com>
Commit: 6fee55d8425e735e652968007ee0d6bc35aa6f26
https://github.com/llvm/llvm-project/commit/6fee55d8425e735e652968007ee0d6bc35aa6f26
Author: Ron Green [NVIDIA] <rogreen at nvidia.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M flang/include/flang/Support/Fortran-features.h
M flang/lib/Semantics/check-declarations.cpp
A flang/test/Semantics/bind-c20.f90
A flang/test/Semantics/bind-c21.f90
Log Message:
-----------
[flang][Semantics] Warn on BIND(C) interfaces with assumed-shape/rank dummies (#225965)
## Motivation
Fortran 2018 §18.3.6 requires assumed-shape, deferred-shape, and
assumed-rank `BIND(C)` dummy arguments to be passed using a CFI
descriptor (`CFI_cdesc_t`). Some existing C/C++ interfaces predate this
requirement and expect such an argument to be passed by bare address
instead. Declaring a `BIND(C)` Fortran interface against such code
currently produces a silent calling-convention mismatch — no diagnostic
warns the user that the ABI they've declared doesn't match what
pre-2018 C/C++ code expects.
## What this PR does
Adds a portability warning in `CheckSubprogram`
(`flang/lib/Semantics/check-declarations.cpp`) that fires when a
`BIND(C)` interface declares an assumed-shape or assumed-rank dummy
argument, under a new `UsageWarning` category, `BindCArrayDescriptor`.
The warning is **off by default** and enabled by `-pedantic` (or
individually via `-Wbind-c-array-descriptor`), matching the existing
precedent set by other portability-only categories in the same enum
(e.g. `CharacterInteroperability`, `LogicalVsCBool`).
To avoid firing on compiler-provided runtime libraries that
legitimately dispatch through CFI-descriptor-consuming `BIND(C)`
wrappers (e.g. an OpenACC runtime module's internal specific procedures
for generic entry points like `acc_copyin`), the warning is suppressed
when the `BIND(C)` binding name — explicit or the implicit default —
starts with `_`, which marks an implementation-internal interface
rather than genuine external interoperability.
This is a **pure diagnostic** — no lowering, `LoweringOptions`, or
codegen changes of any kind. It does not alter how any argument is
actually passed.
## Test plan
- `flang/test/Semantics/bind-c20.f90`: assumed-shape and assumed-rank
dummies warn under `-pedantic` (both default and explicit `BIND(C)
NAME=`); explicit-shape dummies and a leading-underscore binding name
do not.
- `flang/test/Semantics/bind-c21.f90`: the same
assumed-shape/assumed-rank
interfaces produce no diagnostic without `-pedantic`.
- Existing `flang/test/Semantics` and `flang/test/Lower/HLFIR` lit
suites
(1752 tests) pass.
- Verified no false positives against real OpenACC (`use openacc`,
`-acc=gpu`) and CUDA Fortran (`use cudafor`, `-cuda`) runtime API
calls, plus a static scan of all `cu*.mod` runtime interface modules
confirming none use the assumed-shape/rank `BIND(C)` pattern this
warning targets outside the excluded underscore-prefixed convention.
- Full `precommit.py` regression run found zero regressions
attributable to this change (all observed failures traced to an
unrelated, pre-existing upstream crash, confirmed via an A/B control
build with this change fully reverted).
🤖 Generated with [Claude Code](https://claude.com/claude-code)
Commit: f95e5ea5a5eb719e05754de235aaba8e20e6a36b
https://github.com/llvm/llvm-project/commit/f95e5ea5a5eb719e05754de235aaba8e20e6a36b
Author: Nico Weber <thakis at chromium.org>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M llvm/utils/gn/secondary/clang/include/clang/Config/BUILD.gn
Log Message:
-----------
[gn] Fix Interpreter/emulated-tls.cpp on mac (#227132)
In, #225475 (5dfe8605911e), CLANG_HAVE_EMUTLS_GET_ADDRESS got hardcoded
to 0 in the GN build, while the CMake build has a config-time check for
__emutls_get_address.
On mac and linux, compiler-rt provides that symbol, so set
CLANG_HAVE_EMUTLS_GET_ADDRESS to 1 there. That way, __emutls_get_address
is force-linked as absolute symbol and things are happy.
(With it set to 0. clang-repl dlsym()s for the symbol, which works on
Linux where it's found in libgcc_s.so.1, but it doesn't work on mac.)
Commit: 9f009662f3fba1d8955e5e79261c60c2f98d24b6
https://github.com/llvm/llvm-project/commit/9f009662f3fba1d8955e5e79261c60c2f98d24b6
Author: Delaram Talaashrafi <dtalaashrafi at nvidia.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M mlir/include/mlir/Dialect/OpenACC/OpenACCCGAttributes.td
M mlir/include/mlir/Dialect/OpenACC/OpenACCUtilsCG.h
M mlir/lib/Dialect/OpenACC/Transforms/ACCComputeLowering.cpp
M mlir/lib/Dialect/OpenACC/Utils/OpenACCUtilsCG.cpp
M mlir/test/Dialect/OpenACC/acc-compute-lowering-loop.mlir
M mlir/unittests/Dialect/OpenACC/OpenACCUtilsCGTest.cpp
Log Message:
-----------
[mlir][OpenACC] Record gang(static:) chunk size on lowered loops (#227037)
Lower OpenACC `gang(static:)` through compute lowering as
`acc.chunk_size`. A constant size is stored directly; `static:*` and a
non-constant size are recorded as -1. `gang(static:)` also maps to gang
dimension 1.
Commit: bc1a55167c5b0c32a755ce51597bd35a9db85660
https://github.com/llvm/llvm-project/commit/bc1a55167c5b0c32a755ce51597bd35a9db85660
Author: Alex MacLean <amaclean at nvidia.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
M llvm/lib/Target/NVPTX/NVPTXUtilities.h
M llvm/test/CodeGen/NVPTX/call_bitcast_byval.ll
M llvm/test/CodeGen/NVPTX/callchain.ll
M llvm/test/CodeGen/NVPTX/empty-type.ll
A llvm/test/CodeGen/NVPTX/fp-global.ll
M llvm/test/CodeGen/NVPTX/i1-param.ll
M llvm/test/CodeGen/NVPTX/managed.ll
M llvm/test/CodeGen/NVPTX/noreturn.ll
A llvm/test/CodeGen/NVPTX/odd-integer-width.ll
M llvm/test/CodeGen/NVPTX/param-align.ll
A llvm/test/CodeGen/NVPTX/ptr-global.ll
M llvm/test/CodeGen/NVPTX/vector-global.ll
M llvm/test/DebugInfo/NVPTX/debug-info.ll
Log Message:
-----------
[NVPTX] Consolidate AsmPrinter type and global variable printing (#222240)
Commit: 5b3ae0006a69c8a6c3cb8c1dddf3556f413aa037
https://github.com/llvm/llvm-project/commit/5b3ae0006a69c8a6c3cb8c1dddf3556f413aa037
Author: Alex MacLean <amaclean at nvidia.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
Log Message:
-----------
[NVPTX] Consolidate AsmPrinter type and global variable printing (#222240)
Commit: 1637562456ab8561fa2602a438604cac3ddf4bd0
https://github.com/llvm/llvm-project/commit/1637562456ab8561fa2602a438604cac3ddf4bd0
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPShuffleAnalysis.h
Log Message:
-----------
[SLP][NFC]Fix GCC 7 ICE and unused binding warnings, NFC
Reported in https://lab.llvm.org/buildbot/#/builders/116/builds/31627
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/227151
Commit: e59523e9a9dece16edb17341ee14ade7be8753a9
https://github.com/llvm/llvm-project/commit/e59523e9a9dece16edb17341ee14ade7be8753a9
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
Log Message:
-----------
[SLP][NFC]Fix GCC 7 ICE and unused binding warnings, NFC
Reported in https://lab.llvm.org/buildbot/#/builders/116/builds/31627
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/227151
Commit: f85fe6efc523b4f9d2ecb11ccaeefef49ab5e6f3
https://github.com/llvm/llvm-project/commit/f85fe6efc523b4f9d2ecb11ccaeefef49ab5e6f3
Author: Ian Anderson <iana at apple.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M clang/test/Driver/Inputs/MacOSX15.0.sdk/SDKSettings.json
M clang/test/Driver/Inputs/MacOSX15.1.sdk/SDKSettings.json
M clang/test/Driver/modulemap-allow-subdirectory-search.c
M clang/test/InstallAPI/Inputs/MacOSX13.0.sdk/SDKSettings.json
Log Message:
-----------
[NFC][darwin][test] Fix the hand spacing in the SDKSettings files (#227133)
I hand spaced the VersionMap keys in the SDKSettings files to make it
easier to see where the gaps are where a version of Xcode updated one
SDK but not the other. I almost got them all right, but mis-spaced one
in macOS_iOSMac.
Commit: d718391361333d378a5bce643bbdef553f81c203
https://github.com/llvm/llvm-project/commit/d718391361333d378a5bce643bbdef553f81c203
Author: Razvan Lupusoru <razvan.lupusoru at gmail.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M flang/lib/Semantics/check-acc-structure.cpp
M flang/lib/Semantics/check-acc-structure.h
A flang/test/Semantics/OpenACC/acc-routine-loop-nesting.f90
Log Message:
-----------
[flang][acc] Warn when a loop is above its routine parallelism level (#227041)
OpenACC spec allows a routine to parent a loop at its own parallelism
level or below. A higher level is not allowed: gang inside a worker
routine, gang or worker inside a vector routine, gang, worker, or vector
inside a seq routine, and a gang dimension above the routine's gang
dimension. A device-specific routine clause counts the same way.
Flang accepted these loops with no diagnostic. Warn that the clause is
ignored. A loop at the same level or below is left alone, and illegal
nesting of loops remains an error.
Commit: fbac8e1ff3b8b733183e677f49be73ab2210d7df
https://github.com/llvm/llvm-project/commit/fbac8e1ff3b8b733183e677f49be73ab2210d7df
Author: Akhil Goel <akhil.goel at intel.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
M llvm/test/CodeGen/SPIRV/legalization/signed-narrow-int.ll
Log Message:
-----------
[SPIR-V] Sign extend narrow G_SMIN/G_SMAX operands and mask sign sensitive results (#226957)
This PR includes `G_SMIN` and `G_SMAX` to the list of sign sensitive
ops. It also masks the result of the sign sensitive ops to their
original widths with a bitwise AND because the later users assume the
upper bits are zero and without masking they read the wrong value.
Commit: 0ec4a7fe84cde933c044dafdcf5cfd983f7d086c
https://github.com/llvm/llvm-project/commit/0ec4a7fe84cde933c044dafdcf5cfd983f7d086c
Author: Med Ismail Bennani <ismail at bennani.ma>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M lldb/packages/Python/lldbsuite/test/lldbplatformutil.py
Log Message:
-----------
[lldb/test] Normalize appletvos to tvos in getPlatform() (#227138)
Mirror the existing `iphoneos` -> `ios` SDK-name normalization for
`tvOS`. Without it, an `--apple-sdk` value derived from "appletvos" made
`getPlatform()` return "appletvos", which isn't in
`lldbplatform.__name_lookup`, so `platformIsDarwin(`) returned `False`
and `finalize_build_dictionary` KeyError'd before any `remote-tvos` test
could build.
Signed-off-by: Med Ismail Bennani <ismail at bennani.ma>
Commit: c894e63329c144702bd560a8807d17b489e0484b
https://github.com/llvm/llvm-project/commit/c894e63329c144702bd560a8807d17b489e0484b
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M .github/workflows/libc-fullbuild-tests.yml
M .github/workflows/libc-overlay-tests.yml
Log Message:
-----------
[Github] Temporary fix for #226230 (#227147)
We are seeing this issue in the libc++ runner sets and it can presumably
pop up in the libc runner sets as well in the case of an abnormally long
clone operation.
Commit: b1faf8bc3ebbbe70daaac47a5fcd49006be3709e
https://github.com/llvm/llvm-project/commit/b1faf8bc3ebbbe70daaac47a5fcd49006be3709e
Author: Med Ismail Bennani <ismail at bennani.ma>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M lldb/packages/Python/lldbsuite/test/lldbplatform.py
Log Message:
-----------
[lldb/test] Register xros (visionOS) as a Darwin platform (#227142)
`lldbplatform.py` never registered `xros` at all: no enum value, no
`__name_lookup` entry, and it was absent from `__darwin_embedded`/
`darwin_all`. As a result, `platformIsDarwin()` returned `False` for
`xros`, and `finalize_build_dictionary`'s fallback branch, which indexes
`platform_name_to_uname` by the raw platform name, would `KeyError`
before any visionOS test could build.
Add `xros` alongside the other embedded Darwin platforms so it's
recognized the same way `ios`/`tvos`/`watchos`/`bridgeos` already are.
Signed-off-by: Med Ismail Bennani <ismail at bennani.ma>
Commit: 619028d062d90579edb0e80fd2c0a870f83cce84
https://github.com/llvm/llvm-project/commit/619028d062d90579edb0e80fd2c0a870f83cce84
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M llvm/test/lit.cfg.py
M llvm/utils/profcheck-xfail.txt
Log Message:
-----------
[ProfCheck] Exclude DirectX (#227157)
I don't think anyone runs profiling on DirectX, so exclude it for now.
Also move AMDGPU to the normal exclusion list given there are efforts
around PGO for AMDGPU currently.
Commit: 7b5ec23c6053560e306fce71a4332e2b9793dd7e
https://github.com/llvm/llvm-project/commit/7b5ec23c6053560e306fce71a4332e2b9793dd7e
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
R llvm/test/tools/llvm-readobj/ELF/RISCV/eflags-abi.test
A llvm/test/tools/llvm-readobj/ELF/RISCV/eflags.test
Log Message:
-----------
[RISCV][llvm-readobj] Generalize the eflags-abi test to cover all of the eflags. NFC (#227152)
Assisted-by: Claude
Commit: 78f2beb7655e19b3f5a8c55dda3f7b8b20771bed
https://github.com/llvm/llvm-project/commit/78f2beb7655e19b3f5a8c55dda3f7b8b20771bed
Author: Samarth Narang <70980689+snarang181 at users.noreply.github.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M mlir/include/mlir/Dialect/SCF/IR/SCFOps.td
M mlir/lib/Conversion/SCFToControlFlow/SCFToControlFlow.cpp
M mlir/lib/Conversion/SCFToGPU/SCFToGPU.cpp
M mlir/lib/Conversion/SCFToOpenMP/SCFToOpenMP.cpp
M mlir/lib/Dialect/Async/Transforms/AsyncParallelFor.cpp
M mlir/lib/Dialect/SCF/IR/SCF.cpp
M mlir/lib/Dialect/SCF/Transforms/ParallelForToNestedFors.cpp
M mlir/lib/Dialect/SCF/Transforms/ParallelLoopCollapsing.cpp
M mlir/lib/Dialect/SCF/Transforms/ParallelLoopFusion.cpp
M mlir/lib/Dialect/SCF/Transforms/ParallelLoopTiling.cpp
M mlir/test/Conversion/SCFToControlFlow/convert-to-cfg.mlir
M mlir/test/Conversion/SCFToGPU/parallel_loop.mlir
A mlir/test/Conversion/SCFToOpenMP/scf-to-openmp-unsigned.mlir
M mlir/test/Dialect/Async/async-parallel-for-async-dispatch.mlir
M mlir/test/Dialect/SCF/ops.mlir
M mlir/test/Dialect/SCF/parallel-loop-fusion.mlir
M mlir/test/Dialect/SCF/parallel-loop-tiling-inbound-check.mlir
M mlir/test/Dialect/SCF/parallel-to-nested-fors.mlir
A mlir/test/Transforms/parallel-loop-collapsing-unsigned.mlir
Log Message:
-----------
[mlir][scf] Add unsignedCmp to scf.parallel and use it in the tiling in-bound check (#226130)
This change mirrors `scf.for` where `scf.parallel` gets an `unsignedCmp`
unit attribute, and every pass that rebuilds or lowers a `scf.parallel`
has to respect it:
- Propagate where a loop is rebuilt from another, such as parallel loop
tiling, parallel loop fusion (which also refuses to fuse loops of
different signedness), parallel-to-nested-fors and SCF-to-CF lowering.
- Decline where the bound arithmetic assumes signed values, such as
SCF-to-GPU, SCF-to-OpenMP, async-parallel-for and the
parallel-loop-collapsing test pass.
Fixes #223233
Commit: 9a0c255ce1efbd80ef501e8151d123876fa4b5d4
https://github.com/llvm/llvm-project/commit/9a0c255ce1efbd80ef501e8151d123876fa4b5d4
Author: Owen Rodley <orodley at google.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M clang/lib/CodeGen/CodeGenPGO.cpp
M compiler-rt/test/profile/instrprof-thinlto-indirect-call-promotion.cpp
M llvm/include/llvm/ProfileData/InstrProf.h
M llvm/lib/ProfileData/InstrProf.cpp
M llvm/lib/Transforms/IPO/MemProfContextDisambiguation.cpp
M llvm/lib/Transforms/Instrumentation/InstrProfiling.cpp
M llvm/lib/Transforms/Instrumentation/MemProfUse.cpp
M llvm/lib/Transforms/Instrumentation/PGOInstrumentation.cpp
M llvm/lib/Transforms/Scalar/JumpTableToSwitch.cpp
M llvm/test/Instrumentation/cgprofile.ll
M llvm/test/Transforms/JumpTableToSwitch/profile-no-guid-metadata.ll
M llvm/test/Transforms/JumpThreading/thread-prob-1.ll
M llvm/test/Transforms/PGOProfile/Inputs/cspgo_bar_sample.ll
M llvm/test/Transforms/PGOProfile/Inputs/thinlto_cspgo_bar_gen.ll
M llvm/test/Transforms/PGOProfile/Inputs/thinlto_cspgo_bar_use.ll
M llvm/test/Transforms/PGOProfile/icp_invoke.ll
M llvm/test/Transforms/PGOProfile/icp_invoke_nouse.ll
M llvm/test/Transforms/PGOProfile/thinlto_indirect_call_promotion.ll
M llvm/test/tools/gold/X86/Inputs/thinlto_cspgo_bar.ll
A llvm/test/tools/llvm-profdata/Inputs/guid-roundtrip.c
A llvm/test/tools/llvm-profdata/Inputs/guid-roundtrip.proftext
A llvm/test/tools/llvm-profdata/guid-roundtrip.test
M llvm/unittests/ProfileData/InstrProfTest.cpp
Log Message:
-----------
[InstrProf] Replace !PGOFuncName and !PGOName metadata with !guid (#214134)
!PGOFuncName and !PGOName metadata were attached to internal functions
and vtables during profile annotation to record their original
"<file>;<name>" PGO names before ThinLTO promoted and renamed them. In
post-link LTO passes, InstrProfSymtab read that metadata back so profile
records keyed by the original name's hash could still find the renamed
IR object.
Global objects now carry stable !guid metadata assigned before LTO
renaming, which records the MD5 hash of the original PGO name directly.
See: https://discourse.llvm.org/t/rfc-keep-globalvalue-guids-stable/84801
Use !guid instead of maintaining separate PGO name metadata:
- Stop emitting and reading !PGOFuncName and !PGOName in Clang and
PGOInstrumentation, and remove the metadata helper functions
(createPGOFuncNameMetadata, createPGONameMetadata,
getPGOFuncNameMetadata, and the metadata name getters).
- Unify getIRPGOFuncName(const Function &) and
getPGOName(const GlobalVariable &) into
getIRPGOObjectName(const GlobalObject &).
- In InstrProfSymtab::addFuncWithName and addVTableWithName, key each
name by its own hash as before, and also insert the object's assigned
GUID into MD5FuncMap / MD5VTableMap when it differs from the PGO name
hash. This lets lookups find functions and vtables that LTO has
renamed while preserving lookups by current, deprecated, and canonical
names.
- Remove obsolete !PGOFuncName metadata from test inputs, update the
ThinLTO ICP tests to check for !guid, and add symtab unit tests and an
llvm-profdata text/indexed round-trip test.
Assisted-by: Antigravity
Commit: eabb90030e7908fd2f15d77198c8b1e88f5463a4
https://github.com/llvm/llvm-project/commit/eabb90030e7908fd2f15d77198c8b1e88f5463a4
Author: Harrison Hao <57025411+harrisonGPU at users.noreply.github.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
M llvm/test/Transforms/InstCombine/AMDGPU/llvm.amdgcn.sudot.ll
Log Message:
-----------
[AMDGPU] Canonicalize constant operands of sudot intrinsics (#226478)
Move a constant multiplicand and its sign flag to the second operand.
For example:
```
sudot4(true, 1, false, x, acc, clamp)
->
sudot4(false, x, true, 1, acc, clamp)
```
Commit: f896873b4dddca59ec3c18487cf3f1cf6545df1e
https://github.com/llvm/llvm-project/commit/f896873b4dddca59ec3c18487cf3f1cf6545df1e
Author: Hongyu Chen <xxs_chy at outlook.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M clang/lib/Headers/riscv_packed_simd.h
M clang/test/CodeGen/RISCV/rvp-intrinsics.c
M cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoP.td
M llvm/test/CodeGen/RISCV/rvp-simd-32.ll
Log Message:
-----------
[RISCV][P-ext] Support the missing packed pair (#226992)
This patch supports the packed pair for v2i16.
Some are inconsistent with the spec because existing shuffle-lowering
transforms them into equivalent narrowing shifts or zips.
Commit: 31d7b51dbd5a8a5e58631a3c77421209f562ea5c
https://github.com/llvm/llvm-project/commit/31d7b51dbd5a8a5e58631a3c77421209f562ea5c
Author: aokblast <aokblast at FreeBSD.org>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M clang/docs/ReleaseNotes.md
M clang/test/AST/ByteCode/new-delete.cpp
R clang/test/SemaCXX/new-nothrow-by-value.cpp
Log Message:
-----------
[Clang] Add missing release note entry in #226753 (#227078)
As per the feedback from #226753, we add release note for GH-212211.
Also move the test to new-delete.cpp.
Assisted-by: Claude
Commit: 60ac6298c2e70aeeeac1ae388024bbe30f25784a
https://github.com/llvm/llvm-project/commit/60ac6298c2e70aeeeac1ae388024bbe30f25784a
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Scalar/TailRecursionElimination.cpp
A llvm/test/Transforms/TailCallElim/return-value-select-pgo.ll
M llvm/utils/profcheck-xfail.txt
Log Message:
-----------
[TailCallElim] Add profile annotations to return value selects
Tail call elimination in some cases can create selects on possible
return values conditioned on whether or not execution is currently in
what was a recursive call. That is equal to the probability with which
we recurse, which in turn can be computed from the block frequencies of
blocks that recurse and blocks that directly return.
Reviewers: mtrofin
Reviewed By: mtrofin
Pull Request: https://github.com/llvm/llvm-project/pull/202518
Commit: dae88f2450b03f9a123cd681a7f698f67bde9ece
https://github.com/llvm/llvm-project/commit/dae88f2450b03f9a123cd681a7f698f67bde9ece
Author: Aman Maurya <amanmaurya9209 at gmail.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenCoroutine.cpp
M clang/lib/CIR/CodeGen/CIRGenExprAggregate.cpp
A clang/test/CIR/CodeGenCoroutines/coro-agg.cpp
Log Message:
-----------
[CIR] Support aggregate co_await / co_yield in AggExprEmitter (#225412)
Support evaluating `co_await` and `co_yield` expressions whose result is
an aggregate type in `AggExprEmitter`.
Fixes #225317
Commit: 3b0b6d892bdf4eecf4d6fbccf26c6d91fec2d164
https://github.com/llvm/llvm-project/commit/3b0b6d892bdf4eecf4d6fbccf26c6d91fec2d164
Author: theRonShark <ron.lieberman at amd.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M clang/include/clang/CodeGen/CodeGenAction.h
M clang/include/clang/Interpreter/Interpreter.h
M clang/lib/CodeGen/BackendConsumer.h
M clang/lib/CodeGen/CodeGenAction.cpp
M clang/lib/Interpreter/CMakeLists.txt
M clang/lib/Interpreter/DeviceOffload.cpp
M clang/lib/Interpreter/DeviceOffload.h
M clang/lib/Interpreter/Interpreter.cpp
M clang/unittests/Basic/CMakeLists.txt
R clang/unittests/Basic/TargetIDTest.cpp
Log Message:
-----------
Revert "releand "[clang-repl] Implement IncrementalHIPDeviceParser for HIP device compilation"" (#227123)
Reverts llvm/llvm-project#226930
AMD author has an additional step to perform, that is still needed.
in contact with Author.
Commit: ec1b3b10a71c2181b0dfb90f1178e2e739680e02
https://github.com/llvm/llvm-project/commit/ec1b3b10a71c2181b0dfb90f1178e2e739680e02
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M flang/include/flang/Optimizer/Builder/CUDAIntrinsicCall.h
M flang/include/flang/Optimizer/Builder/CUFCommon.h
M flang/include/flang/Optimizer/Dialect/CUF/CUFOps.td
M flang/include/flang/Optimizer/Transforms/Passes.td
M flang/lib/Optimizer/Builder/CUDAIntrinsicCall.cpp
M flang/lib/Optimizer/Builder/CUFCommon.cpp
M flang/lib/Optimizer/Transforms/CMakeLists.txt
R flang/lib/Optimizer/Transforms/CUDA/CUFFunctionRewrite.cpp
M flang/lib/Optimizer/Transforms/CUDA/CUFOpConversion.cpp
M flang/lib/Optimizer/Transforms/CUDA/CUFOpConversionLate.cpp
R flang/test/Fir/CUDA/cuda-function-rewrite.mlir
A flang/test/Fir/CUDA/cuda-on-device.mlir
M flang/test/Fir/cuf.mlir
A flang/test/Lower/CUDA/cuda-on-device.cuf
Log Message:
-----------
[flang][cuda] Add cuf.on_device op and lower to it (#227089)
Replace the CUFFunctionRewrite pass, which matched fir.call names and
folded them to constants, with a cuf.on_device operation emitted when
the intrinsic is lowered. CUFOpConversion folds the operation once the
code is in its host or device context, and leaves the host copy of an
OpenACC routine unfolded so the device clone is not baked to false. Any
operation that remains is folded by the late CUF conversion, and the
rewrite pass is dropped from the pipeline.
Commit: eb3163c52e9fbea9c579c16bdb881655fb6536d5
https://github.com/llvm/llvm-project/commit/eb3163c52e9fbea9c579c16bdb881655fb6536d5
Author: forking-google-bazel-bot[bot] <265904573+forking-google-bazel-bot[bot]@users.noreply.github.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/flang/lib/Optimizer/Builder/BUILD.bazel
Log Message:
-----------
[Bazel] Fixes ec1b3b1 (#227180)
This fixes ec1b3b10a71c2181b0dfb90f1178e2e739680e02 (#227089).
Buildkite error link:
https://buildkite.com/llvm-project/upstream-bazel/builds?commit=ec1b3b10a71c2181b0dfb90f1178e2e739680e02
Co-authored-by: Google Bazel Bot <google-bazel-bot at google.com>
Commit: 2f13592fb1dee32d498c3ec2993d5f109e614abe
https://github.com/llvm/llvm-project/commit/2f13592fb1dee32d498c3ec2993d5f109e614abe
Author: Prajit Rahul <prajitrahul05 at gmail.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M mlir/include/mlir/Dialect/ControlFlow/IR/ControlFlowOps.td
M mlir/lib/Dialect/ControlFlow/IR/ControlFlowOps.cpp
M mlir/test/Dialect/ControlFlow/canonicalize.mlir
M mlir/test/Dialect/ControlFlow/invalid.mlir
M mlir/test/Dialect/ControlFlow/ops.mlir
Log Message:
-----------
[mlir][cf] Fix cf.switch round-trip for case values wider than 64 bits (#221490)
The `cf.switch` parser reads case values into `int64_t`, and its printer
uses `APInt::getLimitedValue()`, preventing values wider than 64 bits
from round-tripping. Printing negative narrow values as unsigned can
also trigger an assertion when reparsing.
Parse case values into `APInt` and print them directly, so wide and
negative values round-trip correctly. Accept signed or unsigned literals
that fit the switch operand’s bit width, and report an error for values
that do not.
Add regression tests for wide and negative values, integer-width
boundaries, out-of-range diagnostics, and case selection after parsing.
Fixes #220609
Assisted-by: Codex
Commit: fddfd6f01e3f203df3fc1d7fc7769bcb9745d0fa
https://github.com/llvm/llvm-project/commit/fddfd6f01e3f203df3fc1d7fc7769bcb9745d0fa
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M clang/lib/AST/ByteCode/Context.cpp
M clang/lib/AST/ByteCode/Context.h
M clang/lib/AST/ByteCode/EvalEmitter.cpp
M clang/lib/AST/ByteCode/EvalEmitter.h
A clang/lib/AST/ByteCode/EvalSettings.h
M clang/lib/AST/ByteCode/InterpState.cpp
M clang/lib/AST/ByteCode/InterpState.h
M clang/lib/AST/ExprConstant.cpp
Log Message:
-----------
[clang][bytecode] Add `EvalSettings` struct and replace parent `State` (#226175)
We currently always construct a full `EvalInfo` when using the bytecode
interpreter, we then pass it to the `evaluate*` function, which only
copies a few values from it.
Introduce a new `EvalSettings` struct that we pass instead of a `State`.
This is cheaper to construct and we only pass what's needed. There is
one `evaluateAsRValue` overload left that takes a parent `State`, that
will be removed in a subsequent patch.
Commit: f4085066128ac709f25c206c9701285f60a0bf83
https://github.com/llvm/llvm-project/commit/f4085066128ac709f25c206c9701285f60a0bf83
Author: Aman Maurya <amanmaurya9209 at gmail.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenExprAggregate.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.cpp
M clang/test/CIR/CodeGen/pack-indexing.cpp
Log Message:
-----------
[CIR] Support PackIndexingExpr for LValue and Aggregates (#227040)
Support `PackIndexingExpr` in `CIRGenFunction::emitLValue` and
`AggExprEmitter` by visiting its selected expression, matching classic
Clang codegen (`CGExpr.cpp` and `CGExprAgg.cpp`) and completing
`PackIndexingExpr` support across all CIR expression emitters.
Fixes #226928
Assisted by Antigravity and Gemini
Commit: 3376b1f4b2f4db8c7f5c94323e6c9a730d974247
https://github.com/llvm/llvm-project/commit/3376b1f4b2f4db8c7f5c94323e6c9a730d974247
Author: Fangrui Song <i at maskray.me>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M lld/test/ELF/pre_init_fini_array.s
M llvm/lib/MC/ELFObjectWriter.cpp
M llvm/test/CodeGen/AMDGPU/lower-ctor-dtor.ll
M llvm/test/MC/AsmParser/section_names.s
M llvm/test/MC/ELF/section.s
Log Message:
-----------
[MC,ELF] Set sh_entsize for SHT_INIT_ARRAY/FINI_ARRAY/PREINIT_ARRAY (#226875)
Match GNU Assembler: set sh_entsize to 4/8, regardless of sh_size. This
is mostly cosmetic: sh_entsize is not a useful member for non-merge
sections.
When clang-produced and GCC-produced objects are linked together, the
mismatch makes lld's output sh_entsize 0.
Commit: c5a5943133d558b7bae36fe3074e7777178e7a6e
https://github.com/llvm/llvm-project/commit/c5a5943133d558b7bae36fe3074e7777178e7a6e
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M llvm/lib/Target/X86/X86InstCombineIntrinsic.cpp
M llvm/test/Transforms/InstCombine/X86/x86-avx512-inseltpoison.ll
M llvm/utils/profcheck-xfail.txt
Log Message:
-----------
[X86][InstCombine] Fix profcheck failures (#227183)
When optimizing some AVX512 masked intrinsics, we would create a select
with a condition derived from the mask. We cannot infer the distribution
of this synthesized condition, so mark it unknown to make profcheck
green.
Commit: 9fe649af67007493c02108b484c8b9259e3d522e
https://github.com/llvm/llvm-project/commit/9fe649af67007493c02108b484c8b9259e3d522e
Author: Vladimir Shiryaev <w at tagolog.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M llvm/lib/CAS/UnifiedOnDiskCache.cpp
A llvm/test/tools/llvm-cas/validate-if-needed.test
Log Message:
-----------
[CAS] Close the stderr temp file of the out-of-process validator (#226844)
Commit: ef45ca75ce721745b997db165f18e4fdf9e93294
https://github.com/llvm/llvm-project/commit/ef45ca75ce721745b997db165f18e4fdf9e93294
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M clang/test/CodeGen/RISCV/rvp-intrinsics.c
Log Message:
-----------
[RISCV] Add common check-prefix to rvp-intrinsics.c. NFC (#227044)
A large number of test cases have the same IR for RV32 and RV64.
Commit: 876ff1506413684af43a3a61fd4ca3b999000aff
https://github.com/llvm/llvm-project/commit/876ff1506413684af43a3a61fd4ca3b999000aff
Author: Abinaya Saravanan <asaravan at qti.qualcomm.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M llvm/lib/Target/Hexagon/HexagonDepInstrInfo.td
A llvm/test/MC/Hexagon/v79-nontemporal.s
Log Message:
-----------
Add v79 scalar non-temporal forms. (#226017)
Also add support for the non-temporal forms of dcfetch and dczeroa.
Fixes https://github.com/llvm/llvm-project/issues/221485
Commit: ba67350bf808d8bef21cc2d59d7bcd0396adc29d
https://github.com/llvm/llvm-project/commit/ba67350bf808d8bef21cc2d59d7bcd0396adc29d
Author: Nico Weber <thakis at chromium.org>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M clang/lib/Sema/SemaConcept.cpp
M clang/test/CXX/temp/temp.constr/temp.constr.normal/p1.cpp
Log Message:
-----------
[clang] Consistently cache failed constraint normalization (#227086)
Previously, if substituting the parameter mappings of a normalized
constraint failed, Sema::getNormalizedAssociatedConstraints() returned
nullptr, but it stored the partially substituted normal form in
NormalizationCache. So the first lookup for such a declaration failed,
but every later lookup returned the broken normal form, and subsumption
checking and the ambiguous-constraint diagnostics then continued with
it.
I believe this wasn't intentional:
- Before #161671 (e9972debc98c), normalization was a single step, and a
failure was cached as nullptr.
- #161671 added the parameter mapping substitution step. It inserted the
normal form into the cache before substituting, and returned nullptr if
the substitution then failed, leaving the non-null normal form in the
cache.
- #165352 (2984a8db804e) moved the insertion after the substitution to
not use an invalidated iterator, but kept inserting the normal form if
the substitution failed.
To fix this, cache failed substitution as nullptr, like a failed
normalization.
As a consequences we don't emit the diagnostics that were only emitted
because the second lookup continued:
- A second "'type name' declared as a pointer to a reference" error
(with its notes) for the same broken concept. For
template<typename T> concept Foo = True<T*>;
template<typename T> concept Bar = Foo<T&>;
template<typename T> requires Bar<T> struct S { };
template<typename T> requires Bar<T> && true struct S<T> { };
the error got reported once for the partial specialization, and also for
the primary template after. Now, we only have the first report.
- A "similar constraint expressions not considered equivalent" note and
its "similar constraint expression here" note, which we computed from
the broken normal form. The actual problem in that test is the broken
constraint, which is still diagnosed.
This also makes it possible to key the normalization cache by constraint
expression without changing which diagnostics are emitted for failures,
which I want to do in a follow-up.
Commit: 633223d573713822fafbff44a05459e4f27963ba
https://github.com/llvm/llvm-project/commit/633223d573713822fafbff44a05459e4f27963ba
Author: Jiahao Guo <eoonguo at gmail.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
M clang/test/CodeGen/AArch64/neon-intrinsics.c
M clang/test/CodeGen/AArch64/neon/intrinsics.c
Log Message:
-----------
[CIR][AArch64] Lower NEON vshrn* intrinsics (#226382)
## summary
part of : https://github.com/llvm/llvm-project/issues/185382
Lower all intrinsics in :
https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#vector-shift-right-and-narrow
Assisted by : gpt-6-sol
Commit: 992ca79c83b0882465a202883109bd4cd167ec00
https://github.com/llvm/llvm-project/commit/992ca79c83b0882465a202883109bd4cd167ec00
Author: Jack Huang <jackhuang1205 at gmail.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M llvm/include/llvm/IR/IRBuilder.h
M llvm/lib/Transforms/Vectorize/VectorCombine.cpp
M llvm/test/Transforms/VectorCombine/binop-scalarize.ll
A llvm/test/Transforms/VectorCombine/cmp-scalarize.ll
M llvm/test/Transforms/VectorCombine/unary-op-scalarize.ll
Log Message:
-----------
[VectorCombine] Pass flags during IR creation (#193271)
Since commit 777d6b5, VectorCombine has been using InstSimplifyFolder to
simplify vector instructions during IR construction. When creating a new
instruction, InstSimplifyFolder may fold the operation and return an
existing operand instead of emitting a new instruction.
In such cases, copying IR flags to the returned value is incorrect and
may unintentionally propagate flags to pre‑existing instructions,
polluting the original IR. To avoid this, flags should be passed at IR
creation rather than being set after construction. Fix #192607.
Commit: a8d2c44b29e9a5caac37dc400cebca5f997ad6a6
https://github.com/llvm/llvm-project/commit/a8d2c44b29e9a5caac37dc400cebca5f997ad6a6
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
Log Message:
-----------
X86: Mark eflags clobbers dead in va_arg expansion (#227197)
Co-authored-by: Claude Opus 5 <noreply at anthropic.com>
Commit: 8d79b74443de46e78b4f2c90aa65bd42c491e909
https://github.com/llvm/llvm-project/commit/8d79b74443de46e78b4f2c90aa65bd42c491e909
Author: Timur Baidusenov <timurbaidusenov at gmail.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M polly/lib/Transform/ScheduleOptimizer.cpp
A polly/test/ScheduleOptimizer/simplify_deps_bounded_proximity.ll
Log Message:
-----------
[Polly] Keep proximity dependence exact if simplifying it unbounds its distance (#225840)
Before calling the isl scheduler, `runIslScheduleOptimizer` gists the
dependences
with the iteration domains (`-polly-opt-simplify-deps=yes`, the default
since
a26db470834a, 2012). For a statement that reads a value written in one
iteration
of a loop in all later iterations, the gist also drops the upper bound
of that
loop:
{ S[k, i, k] -> S[k, i, j] : k < j <= n - 1 } becomes { S[k, i, k] ->
S[k, i, j] : j > k }
The proximity distance along j is then unbounded. isl's Pluto-like step
needs a
bound `u·n + w` on every proximity distance, finds no row that satisfies
it, and
falls back to carrying dependences one row at a time. For floyd-warshall
this
yields a wavefront over `i + j` below the `k` loop instead of a
permutable band
`(i, j)`. That band is never tiled, and the innermost loop walks the
array
diagonally.
The patch keeps the exact proximity dependence of a statement on itself
when
the gisted dependence has unbounded distances and the exact one has
bounded
distances. Validity dependences, and dependences between different
statements,
are still gisted. The cost of the exact dependences therefore only
applies to
the few maps where the gist removed the bound; heat-3d, where keeping
all
proximity dependences exact makes scheduling take minutes, is
unaffected.
### Measurements
x86-64 (Ryzen 7 9700X), `-O3 -march=native -mllvm -polly`, baseline is
the same
compiler without the change.
| | before | after | |
|---|---|---|---|
| PolyBench 4.2.1 LARGE floyd-warshall (min of 3, pinned) | 26.7 s | 6.8
s | 3.9x |
| llvm-test-suite floyd-warshall (min of 5, pinned) | 60.9 s | 16.4 s |
3.7x |
| compile time floyd-warshall.c (min of 5) | 131 ms | 134 ms | |
| .text floyd-warshall | 4775 | 6298 | |
- Among the 30 PolyBench kernels, only floyd-warshall generates
different code.
- In llvm-test-suite (SingleSource + MultiSource), only floyd-warshall
and two
small regression tests (Regression-C-test_indvars,
GCC-C-execute-20000422-1)
change. All 2137 tests pass in both configurations. The other objects
whose
code differed between the two builds (oggenc, two TSVC programs) differ
by
Polly's pre-existing run-to-run nondeterminism; the patch did not
trigger
there.
- CTMark (`-j1`, pinned, 2 repetitions): identical generated code, total
compile
time within noise.
- With the default 32x32 tiles, floyd-warshall is still 1.2x slower than
plain
-O3 on this machine. That is a tile size effect: with
`-polly-tile-sizes=16,32`
the kernel runs in 1.6 s, 3.5x faster than -O3.
### Test
`polly/test/ScheduleOptimizer/simplify_deps_bounded_proximity.ll`:
floyd-warshall
with a parametric size; checks for the `(k)` band followed by the tiled
`(i, j)`
band. It fails without the patch, which produces the `(i + j)`
wavefront.
Assisted-by: Claude (Anthropic)
Commit: e8c09d19de8212bfb2d5c760c43a21e27729f660
https://github.com/llvm/llvm-project/commit/e8c09d19de8212bfb2d5c760c43a21e27729f660
Author: Nico Weber <thakis at chromium.org>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M clang/docs/InternalsManual.md
M clang/include/clang/Sema/Sema.h
M clang/lib/Sema/SemaConcept.cpp
Log Message:
-----------
[clang] Cache normalized constraints by expression instead of by declaration (#226620)
Sema::NormalizationCache was keyed by the constrained declaration. The
members of a class template specialization are distinct declarations for
every specialization, but they all share the uninstantiated constraint
expressions of the member of the primary template they were instantiated
from. So the constraints of e.g. the constrained constructors of
std::optional, std::span, std::pair or of the members of range adaptors
were normalized from scratch for every single specialization of those
classes that a TU uses. Normalization is expensive: it expands the whole
concept tree below the expression and substitutes the parameter mapping
at every level.
When compiling Chromium, 48%
(chrome/browser/glic/...contents_manager.cc)
to 72% (chrome/browser/ui/views/frame/browser_view.cc) of all
NormalizationCache misses were for expressions that were normalized
before
for a different declaration, and normalization is 4.5% of all compile
time
in a sampling profile.
Instead, key the cache by (expression, pack index). Each associated
constraint is cached separately, and we form the conjunction of a
declaration's associated constraints on every call. That's cheap, and
getNormalizedAssociatedConstraints() is only called on SatisfactionCache
misses and for subsumption checks. Failures are cached as nullptr, like
before.
Build time for 120 random Chromium TUs drawn with probability
proportional to their compile time:
CPU time: 470.0 s => 451.1 s, -4.0%
instructions: 4948.9e9 => 4702.7e9, -5.0%
mean max RSS: 779 MB => 710 MB, -8.9%
(To check noise level, running this with the same binary twice: +-0.04%
CPU time and +-0.01% instructions.)
Recovers some more of the time lost to #161671 and contributes to
improving issue #172266.
No behavior change on the non-error case.
(If several declarations share a constraint expression that fails to
normalize (e.g. the members of different specializations of a class
template), we now diagnose the failure once instead of once per
declaration.)
Commit: 6aeadac52d4f564e5030a1a22013ab381436cce3
https://github.com/llvm/llvm-project/commit/6aeadac52d4f564e5030a1a22013ab381436cce3
Author: David Spickett <david.spickett at arm.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M lldb/examples/python/templates/scripted_process.py
Log Message:
-----------
[lldb] Correct types for ScriptedFrame get_function_name get_display_function_name (#226938)
These claimed to return str but the initial value for self.name is None,
and the C++ side returns optional<string>. So I think optional string is
correct here.
Commit: d7daf1d24be8231f7f422ef2bca1003d4b77ec11
https://github.com/llvm/llvm-project/commit/d7daf1d24be8231f7f422ef2bca1003d4b77ec11
Author: David Spickett <david.spickett at arm.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M llvm/tools/llvm-profgen/PerfReader.cpp
Log Message:
-----------
[llvm][llvm-profgen] Fix printing bogus trace info on 32-bit (#226965)
And as a result, fix
llvm/test/tools/llvm-profgen/AArch64/cs-bogus-trace.test when run on Arm
32-bit:
https://lab.llvm.org/buildbot/#/builders/122/builds/59
Fixes #225569 / 28fec94991905d8dd8a08658e9590e13b7fe1af5.
`x` is for an unsigned integer but the argument given for it is a
uint64_t. This worked on 64-bit (maybe it's passed in a register), but
not on 32-bit where we got strange values printed.
Use format_hex instead, so we don't have to choose a format code.
Commit: b20896c96deab703d7f0e99301b553a8ef4abad7
https://github.com/llvm/llvm-project/commit/b20896c96deab703d7f0e99301b553a8ef4abad7
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M llvm/lib/Target/DirectX/DXILDataScalarization.cpp
M llvm/lib/Target/DirectX/DXILFlattenArrays.cpp
M llvm/lib/Target/DirectX/DXILLegalizePass.cpp
M llvm/lib/Target/DirectX/DXILMemIntrinsics.cpp
M llvm/lib/Target/DirectX/DXILOpLowering.cpp
M llvm/test/CodeGen/DirectX/bugfix_150050_data_scalarize_const_gep.ll
M llvm/test/CodeGen/DirectX/flatten-array.ll
M llvm/test/CodeGen/DirectX/flatten-bug-117273.ll
M llvm/test/CodeGen/DirectX/legalize-i8.ll
M llvm/test/CodeGen/DirectX/llc-vector-load-scalarize.ll
M llvm/test/CodeGen/DirectX/scalar-store.ll
M llvm/test/CodeGen/DirectX/scalarize-static-array-of-float-vectors.ll
M llvm/test/tools/dxil-dis/constantexpr-gep.ll
Log Message:
-----------
[DirectX] Don't use IRBuilder to create GEPs (#227000)
This switches the DirectX backend to directly call
`GetElementPtrInst::Create()` instead of creating GEPs via IRBuilder.
IRBuilder will soon start canonicalizing GEPs to ptradd representation
(with the first change being
https://github.com/llvm/llvm-project/pull/226425, affecting constant
expressions only), while DirectX needs GEPs to have specific form.
The change implemented here is a minimal one to unblock further work. In
the future, it will become impossible to construct such GEPs through any
API. The DirectX backend needs to switch to using an intrinsic to
represent any non-canonical GEPs it needs. This followup work is tracked
in https://github.com/llvm/llvm-project/issues/227005.
Commit: bb9dd27ae02c6b4fb49757085aa13af92cc1ccda
https://github.com/llvm/llvm-project/commit/bb9dd27ae02c6b4fb49757085aa13af92cc1ccda
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M clang/lib/AST/ByteCode/Context.cpp
M clang/lib/AST/ByteCode/Context.h
M clang/lib/AST/ByteCode/EvalEmitter.cpp
M clang/lib/AST/ByteCode/EvalEmitter.h
M clang/lib/AST/ByteCode/InterpState.cpp
M clang/lib/AST/ByteCode/InterpState.h
M clang/lib/AST/ExprConstant.cpp
Log Message:
-----------
[clang][bytecode] Use bytecode interpreter in toplevel `Expr::Evaluate*` functions (#226217)
To avoid all the state setup we otherwise do. This also lets us remove
the `EvalInfo::EnableNewConstInterp` flag, which was previously checked
on every `::EvaluateAsRValue` call.
Commit: c68a4ca2a9202d073b569cbfbfb269f21abf7aec
https://github.com/llvm/llvm-project/commit/c68a4ca2a9202d073b569cbfbfb269f21abf7aec
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M mlir/lib/Target/LLVMIR/Dialect/LLVMIR/LLVMToLLVMIRTranslation.cpp
M mlir/test/Target/LLVMIR/llvmir-invalid.mlir
Log Message:
-----------
[LLVMIR] Directly lower global initializer GEP to constant expression (#226904)
MLIR lowers global initializers in a very unusual way, by using an
IRBuilder without insertion point, and relying on the fact that for a
well-formed initializer, all the instructions will be converted to
constant expressions and no actual instructions that require insertion
will be produced.
This causes issues for https://github.com/llvm/llvm-project/pull/226425,
which requires an insertion point for CreateGEP to determine the data
layout.
To avoid this, make convertGEPOp() directly produce a constant
expression GEP if there is no insertion point, reusing the existing code
path for inrange GEPs.
Commit: 090b123694953beeb55d003e45c24372858b29b8
https://github.com/llvm/llvm-project/commit/090b123694953beeb55d003e45c24372858b29b8
Author: David Spickett <david.spickett at arm.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M lldb/test/API/functionalities/scripted_frame_provider/pass_through_prefix/TestFrameProviderPassThroughPrefix.py
M lldb/test/API/functionalities/scripted_frame_provider/pass_through_prefix/frame_provider.py
Log Message:
-----------
[lldb][test] Handle None function name in frame provider tests (#226936)
Fixes #191859.
On Arm one of the functions has no name, which is a valid state.
```
Num frames: 7
0 frame #0: 0x092a151c a.out`baz at main.c:5:3 --name: baz
1 frame #1: 0x092a1540 a.out`bar at main.c:10:10 --name: bar
2 frame #2: 0x092a1560 a.out`foo at main.c:15:10 --name: foo
3 frame #3: 0x092a158c a.out`main at main.c:20:10 --name: main
4 frame #4: 0xf7ab939a libc.so.6` --name: None
5 frame #5: 0xf7ab943e libc.so.6`__libc_start_main + 94 --name: __libc_start_main
6 frame #6: 0x092a1434 a.out`_start + 40 --name: _start
```
The prefix provider needs to handle that possibility.
Though the Python type annotations on ScriptedFrame say that the name
methods return string, in reality they can return None, which the C++
sides expect. I will fix that in another PR.
Commit: e0bd48983e9d1d0de471a7689573622464c0b332
https://github.com/llvm/llvm-project/commit/e0bd48983e9d1d0de471a7689573622464c0b332
Author: Fangrui Song <i at maskray.me>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M clang/docs/LibASTImporter.md
M clang/docs/UsersManual.md
Log Message:
-----------
[docs] Pass -c when generating a PCH file (#226850)
Without options like -fsyntax-only/-E/-S/-c, the driver runs in link
mode, and a header-only command line produces a PCH only incidentally: a
linker option such as -lm or -Wl,..., including one from a config file,
adds a link job. Use -c in the PCH examples.
Also fix two broken examples: -ignore-pch is a driver option (cc1
rejects -Xclang -ignore-pch), and the relocatable PCH example is
missing -o. In LibASTImporter.md, generate the C++ AST files with
-emit-ast instead of treating .cpp files as headers.
LLM-aided
Commit: 58b102609a9d08fbadb9c3fa1dd88bba2cf7f711
https://github.com/llvm/llvm-project/commit/58b102609a9d08fbadb9c3fa1dd88bba2cf7f711
Author: Pawan Nirpal <pnirpal at qti.qualcomm.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M llvm/lib/Analysis/ScalarEvolution.cpp
A llvm/test/Analysis/ScalarEvolution/trip-count-variable-stride-predicate.ll
A llvm/test/Transforms/LoopVectorize/scev-variable-stride-predicate.ll
Log Message:
-----------
[SCEV] - Add positive-stride predicate for backedge-taken count. (#222261)
When `howManyLessThans` encounters a loop with an unknown stride that
cannot be proven finite (no `mustprogress` or side-effect-free
guarantee), SCEV currently returns `CouldNotCompute` for the
backedge-taken count. This blocks downstream consumers like the loop
vectorizer from optimizing such loops.
This patch relaxes the requirement by allowing a predicated
backedge-taken count when `AllowPredicates` is true. Instead of
requiring `loopIsFiniteByAssumption(L)` unconditionally, we add a
`Compare predicate: stride sgt 0` when finiteness cannot be proven.
A positive stride guarantees forward progress, making the BTC formula
correct. The predicate is emitted as a runtime check by consumers
(e.g., the loop vectorizer generates a guard branch before the vector
loop).
This is the SCEV-level fix for a class of variable-increment loops
common in Fortran-style benchmarks, e.g.:
void f(int n, int *a, int *b, int *c, int inc) {
int i = 0;
L10: if (i >= n) goto L20;
a[i] = a[i] + b[i] * c[i];
i = i + inc; // inc unknown at compile time
goto L10;
L20: ;
}
Addressing : https://github.com/llvm/llvm-project/issues/221915
---------
Co-authored-by: Florian Hahn <flo at fhahn.com>
Commit: ab0582707ef7ea0c4b03dff58ae9c32a9bdfec5c
https://github.com/llvm/llvm-project/commit/ab0582707ef7ea0c4b03dff58ae9c32a9bdfec5c
Author: Ties Stuij <ties.stuij at arm.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M compiler-rt/test/builtins/Unit/arm/aeabi_cmpflags_interwork_test.c
Log Message:
-----------
[compiler-rt][ARM] Make interworking test compatible with BTI (#226154)
In the aeabi_cmpflags_interwork_test.c test wrappers, we should return
through lr instead of r3 so that runs with BTI enabled don't fail. As
returns through lr don't require a landing pad, and returns through r3
do.
Commit: a3a37848d8cac394d067a6c9c5d545753556e4e7
https://github.com/llvm/llvm-project/commit/a3a37848d8cac394d067a6c9c5d545753556e4e7
Author: Henrich Lauko <xlauko at mail.muni.cz>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M mlir/include/mlir/IR/Diagnostics.h
M mlir/lib/IR/Diagnostics.cpp
M mlir/lib/Tools/mlir-opt/MlirOptMain.cpp
A mlir/test/Pass/remark-final-verify-diagnostics.mlir
M mlir/unittests/IR/Diagnostic.cpp
Log Message:
-----------
[mlir] Own the registrations of SourceMgrDiagnosticVerifierHandler (#226258)
`SourceMgrDiagnosticVerifierHandler::registerInContext` registered a
callback capturing `this` and dropped the handler id, so nothing could
erase it. The constructor did the same in its own context. After the
verifier was destroyed, the next diagnostic called into a dead object.
mlir-opt's per-buffer contexts die first, which hid the bug.
Make both registrations owned:
- The constructor installs its callback through `setHandler`, replacing
the base class's printing handler. That handler was unreachable anyway:
the verifier consumes every diagnostic and reports unexpected ones
itself. The base destructor now erases it.
- `registerInContext` returns a scoped registration. Callers destroy it
before the verifier and the context.
Erasing from every registered context in the destructor would not work:
mlir-opt's per-buffer contexts are already gone by then.
mlir-opt's `performActions` finalized the remark policy only after
textual output; on a failing pipeline the remarks deferred by
`--remark-policy=final` were emitted from `~MLIRContext`, after the
handlers were gone. It now finalizes on every exit, so those remarks
reach the verifier, or the printing handler in the non-verify path where
they were dropped before. A lit test pins this.
Assisted-by: Claude Code (Claude Fable 5.1)
Commit: f72d03de7c159efd3c4a4501323d19c86c17d7a8
https://github.com/llvm/llvm-project/commit/f72d03de7c159efd3c4a4501323d19c86c17d7a8
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
M llvm/test/CodeGen/SPIRV/legalization/signed-narrow-int.ll
Log Message:
-----------
[SPIR-V] Sign extend narrow ints feeding sitofp (#222969)
Commit: 197c16add5b16f4bd68c4f4bae115723e74330e2
https://github.com/llvm/llvm-project/commit/197c16add5b16f4bd68c4f4bae115723e74330e2
Author: Luke Lau <luke at igalia.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M .github/workflows/test-suite.yml
Log Message:
-----------
[GitHub] Add ffmpeg to test-suite.yml workflow (#227219)
This provides additional coverage for vector related codegen
Commit: 5e1ed67dbadba1b2bc254411cf78e61db51687d1
https://github.com/llvm/llvm-project/commit/5e1ed67dbadba1b2bc254411cf78e61db51687d1
Author: Momchil Velikov <momchil.velikov at arm.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M llvm/include/llvm/Transforms/Scalar/GVN.h
A llvm/include/llvm/Transforms/Scalar/GVNHoist.h
A llvm/include/llvm/Transforms/Scalar/GVNSink.h
A llvm/include/llvm/Transforms/Scalar/GVNValueTable.h
M llvm/lib/Passes/PassBuilder.cpp
M llvm/lib/Passes/PassBuilderPipelines.cpp
M llvm/lib/Transforms/Scalar/GVN.cpp
M llvm/lib/Transforms/Scalar/GVNHoist.cpp
M llvm/lib/Transforms/Scalar/GVNSink.cpp
Log Message:
-----------
[GVN] Move `ValueTable` out of `GVN.h` (NFC) (#226233)
* Rename `GVNPass::ValueTable` to `GVNValueTable`, and move it out to
the `llvm` namespace and to its own file `GVNValueTable.h`.
* Move `GVNPass::Expression` into `llvm::GVNValueTable`.
* Move `GVNHoistPass` and `GVNSinkPass` to their own headers.
With these changes `GVHoist.cpp` and `GVNSink.cpp` no longer need to
include `GVN.h` or peek into `GVNPass` internals.
Commit: 6286f77214be257eed1cff70d3e2e16f024e3dfb
https://github.com/llvm/llvm-project/commit/6286f77214be257eed1cff70d3e2e16f024e3dfb
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M llvm/include/llvm/Target/CGPassBuilderOption.h
M llvm/lib/CodeGen/TargetPassConfig.cpp
M llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
M llvm/lib/Passes/CodeGenPassBuilder.cpp
M llvm/test/CodeGen/AArch64/O3-pipeline.ll
M llvm/test/CodeGen/AArch64/coalescer-empty-subrange-early-lis.ll
M llvm/test/CodeGen/AArch64/itofp-bf16.ll
M llvm/test/CodeGen/AArch64/pr161420.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-trunc.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/twoaddr-extract-dyn-v7f64.mir
M llvm/test/CodeGen/AMDGPU/a-v-flat-atomic-cmpxchg.ll
M llvm/test/CodeGen/AMDGPU/acc-ldst.ll
M llvm/test/CodeGen/AMDGPU/add_i128.ll
M llvm/test/CodeGen/AMDGPU/add_i64.ll
M llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.160bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.224bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.288bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.32bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.352bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.384bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.448bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.48bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.576bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.640bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.64bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.704bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.768bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-mul24-knownbits.ll
M llvm/test/CodeGen/AMDGPU/and.ll
M llvm/test/CodeGen/AMDGPU/any_extend_vector_inreg.ll
M llvm/test/CodeGen/AMDGPU/anyext.ll
M llvm/test/CodeGen/AMDGPU/asyncmark-gfx12plus.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomicrmw_usub_sat.ll
M llvm/test/CodeGen/AMDGPU/atomics-system-scope.ll
M llvm/test/CodeGen/AMDGPU/av-split-dead-valno-crash.ll
M llvm/test/CodeGen/AMDGPU/bf16.ll
M llvm/test/CodeGen/AMDGPU/bitinsert-bitextract-fp.ll
M llvm/test/CodeGen/AMDGPU/bitinsert-bitextract.ll
M llvm/test/CodeGen/AMDGPU/bitreverse.ll
M llvm/test/CodeGen/AMDGPU/branch-folding-implicit-def-subreg.ll
M llvm/test/CodeGen/AMDGPU/bswap.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointers-memcpy.ll
M llvm/test/CodeGen/AMDGPU/bypass-div.ll
M llvm/test/CodeGen/AMDGPU/clmul.ll
M llvm/test/CodeGen/AMDGPU/consecutive-loads-in-branch.ll
M llvm/test/CodeGen/AMDGPU/copy-illegal-type.ll
M llvm/test/CodeGen/AMDGPU/ctlz.ll
M llvm/test/CodeGen/AMDGPU/ctlz_zero_poison.ll
M llvm/test/CodeGen/AMDGPU/ctpop.ll
M llvm/test/CodeGen/AMDGPU/ctpop16.ll
M llvm/test/CodeGen/AMDGPU/ctpop64.ll
M llvm/test/CodeGen/AMDGPU/cttz.ll
M llvm/test/CodeGen/AMDGPU/cttz_zero_poison.ll
M llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
M llvm/test/CodeGen/AMDGPU/dead-lane.mir
M llvm/test/CodeGen/AMDGPU/div_v2i128.ll
M llvm/test/CodeGen/AMDGPU/ds_gws_align.ll
M llvm/test/CodeGen/AMDGPU/dynamic-vgpr-reserve-stack-for-cwsr.ll
M llvm/test/CodeGen/AMDGPU/fadd.f16.ll
M llvm/test/CodeGen/AMDGPU/fceil64.ll
M llvm/test/CodeGen/AMDGPU/fcmp.f16.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64_noprivate.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system.ll
M llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp-fp8-hw.ll
M llvm/test/CodeGen/AMDGPU/fmax_legacy.f64.ll
M llvm/test/CodeGen/AMDGPU/fmin_legacy.f64.ll
M llvm/test/CodeGen/AMDGPU/fmul.f16.ll
M llvm/test/CodeGen/AMDGPU/fnearbyint.ll
M llvm/test/CodeGen/AMDGPU/fptoi.i128.ll
M llvm/test/CodeGen/AMDGPU/fptrunc.ll
M llvm/test/CodeGen/AMDGPU/freeze.ll
M llvm/test/CodeGen/AMDGPU/frem.ll
M llvm/test/CodeGen/AMDGPU/fshl.ll
M llvm/test/CodeGen/AMDGPU/fsub.f16.ll
M llvm/test/CodeGen/AMDGPU/gfx-callable-return-types.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/global-load-xcnt.ll
M llvm/test/CodeGen/AMDGPU/half.ll
M llvm/test/CodeGen/AMDGPU/hsa-metadata-kernel-code-props.ll
M llvm/test/CodeGen/AMDGPU/identical-subrange-spill-infloop.ll
M llvm/test/CodeGen/AMDGPU/idot2.ll
M llvm/test/CodeGen/AMDGPU/idot4s.ll
M llvm/test/CodeGen/AMDGPU/idot4u.ll
M llvm/test/CodeGen/AMDGPU/idot8u.ll
M llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll
M llvm/test/CodeGen/AMDGPU/indirect-call.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_elt.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll
M llvm/test/CodeGen/AMDGPU/lds-misaligned-bug.ll
M llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll
M llvm/test/CodeGen/AMDGPU/llc-pipeline.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dual_intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.atomic.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.dim.gfx90a.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.dim.gfx90a.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.scale.f32.32x32x64.f8f6f4.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fadd.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fsub.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.set.inactive.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.smfmac.gfx950.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp10.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp10.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp2.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp2.ll
M llvm/test/CodeGen/AMDGPU/llvm.fma.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.log2.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.maxnum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.minimum.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.minnum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.round.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.round.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i16.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i32.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i64.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i8.ll
M llvm/test/CodeGen/AMDGPU/load-global-f32.ll
M llvm/test/CodeGen/AMDGPU/load-global-i16.ll
M llvm/test/CodeGen/AMDGPU/load-global-i32.ll
M llvm/test/CodeGen/AMDGPU/load-global-i8.ll
M llvm/test/CodeGen/AMDGPU/load-local-i16.ll
M llvm/test/CodeGen/AMDGPU/lower-control-flow-live-variables-update.mir
M llvm/test/CodeGen/AMDGPU/machine-sink-temporal-divergence-swdev407790.ll
M llvm/test/CodeGen/AMDGPU/mad-combine.ll
M llvm/test/CodeGen/AMDGPU/mad_uint24.ll
M llvm/test/CodeGen/AMDGPU/max.ll
M llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll
M llvm/test/CodeGen/AMDGPU/merge-stores.ll
M llvm/test/CodeGen/AMDGPU/mfma-cd-select.ll
M llvm/test/CodeGen/AMDGPU/mfma-no-register-aliasing.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-atomicrmw-system.ll
M llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands-non-ptr-intrinsics.ll
M llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands.ll
M llvm/test/CodeGen/AMDGPU/mul.ll
M llvm/test/CodeGen/AMDGPU/mul_uint24-amdgcn.ll
M llvm/test/CodeGen/AMDGPU/no-remat-indirect-mov.mir
M llvm/test/CodeGen/AMDGPU/operand-folding.ll
M llvm/test/CodeGen/AMDGPU/or.ll
M llvm/test/CodeGen/AMDGPU/packed-fp32.ll
M llvm/test/CodeGen/AMDGPU/packed-fp64.ll
M llvm/test/CodeGen/AMDGPU/packed-u64.ll
M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll
M llvm/test/CodeGen/AMDGPU/rewrite-mfma-single-exit-copy.ll
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-reserved-wwm-vgpr.ll
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-spill-joint-dom.ll
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr.ll
M llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll
M llvm/test/CodeGen/AMDGPU/schedule-relaxed-occupancy.ll
M llvm/test/CodeGen/AMDGPU/scratch-simple.ll
M llvm/test/CodeGen/AMDGPU/sdiv.ll
M llvm/test/CodeGen/AMDGPU/select.f16.ll
M llvm/test/CodeGen/AMDGPU/shift-and-i64-ubfe.ll
M llvm/test/CodeGen/AMDGPU/shl.ll
M llvm/test/CodeGen/AMDGPU/shl.v2i64.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll
M llvm/test/CodeGen/AMDGPU/sint_to_fp.i64.ll
M llvm/test/CodeGen/AMDGPU/sminmax.v2i16.ll
M llvm/test/CodeGen/AMDGPU/spill-scavenge-offset.ll
M llvm/test/CodeGen/AMDGPU/spill-vgpr.ll
M llvm/test/CodeGen/AMDGPU/splitkit-getsubrangeformask-phi-extend.ll
M llvm/test/CodeGen/AMDGPU/sra.ll
M llvm/test/CodeGen/AMDGPU/srem.ll
M llvm/test/CodeGen/AMDGPU/srl.ll
M llvm/test/CodeGen/AMDGPU/sub.ll
M llvm/test/CodeGen/AMDGPU/twoaddr-constrain.ll
M llvm/test/CodeGen/AMDGPU/udiv.ll
M llvm/test/CodeGen/AMDGPU/uint_to_fp.i64.ll
M llvm/test/CodeGen/AMDGPU/undef-handling-crash-in-ra.ll
M llvm/test/CodeGen/AMDGPU/undefined-subreg-liverange.ll
M llvm/test/CodeGen/AMDGPU/unspill-vgpr-after-rewrite-vgpr-mfma.ll
M llvm/test/CodeGen/AMDGPU/urem64.ll
M llvm/test/CodeGen/AMDGPU/v_madak_f16.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fmaximum.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fminimum.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-smax.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-smin.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-umax.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-umin.ll
M llvm/test/CodeGen/AMDGPU/vgpr-mark-last-scratch-load.ll
M llvm/test/CodeGen/AMDGPU/vni8-across-blocks.ll
M llvm/test/CodeGen/AMDGPU/vselect.ll
M llvm/test/CodeGen/AMDGPU/waitcnt-loop-ds-prefetch-pattern.ll
M llvm/test/CodeGen/AMDGPU/wave32.ll
M llvm/test/CodeGen/AMDGPU/widen-vselect-and-mask.ll
M llvm/test/CodeGen/AMDGPU/wqm.ll
M llvm/test/CodeGen/AMDGPU/xor.ll
M llvm/test/CodeGen/ARM/O3-pipeline.ll
M llvm/test/CodeGen/ARM/fp-intrinsics-vector.ll
M llvm/test/CodeGen/ARM/inlineasm-operand-implicit-cast.ll
M llvm/test/CodeGen/ARM/llvm.modf.ll
M llvm/test/CodeGen/ARM/llvm.sincos.ll
M llvm/test/CodeGen/ARM/signext-inreg.ll
M llvm/test/CodeGen/ARM/vldlane.ll
M llvm/test/CodeGen/Hexagon/addh.ll
M llvm/test/CodeGen/Hexagon/cttz-elts-widen.ll
M llvm/test/CodeGen/Hexagon/isel-extload-i1.ll
M llvm/test/CodeGen/Hexagon/mulhs.ll
M llvm/test/CodeGen/Hexagon/swp-vect-dotprod.ll
M llvm/test/CodeGen/LoongArch/opt-pipeline.ll
M llvm/test/CodeGen/M68k/pipeline.ll
M llvm/test/CodeGen/PowerPC/O3-pipeline.ll
M llvm/test/CodeGen/PowerPC/dmr-copy.ll
M llvm/test/CodeGen/PowerPC/dmr-enable.ll
M llvm/test/CodeGen/PowerPC/no-rlwimi-trivial-commute.mir
M llvm/test/CodeGen/RISCV/O3-newpm-pipeline.ll
M llvm/test/CodeGen/RISCV/O3-pipeline.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-subvector.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll
M llvm/test/CodeGen/RISCV/rvv/fmaximum-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fminimum-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfmsub-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vwadd.w.ll
M llvm/test/CodeGen/SystemZ/atomicrmw-ops-i128.ll
M llvm/test/CodeGen/SystemZ/atomicrmw-xchg-07.ll
M llvm/test/CodeGen/SystemZ/rot-02.ll
M llvm/test/CodeGen/SystemZ/subregliveness-01.ll
M llvm/test/CodeGen/Thumb/emergency-spill-slot.ll
M llvm/test/CodeGen/Thumb2/mve-clmul.ll
M llvm/test/CodeGen/Thumb2/mve-complex-deinterleaving-f64-add.ll
M llvm/test/CodeGen/Thumb2/mve-complex-deinterleaving-f64-mul.ll
M llvm/test/CodeGen/Thumb2/mve-complex-deinterleaving-mixed-cases.ll
M llvm/test/CodeGen/Thumb2/mve-complex-deinterleaving-uniform-cases.ll
M llvm/test/CodeGen/Thumb2/mve-ctlz.ll
M llvm/test/CodeGen/Thumb2/mve-fmath.ll
M llvm/test/CodeGen/Thumb2/mve-insertshuffleload.ll
M llvm/test/CodeGen/Thumb2/mve-laneinterleaving-cost.ll
M llvm/test/CodeGen/Thumb2/mve-laneinterleaving.ll
M llvm/test/CodeGen/Thumb2/mve-multivec-spill.ll
M llvm/test/CodeGen/Thumb2/mve-pred-shuffle.ll
M llvm/test/CodeGen/Thumb2/mve-saturating-arith.ll
M llvm/test/CodeGen/Thumb2/mve-sext-masked-load.ll
M llvm/test/CodeGen/Thumb2/mve-shuffle-fp16.ll
M llvm/test/CodeGen/Thumb2/mve-shuffle.ll
M llvm/test/CodeGen/Thumb2/mve-shuffleext.ll
M llvm/test/CodeGen/Thumb2/mve-shufflemov.ll
M llvm/test/CodeGen/Thumb2/mve-vabdus.ll
M llvm/test/CodeGen/Thumb2/mve-vcvt16.ll
M llvm/test/CodeGen/Thumb2/mve-vld2.ll
M llvm/test/CodeGen/Thumb2/mve-vld3.ll
M llvm/test/CodeGen/Thumb2/mve-vld4-post.ll
M llvm/test/CodeGen/Thumb2/mve-vld4.ll
M llvm/test/CodeGen/Thumb2/mve-vldst4.ll
M llvm/test/CodeGen/Thumb2/mve-vst2.ll
M llvm/test/CodeGen/Thumb2/mve-vst3.ll
M llvm/test/CodeGen/Thumb2/mve-vst4-post.ll
M llvm/test/CodeGen/Thumb2/mve-vst4.ll
M llvm/test/CodeGen/Thumb2/mve-zext-masked-load.ll
M llvm/test/CodeGen/X86/active_lane_mask.ll
M llvm/test/CodeGen/X86/addcarry.ll
M llvm/test/CodeGen/X86/apx/mul-i1024.ll
M llvm/test/CodeGen/X86/apx/pr191368.ll
M llvm/test/CodeGen/X86/apx/push2-pop2.ll
M llvm/test/CodeGen/X86/bit-manip-i512.ll
M llvm/test/CodeGen/X86/bitselect.ll
M llvm/test/CodeGen/X86/clmul-vector.ll
M llvm/test/CodeGen/X86/combine-bitselect.ll
M llvm/test/CodeGen/X86/combine-or.ll
M llvm/test/CodeGen/X86/combine-rotates.ll
M llvm/test/CodeGen/X86/div-rem-pair-recomposition-unsigned.ll
M llvm/test/CodeGen/X86/fpclamptosat_vec.ll
M llvm/test/CodeGen/X86/ftrunc.ll
M llvm/test/CodeGen/X86/funnel-shift-i512.ll
M llvm/test/CodeGen/X86/half.ll
M llvm/test/CodeGen/X86/i128-udiv.ll
M llvm/test/CodeGen/X86/icmp-abs-C.ll
M llvm/test/CodeGen/X86/inline-asm-A-constraint.ll
M llvm/test/CodeGen/X86/llc-pipeline-npm.ll
M llvm/test/CodeGen/X86/machine-combiner-int-vec.ll
M llvm/test/CodeGen/X86/machine-cse.ll
M llvm/test/CodeGen/X86/masked-urem.ll
M llvm/test/CodeGen/X86/midpoint-int-vec-128.ll
M llvm/test/CodeGen/X86/midpoint-int.ll
M llvm/test/CodeGen/X86/mul-i1024.ll
M llvm/test/CodeGen/X86/mul-i256.ll
M llvm/test/CodeGen/X86/mul-i512.ll
M llvm/test/CodeGen/X86/mul-shift-reassoc.ll
M llvm/test/CodeGen/X86/mul128.ll
M llvm/test/CodeGen/X86/neg-abs.ll
M llvm/test/CodeGen/X86/oddshuffles.ll
M llvm/test/CodeGen/X86/opt-pipeline.ll
M llvm/test/CodeGen/X86/pr46877.ll
M llvm/test/CodeGen/X86/scalar-minmax-simd.ll
M llvm/test/CodeGen/X86/shift-amount-mod.ll
M llvm/test/CodeGen/X86/shift-and.ll
M llvm/test/CodeGen/X86/statepoint-cmp-sunk-past-statepoint.ll
M llvm/test/CodeGen/X86/statepoint-relocate-eh.ll
M llvm/test/CodeGen/X86/statepoint-vreg-unlimited-tied-opnds.ll
M llvm/test/CodeGen/X86/ternlog.ll
M llvm/test/CodeGen/X86/twoaddr-lea-eflags-liveintervals.ll
M llvm/test/CodeGen/X86/ucmp.ll
M llvm/test/CodeGen/X86/unfold-masked-merge-vector-variablemask.ll
M llvm/test/CodeGen/X86/vec_umulo.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-3.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-3.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-3.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-8.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-3.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-8.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-3.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-8.ll
M llvm/test/CodeGen/X86/vector-lzcnt-128.ll
M llvm/test/CodeGen/X86/vector-partial-reduce-sumla.ll
M llvm/test/CodeGen/X86/vector-partial-reduce-umla.ll
M llvm/test/CodeGen/X86/vector-reduce-ctpop.ll
M llvm/test/CodeGen/X86/vector-reduce-smax.ll
M llvm/test/CodeGen/X86/vector-reduce-smin.ll
M llvm/test/CodeGen/X86/vector-reduce-umax.ll
M llvm/test/CodeGen/X86/vector-reduce-umin.ll
M llvm/test/CodeGen/X86/vector-trunc-packus.ll
M llvm/test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll
M llvm/test/CodeGen/X86/widen_arith-2.ll
M llvm/test/CodeGen/X86/widen_bitcnt.ll
M llvm/test/CodeGen/X86/zext-trunc.ll
M llvm/test/DebugInfo/MIR/X86/mlicm-hoist-post-regalloc.mir
M llvm/test/Transforms/SampleProfile/pseudo-probe-twoaddr.ll
Log Message:
-----------
CodeGen: Compute LiveIntervals before TwoAddressInstructions (#225174)
TwoAddressInstructions is the traditional primary use of LiveVariables, but it has
gained a LiveIntervals path. By moving LiveIntervals earlier, the default flips to rely
on it instead of LiveVariables. The overall test churn is mostly neutral, with more net
wins than losses.
This should move before phi elimination. This is a staging move to incrementally
remove the LiveVariables support from TwoAddressInstructions, and because the
move to running LiveIntervals on SSA is a bigger leap.
This obsoletes -early-live-intervals (though, maybe it could be repurposed for
move before SSA).
Co-authored-by: Claude (Claude-Opus-4.8)
Commit: f0f0fe2d928a4c46dbd60b6d6bf6cf6d9f8b2993
https://github.com/llvm/llvm-project/commit/f0f0fe2d928a4c46dbd60b6d6bf6cf6d9f8b2993
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
R libcxx/utils/ci/images/libcxx_next_runners.txt
R libcxx/utils/ci/images/libcxx_release_runners.txt
R libcxx/utils/ci/images/libcxx_runners.txt
Log Message:
-----------
[libcxx] Delete runner set image versions (#227141)
These are no longer needed now that we have removed the old runner sets.
Commit: cdebdbdba13e79bdb09d328e05b417d2b7614a82
https://github.com/llvm/llvm-project/commit/cdebdbdba13e79bdb09d328e05b417d2b7614a82
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
M llvm/lib/Transforms/Vectorize/VPlanUtils.h
M llvm/test/Transforms/LoopVectorize/VPlan/execution-frequencies-match-bfi.ll
M llvm/test/Transforms/LoopVectorize/VPlan/record-execution-frequencies.ll
M llvm/test/Transforms/LoopVectorize/VPlan/vplan-based-stride-mv.ll
M llvm/test/Transforms/LoopVectorize/VPlan/vplan-printing-branch-weights.ll
Log Message:
-----------
[VPlan] Use BlockFrequencyInfo's full mass for execution frequencies. (#227006)
Use BlockFrequencyInfo's full mass instead of custom 2^63 for "always
execute".
This updates VPlan's block frequencies to match BFI.
PR: https://github.com/llvm/llvm-project/pull/227006
Commit: f69661de1c6fd034afabc2acf79a888cf7b58c5c
https://github.com/llvm/llvm-project/commit/f69661de1c6fd034afabc2acf79a888cf7b58c5c
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M llvm/lib/Analysis/BlockFrequencyInfoImpl.cpp
A llvm/test/Analysis/BlockFrequencyInfo/many-successors-order.ll
Log Message:
-----------
[BFI] Use MapVector in combineWeightsByHashing. (#227027)
combineWeightsByHashing iterated over a DenseMap, which depends on the
hash. Use MapVector to get consistent results, independent of index
type/values.
This is mainly to ensure consistency between users that use different
index numbers, i.e. used for IR BFI and VPlan's use.
PR: https://github.com/llvm/llvm-project/pull/227027
Commit: 724557a9bd1389446ba52d270ad31d78a6071497
https://github.com/llvm/llvm-project/commit/724557a9bd1389446ba52d270ad31d78a6071497
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M llvm/test/CodeGen/X86/two-address-subreg-to-reg-kill.mir
Log Message:
-----------
X86: Fix missing ... separator between functions in mir test (#227228)
The update_mir_test_checks output is incomplete so the later functions
here were really manually checked.
Commit: fa3d17075284bf746f4030ad3371fe5c05b06653
https://github.com/llvm/llvm-project/commit/fa3d17075284bf746f4030ad3371fe5c05b06653
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M llvm/lib/Transforms/IPO/FunctionAttrs.cpp
M llvm/test/Transforms/FunctionAttrs/noalias.ll
Log Message:
-----------
[FunctionAttrs] Infer noalias through a null check. (#226956)
Only comparing against null does not captures provenance and should not
impact whether a pointer is noalias or not.
This enables noalias inference in a number of cases for malloc-like
functions:
https://github.com/dtcxzyw/llvm-opt-benchmark-nightly/pull/1459.
PR: https://github.com/llvm/llvm-project/pull/226956
Commit: 6ccc4917217c650428fd36360690dad4a3f69d20
https://github.com/llvm/llvm-project/commit/6ccc4917217c650428fd36360690dad4a3f69d20
Author: Utkarsh Saxena <usx at google.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M clang/lib/Analysis/LifetimeSafety/FactsGenerator.cpp
M clang/test/Sema/LifetimeSafety/safety.cpp
Log Message:
-----------
[LifetimeSafety] Fix off-by-one crash in `lifetime_capture_by` argument indexing (#227231)
Fixes an off-by-one crash in the lifetime_capture_by attribute handling.
The CapturingArgIdx is already an index into the full Args array, but
the code was incorrectly creating a CallArgs array (dropping the first
argument for instance methods) and then indexing into it with
CapturingArgIdx, causing incorrect argument access and potential
out-of-bounds crashes.
Currently crashes at head: https://godbolt.org/z/7rYczK1z6
Commit: 74c86a79968b3f23eb3b292d318429364709f6b2
https://github.com/llvm/llvm-project/commit/74c86a79968b3f23eb3b292d318429364709f6b2
Author: Jay Foad <jay.foad at amd.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPULaneMaskUtils.h
M llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.h
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
M llvm/test/CodeGen/AMDGPU/anyext.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
M llvm/test/CodeGen/AMDGPU/bf16-conversions.ll
M llvm/test/CodeGen/AMDGPU/copy-to-reg-scc-clobber.ll
M llvm/test/CodeGen/AMDGPU/extract-subvector-16bit.ll
M llvm/test/CodeGen/AMDGPU/fcmp.f16.ll
M llvm/test/CodeGen/AMDGPU/fcopysign.bf16.ll
A llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-scc-cmp-wave32.mir
A llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-scc-cmp.mir
M llvm/test/CodeGen/AMDGPU/fneg-combines.new.ll
M llvm/test/CodeGen/AMDGPU/fneg-modifier-casting.ll
M llvm/test/CodeGen/AMDGPU/fp-classify.ll
M llvm/test/CodeGen/AMDGPU/fp_to_sint.ll
M llvm/test/CodeGen/AMDGPU/fp_to_uint.ll
M llvm/test/CodeGen/AMDGPU/fpow.ll
M llvm/test/CodeGen/AMDGPU/fptosi-sat-scalar.ll
M llvm/test/CodeGen/AMDGPU/fptosi.f16.ll
M llvm/test/CodeGen/AMDGPU/fptoui.f16.ll
M llvm/test/CodeGen/AMDGPU/frem.ll
M llvm/test/CodeGen/AMDGPU/fsqrt.f64.ll
M llvm/test/CodeGen/AMDGPU/literal64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.class.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp2.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.ll
M llvm/test/CodeGen/AMDGPU/llvm.log.ll
M llvm/test/CodeGen/AMDGPU/llvm.log10.ll
M llvm/test/CodeGen/AMDGPU/llvm.log2.ll
M llvm/test/CodeGen/AMDGPU/max.ll
M llvm/test/CodeGen/AMDGPU/min.ll
M llvm/test/CodeGen/AMDGPU/mixed-vmem-types.ll
M llvm/test/CodeGen/AMDGPU/or.ll
M llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.ll
M llvm/test/CodeGen/AMDGPU/rsq.f64.ll
M llvm/test/CodeGen/AMDGPU/saddo.ll
M llvm/test/CodeGen/AMDGPU/scmp.ll
M llvm/test/CodeGen/AMDGPU/setcc-f64-hi32mask.ll
M llvm/test/CodeGen/AMDGPU/ssubo.ll
M llvm/test/CodeGen/AMDGPU/ucmp.ll
M llvm/test/CodeGen/AMDGPU/umin-sub-to-usubo-select-combine.ll
M llvm/test/CodeGen/AMDGPU/wave32.ll
Log Message:
-----------
[AMDGPU] Use S_CMP to lower a copy of a lane mask to SCC (#221445)
SIFixSGPRCopies lowers a copy of a lane mask to SCC as an AND with EXEC,
whose destination register is created by the pass and is always dead.
The AND with EXEC is only needed because SCC has to be "any active lane
is set". When the lane mask already has 0 in the bits of all inactive
lanes, that is just "the mask is non-zero", which S_CMP computes without
needing a destination register. In some cases the S_CMP can be optimized
away later by SIInstrInfo::optimizeCompareInstr.
Co-authored-by: Claude Opus 5 (1M context) <noreply at anthropic.com>
Commit: 7cf8ecb2ef8acc2bca15f2223a3635f5863a81a7
https://github.com/llvm/llvm-project/commit/7cf8ecb2ef8acc2bca15f2223a3635f5863a81a7
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M llvm/lib/Target/Mips/MipsFastISel.cpp
A llvm/test/CodeGen/Mips/Fast-ISel/mul-dead-hilo.ll
Log Message:
-----------
Mips: Mark MUL's existing HI0/LO0 defs dead in FastISel (#227230)
Commit: 5a245737377fec09c871c802cc730189a61df459
https://github.com/llvm/llvm-project/commit/5a245737377fec09c871c802cc730189a61df459
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M llvm/lib/Target/Mips/MipsCallLowering.cpp
M llvm/test/CodeGen/Mips/GlobalISel/irtranslator/aggregate_struct_return.ll
M llvm/test/CodeGen/Mips/GlobalISel/irtranslator/call.ll
M llvm/test/CodeGen/Mips/GlobalISel/irtranslator/extend_args.ll
M llvm/test/CodeGen/Mips/GlobalISel/irtranslator/float_args.ll
M llvm/test/CodeGen/Mips/GlobalISel/irtranslator/global_address.ll
M llvm/test/CodeGen/Mips/GlobalISel/irtranslator/global_address_pic.ll
M llvm/test/CodeGen/Mips/GlobalISel/irtranslator/sret_pointer.ll
M llvm/test/CodeGen/Mips/GlobalISel/irtranslator/stack_args.ll
M llvm/test/CodeGen/Mips/GlobalISel/irtranslator/var_arg.ll
M llvm/test/CodeGen/Mips/GlobalISel/legalizer/ceil_and_floor.mir
M llvm/test/CodeGen/Mips/GlobalISel/legalizer/dyn_stackalloc.mir
M llvm/test/CodeGen/Mips/GlobalISel/legalizer/fptosi_and_fptoui.mir
M llvm/test/CodeGen/Mips/GlobalISel/legalizer/rem_and_div.mir
M llvm/test/CodeGen/Mips/GlobalISel/legalizer/sitofp_and_uitofp.mir
Log Message:
-----------
Mips/GlobalISel: Mark call's implicit RA def dead (#227233)
Co-authored-by: Claude Opus 5 <noreply at anthropic.com>
Commit: a4b0944bde4640586dd902d3ad401a6270c8a1fe
https://github.com/llvm/llvm-project/commit/a4b0944bde4640586dd902d3ad401a6270c8a1fe
Author: Gaëtan Bossu <gaetan.bossu at arm.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.h
M llvm/test/CodeGen/AArch64/named-vector-shuffle-reverse-sve.ll
Log Message:
-----------
[AArch64] ISel support for nxv1i1 vector_reverse (#226939)
This ensures llvm.vector.reverse can be selected for nxv1i1 types. These intrinsics can be generated by LoopVectorizer for `VF = vscale x 1` and loops iterating in reverse order.
Commit: d5f6c302fff1aeed8fb6a247c21a694b156778bc
https://github.com/llvm/llvm-project/commit/d5f6c302fff1aeed8fb6a247c21a694b156778bc
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M libcxx/docs/Hardening.rst
M libcxx/include/__configuration/attributes.h
Log Message:
-----------
[libc++] Encode the standard version in the ABI tag (#218527)
This prevents ODR mismatch issues from biting us across standard
versions. The order of elements in the ABI tag is now: libc++ version,
hardening mode, assertion semantic, exceptions, standard version.
Fixes #218524
Commit: 5c170b01350198b7f1f830fb53253652015077b3
https://github.com/llvm/llvm-project/commit/5c170b01350198b7f1f830fb53253652015077b3
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M llvm/lib/Target/Mips/MipsOptimizePICCall.cpp
A llvm/test/CodeGen/Mips/optimize-pic-call-dead-gp.ll
Log Message:
-----------
Mips: Mark the $gp setup copy dead when erasing the call's $gp use (#227216)
MipsOptimizePICCall drops the implicit $gp operand from a call when the
lazy binding stub for the callee has already run. The copy that set $gp
up for that call then has no reader left, but nothing flagged it, so the
MIR carried a live def until a later liveness recomputation cleaned it
up.
The pass already walks each block in order, so track the reaching
definition of $gp as it goes and mark it dead when the use is erased.
Co-authored-by: Claude Opus 5 <noreply at anthropic.com>
Commit: e0c49c0739807c8c75d38148babfa338d1e07f6a
https://github.com/llvm/llvm-project/commit/e0c49c0739807c8c75d38148babfa338d1e07f6a
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
A llvm/test/CodeGen/AArch64/GlobalISel/select-tls-macho.ll
Log Message:
-----------
AArch64/GlobalISel: Mark the LR def of the Mach-O TLS call dead (#227234)
The ordinary call path already does this, and the SelectionDAG emitter
marks unused implicit physreg defs dead for free. Without it the dead
flag needs to be reinferred later.
Co-authored-by: Claude Opus 5 <noreply at anthropic.com>
Commit: 5aa04826046edad5122d959688c0b8e9950f261f
https://github.com/llvm/llvm-project/commit/5aa04826046edad5122d959688c0b8e9950f261f
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCTargetDesc.cpp
A llvm/test/CodeGen/LoongArch/null-streamer.ll
Log Message:
-----------
LoongArch: Register a null target streamer (#226497)
Emitting a TLS variable's debug location calls into the target streamer,
which was only registered for asm and object output. -filetype=null
therefore null dereferenced.
Co-authored-by: Claude Opus 5 <noreply at anthropic.com>
Commit: 80cd6102a79c02763034fbf1b6a1473930b1d4ab
https://github.com/llvm/llvm-project/commit/80cd6102a79c02763034fbf1b6a1473930b1d4ab
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M llvm/lib/Target/LoongArch/LoongArchAsmPrinter.cpp
M llvm/lib/Target/LoongArch/LoongArchAsmPrinter.h
A llvm/test/CodeGen/LoongArch/module-target-abi.ll
Log Message:
-----------
LoongArch: Respect the target-abi module flag in the ELF header (#226498)
The target streamer read the ABI from MCTargetOptions when constructed,
so the e_flags recorded the command line -target-abi and ignored the
module flag.
Co-authored-by: Claude Opus 5 <noreply at anthropic.com>
Commit: b7bd84ff2a30e08e7f1bd2b36db5f8ec9ba300ee
https://github.com/llvm/llvm-project/commit/b7bd84ff2a30e08e7f1bd2b36db5f8ec9ba300ee
Author: Luke Lau <luke at igalia.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/conditional-scalar-assignment-fold-tail.ll
M llvm/test/Transforms/LoopVectorize/AArch64/conditional-scalar-assignment.ll
M llvm/test/Transforms/LoopVectorize/AArch64/findlast-epilogue-loop.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-select-cmp.ll
M llvm/test/Transforms/LoopVectorize/RISCV/conditional-scalar-assignment-fold-tail.ll
M llvm/test/Transforms/LoopVectorize/RISCV/conditional-scalar-assignment.ll
M llvm/test/Transforms/LoopVectorize/RISCV/iv-select-cmp.ll
M llvm/test/Transforms/LoopVectorize/RISCV/select-cmp-reduction.ll
M llvm/test/Transforms/LoopVectorize/VPlan/conditional-scalar-assignment-vplan.ll
M llvm/test/Transforms/LoopVectorize/VPlan/interleave-conditional-scalar-assignment-vplan.ll
M llvm/test/Transforms/LoopVectorize/X86/conditional-scalar-assignment.ll
M llvm/test/Transforms/LoopVectorize/alias-mask.ll
M llvm/test/Transforms/LoopVectorize/conditional-scalar-assignment-interleave-only.ll
M llvm/test/Transforms/LoopVectorize/find-last-iv-sinkable-expr-tail-folding.ll
M llvm/test/Transforms/LoopVectorize/find-last-iv-sinkable-expr.ll
M llvm/test/Transforms/LoopVectorize/find-last-iv-sinkable-load.ll
M llvm/test/Transforms/LoopVectorize/find-last-ptr-induction.ll
M llvm/test/Transforms/LoopVectorize/find-last.ll
M llvm/test/Transforms/LoopVectorize/iv-select-cmp-fold-tail.ll
M llvm/test/Transforms/LoopVectorize/iv-select-cmp-non-const-iv-start.ll
M llvm/test/Transforms/LoopVectorize/iv-select-cmp-trunc.ll
M llvm/test/Transforms/LoopVectorize/iv-select-cmp.ll
M llvm/test/Transforms/LoopVectorize/select-cmp.ll
Log Message:
-----------
[VPlan] Fix find last reductions not using frozen condition in select (#223962)
A find last reduction is something like:
(select c[n], x[n], (select c[n-1], x[n-1], (select ...)))
So even if previous iterations had poison for c[x], the top-level select
blocks it.
MaskSelect uses the non-frozen Cond, and that in turn is fed into
VPInstruction::ExtractLastActive, which in turn gets expanded to
vector.reduce.umax, which returns poison if any of the lanes were
poison.
So in the case e.g. c[n] = 1, c[n-1] = poison and VF=2, the scalar loop
returns x[n] whilst vector loop returns poison.
We're also introducing multiple uses of Cond which isn't sound for
undef, so for these reasons we need to use the frozen Cond.
Commit: bd9d96ce12d083a8de6e06c5dffd1b79a5cbef47
https://github.com/llvm/llvm-project/commit/bd9d96ce12d083a8de6e06c5dffd1b79a5cbef47
Author: Dharuni R Acharya <125176188+DharuniRAcharya at users.noreply.github.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M clang/include/clang/Basic/BuiltinsNVPTX.td
M clang/lib/CodeGen/TargetBuiltins/NVPTX.cpp
M clang/test/CodeGen/builtins-nvptx.c
M llvm/include/llvm/IR/IntrinsicsNVVM.td
M llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
M llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
A llvm/test/CodeGen/NVPTX/convert-fp4-pzo.ll
M mlir/lib/Dialect/LLVMIR/IR/NVVMDialect.cpp
M mlir/test/Target/LLVMIR/nvvm/convert_fp4x2.mlir
Log Message:
-----------
[clang][NVPTX] Add support for pzo in f32/f16x2/bf16x2 to FP4 conversions (#225318)
This patch adds support for `pzo` variants and `rz` rounding mode to
existing `f32/f16x2/bf16x2` to `FP4` (`e2m1x2`) conversion intrinsics.
Also adds `clang builtins` for the new variants.
Tests have been verified through `ptxas-13.4`.
PTX ISA Reference:
https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-cvt
---------
Signed-off-by: DharuniRAcharya <dharunira at nvidia.com>
Commit: 5da194580292bc90f6577f3959dda3a9bb6d5366
https://github.com/llvm/llvm-project/commit/5da194580292bc90f6577f3959dda3a9bb6d5366
Author: Anand Mistry (MSFT) <anandmistry at microsoft.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
M llvm/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp
M llvm/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.h
A llvm/test/MC/Mips/eva/set-eva-directive.s
A llvm/test/MC/Mips/eva/set-noeva-directive.s
Log Message:
-----------
[Mips] Add set directive support for EVA instructions (#225888)
Add assembler directives to enable/disable access to EVA instructions,
such as `cachee/lbe/sbe/tlbinv/etc`, with `.set eva/noeva`.
Commit: 84c14dac5c730f5b888b42193d252eb41cc77247
https://github.com/llvm/llvm-project/commit/84c14dac5c730f5b888b42193d252eb41cc77247
Author: Utkarsh Saxena <usx at google.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M clang/test/Sema/LifetimeSafety/safety.cpp
Log Message:
-----------
[LifetimeSafety] Add negative-test for `lifetime_capture_by_this` on constructors (#227251)
Commit: 5239371ffa13f30915fe67744be2ea261b74be2a
https://github.com/llvm/llvm-project/commit/5239371ffa13f30915fe67744be2ea261b74be2a
Author: Balázs Benics <benicsbalazs at gmail.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M clang/include/clang/ScalableStaticAnalysis/Analyses/VirtualMethodFamily/VirtualMethodFamily.h
M clang/include/clang/ScalableStaticAnalysis/BuiltinAnchorSources.def
M clang/include/clang/ScalableStaticAnalysis/Core/Model/EntityId.h
M clang/lib/ScalableStaticAnalysis/Analyses/CMakeLists.txt
A clang/lib/ScalableStaticAnalysis/Analyses/VirtualMethodFamily/VirtualMethodFamilyAnalysis.cpp
A clang/unittests/ScalableStaticAnalysis/Analyses/VirtualMethodFamily/VirtualMethodFamilyAnalysisTest.cpp
M clang/unittests/ScalableStaticAnalysis/CMakeLists.txt
Log Message:
-----------
[SSAF] Group virtual method slots into override families (#213317)
A virtual call site can dispatch to any override, so the parameter and
return slots that occupy the same vtable slot across an override chain are
indistinguishable to a caller. Whole-program consumers therefore have to
treat them as one unit or they will reason about a slot that a call never
actually reaches.
Compute those units up front, keyed per slot, so consumers only need a
map lookup rather than their own traversal of the override relation.
Overloads occupy distinct vtable slots and stay in distinct families.
The family representative is the smallest EntityId in the class, which
keeps the result stable across runs.
§2 of rdar://179151603
Assisted-By: claude
Commit: fa10e634e2be9c16a7fdf01aefe0ed45ab6d1b47
https://github.com/llvm/llvm-project/commit/fa10e634e2be9c16a7fdf01aefe0ed45ab6d1b47
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/X86/runtime-alias-checks.ll
Log Message:
-----------
[SLP]Support runtime alias checks versioning for blocks in loops
Allow versioning of blocks inside loops, e.g. fully unrolled inner loop,
whose pointers are advanced by the loop header PHIs. Accept header PHIs
as base objects, use the base values directly in the bounds instead of
recomputing loop-variant bases from their recurrences.
Fixes #49896
Assisted-by: Cursor
Reviewers: RKSimon, bababuck
Pull Request: https://github.com/llvm/llvm-project/pull/226955
Commit: d0adadb4a1838eef7050da75d3526169697b121e
https://github.com/llvm/llvm-project/commit/d0adadb4a1838eef7050da75d3526169697b121e
Author: David Green <david.green at arm.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64Combine.td
Log Message:
-----------
[AArch64][GlobalISel] Reorganise shuffle combines. NFC (#227268)
Other combines had been added between shuffle lowerings, make sure they
are adjacent. Also remove show extra whitespace whilst here.
Commit: 09c59107ab65919fd2c186e57c183819eb42a5df
https://github.com/llvm/llvm-project/commit/09c59107ab65919fd2c186e57c183819eb42a5df
Author: Valery Pykhtin <valery.pykhtin at amd.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/test/MC/AMDGPU/misaligned-vgpr-tuples-err.s
M llvm/test/MC/AMDGPU/out-of-range-registers.s
Log Message:
-----------
[AMDGPU] Route no-modifier reg-or-inline AsmParser operands through HwMode predicate (#221989)
Follow-up to #221988: routes the no-modifier reg-or-inline operands through the HwMode-split *_AlignTarget register classes, like #221988 did for the with-modifiers ones, so VGPR-tuple alignment is enforced by the operand's register class on subtargets that require aligned VGPRs. NFC on subtargets that don't require aligned VGPRs.
Co-Authored-By: Claude [noreply at anthropic.com](mailto:noreply at anthropic.com)
Commit: 51258c8a1fafac2b274cfe05a92f31c40fab1f93
https://github.com/llvm/llvm-project/commit/51258c8a1fafac2b274cfe05a92f31c40fab1f93
Author: Valery Pykhtin <valery.pykhtin at amd.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
Log Message:
-----------
[AMDGPU] Route no-modifier reg-or-inline AsmParser operands through HwMode predicate (#221989)
Follow-up to #221988: routes the no-modifier reg-or-inline operands through the HwMode-split *_AlignTarget register classes, like #221988 did for the with-modifiers ones, so VGPR-tuple alignment is enforced by the operand's register class on subtargets that require aligned VGPRs. NFC on subtargets that don't require aligned VGPRs.
Co-Authored-By: Claude [noreply at anthropic.com](mailto:noreply at anthropic.com)
Commit: 940e03584de8bfbcd86fc25de9a738d067d3a342
https://github.com/llvm/llvm-project/commit/940e03584de8bfbcd86fc25de9a738d067d3a342
Author: Gaëtan Bossu <gaetan.bossu at arm.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M clang/lib/CodeGen/CGLoopInfo.cpp
M clang/test/CodeGenCXX/pragma-loop-predicate.cpp
M clang/test/CodeGenCXX/pragma-loop-safety.cpp
M clang/test/CodeGenCXX/pragma-loop.cpp
Log Message:
-----------
[clang] Also disable scalable vectorisation for vectorize(disable) (#227254)
This ensures that #pragma clang loop vectorize(disable) also disables
scalable vectorisation. Only setting the width to 1 could potentially
enable LoopVectorizer to vectorize with VF = vscale x 1. Especially with
the -scalable-vectorization=preferred option.
Commit: c6a561d18f5d0e5af25200d18a2653b9f18c8e87
https://github.com/llvm/llvm-project/commit/c6a561d18f5d0e5af25200d18a2653b9f18c8e87
Author: Corentin Jabot <corentinjabot at gmail.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M clang/lib/Sema/SemaTemplateDeduction.cpp
M clang/test/SemaTemplate/temp_arg_nontype_ref.cpp
M clang/test/SemaTemplate/temp_arg_template_p0522.cpp
Log Message:
-----------
[Clang] Fix a regression introduced by #223645. (#227085)
In #223645, I removed a fixme I thought was no longer necessary. But it
was, our test coverage is just patchy.
This just reintroduces it to fix the regression,
I have not investigated whether there was a better solution.
I got the AI to write as much tests as i could think of, however this
revealed regressions introduced in an earlier version of clang, this
weill be fixed separately.
Reported in
https://github.com/llvm/llvm-project/pull/223645#issuecomment-5868853308
Assisted-By: Opus 5.5
Commit: 39b72080e0399a15b0313b4eb24e3dbb0aee3c08
https://github.com/llvm/llvm-project/commit/39b72080e0399a15b0313b4eb24e3dbb0aee3c08
Author: Jack Vickers <jack.vickers at arm.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M mlir/lib/Dialect/Tosa/Transforms/TosaNarrowTypes.cpp
M mlir/test/Dialect/Tosa/tosa-narrow-f32-to-f16.mlir
M mlir/test/Dialect/Tosa/tosa-narrow-f64-to-f32.mlir
M mlir/test/Dialect/Tosa/tosa-narrow-i64-to-i32.mlir
Log Message:
-----------
[mlir][tosa] Preserve non-TOSA ops in narrowing passes (#224594)
The TOSA narrowing passes currently reject operations from non-TOSA
dialects even when their types do not require conversion.
This change marks unknown ops as legal provided that their operand and
result types are legal. This follows the approach used by
TosaConvertIntegerTypeToSignless and allows mixed-dialect IR to pass
through TOSA narrowing.
Adds a lit test for each narrowing pass to prove that mixed-dialect is
allowed.
Updates the i64-to-i32 rollback lit test to continue forcing a
conversion failure using illegal operand and result types.
Assisted by: Codex
Commit: c68b1ff4f6af7ed0f96d65739f3826b0ef0fd26c
https://github.com/llvm/llvm-project/commit/c68b1ff4f6af7ed0f96d65739f3826b0ef0fd26c
Author: Hariprasad Ravishankar <hravisha at mathworks.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M mlir/include/mlir/Conversion/Passes.td
M mlir/include/mlir/Conversion/TosaToLinalg/TosaToLinalg.h
M mlir/lib/Conversion/TosaToLinalg/TosaToLinalg.cpp
M mlir/lib/Conversion/TosaToLinalg/TosaToLinalgPass.cpp
M mlir/test/Conversion/TosaToLinalg/tosa-to-linalg.mlir
Log Message:
-----------
[mlir][tosa] Add allow-non-finites option for float min/max reduction (#222140)
TosaToLinalg seeds float min/max reductions with the largest finite
value of the element type, but the TOSA spec asks for the infinite
bound.
[§2.9.4](https://www.mlplatform.org/tosa/tosa_spec_1_0_2.html#_reduce_min)
seeds REDUCE_MIN with `maximum_s<in_out_t>()`,
[§4.5.1](https://www.mlplatform.org/tosa/tosa_spec_1_0_2.html#_arithmetic_helpers)
defines that as the type maximum after `make_signed`,
[§4.5.2](https://www.mlplatform.org/tosa/tosa_spec_1_0_2.html#_type_conversion_helpers)
makes `make_signed` a no-op for floats, and Table 5 in
[§1.9](https://www.mlplatform.org/tosa/tosa_spec_1_0_2.html#_supported_number_formats)
gives that maximum as `+infinity` for fp16, bf16, fp32 and fp64.
REDUCE_MAX and ARGMAX mirror it. The symptom is a clamp: reduce an
all-`+Inf` tensor and you get `3.40282347E+38` back.
This adds an `allow-non-finites` option to `tosa-to-linalg` that selects
the conforming seed.
**Why a flag rather than just fixing the seed.** Non-finite values
aren't always wanted. TOSA has a format that can't represent them at all
— Table 5 bounds fp8e4m3_t at ±448, "This format has no encoding for
infinities" — and embedded code generation often disables them wholesale
to avoid the support code, as MATLAB Coder's `SupportNonFinite` does.
llvm/torch-mlir#4363 added the same toggle under the same name to
ConvertTorchToLinalg and friends; today setting it `true` is silently
dropped for graphs routed through TOSA, so the two backends disagree on
the same model. This makes the flag mean something on both paths.
**Why the default is false.** It keeps this pass's current output.
torch-mlir defaults to `true` because it already emitted `-inf`, so in
both projects the default is the no-op, and setting the flag the same
way on both sides is what makes the paths agree.
**The `semanticsHasInf` guard.** `APFloat::getInf` is `llvm_unreachable`
under FiniteOnly semantics and silently returns a NaN under NanOnly
semantics, e.g. f8E4M3FN. Without the guard every fp8 min/max reduction
would return NaN through NaN-propagating `arith.minimumf`, which is
worse than the bug being fixed. Tests pin f8E4M3FN to the ±448 fallback
with the option both on and off.
Three smaller notes. The flag governs only identities the pass invents,
not the NaN that `nan_mode = IGNORE` is required to produce. ARGMAX is
updated for uniformity but is NFC in effect, since its running max only
feeds the `UGT`/`OGT` predicate and its value output is discarded.
`max_pool2d` in TosaToLinalgNamed.cpp is wrong the same way but left
alone here, because its initial value doubles as the `tensor.pad`
padding value and needs its own review.
Every pre-existing test in tosa-to-linalg.mlir now runs under both
settings, via a second RUN line sharing the CHECK prefix with only the
four seed constants split into FINITE/NONFINITE. New cases cover f16,
bf16 and f64 min/max, argmax f16, both f8E4M3FN fallbacks, and the
IGNORE seed. check-mlir-conversion is green.
Developed with AI assistance (Claude Opus 5 via Claude Code) per the
[LLVM AI Tool Use Policy](https://llvm.org/docs/AIToolPolicy.html): the
implementation, the tests, and the first draft of this description were
tool-generated, then reviewed and edited by me before posting.
Co-authored-by: Hariprasad Ravishankar <hravisha at ls-01-1c-a0-b8-77-e7-5d.dhcp.mathworks.com>
Co-authored-by: Claude Opus 5 <noreply at anthropic.com>
Commit: 04d107c5289d7f39d5eadbf559d330e7ac545bc7
https://github.com/llvm/llvm-project/commit/04d107c5289d7f39d5eadbf559d330e7ac545bc7
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.h
M llvm/test/Transforms/LoopVectorize/AArch64/induction-costs.ll
M llvm/test/Transforms/LoopVectorize/AArch64/predicated-costs.ll
M llvm/test/Transforms/LoopVectorize/AArch64/reduction-cost.ll
M llvm/test/Transforms/LoopVectorize/RISCV/blocks-with-dead-instructions.ll
M llvm/test/Transforms/LoopVectorize/RISCV/dead-ops-cost.ll
M llvm/test/Transforms/LoopVectorize/RISCV/induction-costs.ll
M llvm/test/Transforms/LoopVectorize/RISCV/truncate-to-minimal-bitwidth-cost.ll
M llvm/test/Transforms/LoopVectorize/RISCV/type-info-cache-evl-crash.ll
M llvm/test/Transforms/LoopVectorize/VPlan/memory-checks.ll
M llvm/test/Transforms/LoopVectorize/X86/cost-model.ll
M llvm/test/Transforms/LoopVectorize/X86/interleave-cost.ll
M llvm/test/Transforms/LoopVectorize/consecutive-ptr-uniforms.ll
M llvm/test/Transforms/LoopVectorize/if-conversion.ll
M llvm/test/Transforms/LoopVectorize/induction.ll
M llvm/test/Transforms/LoopVectorize/interleaved-accesses-metadata.ll
M llvm/test/Transforms/LoopVectorize/invariant-store-vectorization-2.ll
M llvm/test/Transforms/LoopVectorize/invariant-store-vectorization.ll
M llvm/test/Transforms/LoopVectorize/metadata.ll
M llvm/test/Transforms/LoopVectorize/opaque-ptr.ll
M llvm/test/Transforms/LoopVectorize/pointer-select-runtime-checks.ll
M llvm/test/Transforms/LoopVectorize/pr59319-loop-access-info-invalidation.ll
M llvm/test/Transforms/LoopVectorize/predicated-inductions-vs-first-order-recurrences.ll
M llvm/test/Transforms/LoopVectorize/runtime-check.ll
Log Message:
-----------
[VPlan] Model first memory runtime checks as VPlan recipes. (#221483)
Add VPlanTransforms::addMemoryRuntimeChecks to generate memory runtime
checks directly as VPlan recipes, re-using VPSCEVExpander. This enables
more CSE/simplification opportunities in VPlan, and in the long term
allows us to remove the current slightly hacky runtime check generation
code, which builds checks up front in IR, and removes them again if we
do not vectorize. This whole dance requires quite a bit of code to make
the removal step transparent if the loop was not vectorized.
The initial patch excludes the following checks from VPlan expansion (to
be added in follow-ups), to keep the initial logic as simple as
possible:
* checks in nested loops (VPlan expansion cannot hoist out of the outer
loop)
* diff checks
* bounds requiring expanding AddRecs (currently AddRecs must be expanded
in the Plan's entry)
The IR block built by GeneratedRTChecks::create() is still needed to
cost the checks and to detect that they folded to a constant. Once all
kinds of runtime checks can be created directly in VPlan, we can compute
their cost via the VPlan-based cost model, like other skeleton blocks.
PR: https://github.com/llvm/llvm-project/pull/221483
Commit: e6d803d0cd96bac00bee2e4b8b23b492f99c1590
https://github.com/llvm/llvm-project/commit/e6d803d0cd96bac00bee2e4b8b23b492f99c1590
Author: HernandezJosze <joseantoniohg at google.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M lldb/source/Plugins/TypeSystem/Clike/TypeSystemClike.cpp
M lldb/source/Plugins/TypeSystem/Clike/TypeSystemClike.h
Log Message:
-----------
[lldb][Clike][NFC] Fix for #222611 (#227146)
Fixes #222611
This fixes an issue with Verify being conditionally compiled only when
assertions are enabled
Commit: 9790fc2b212b3f558460a00a5245f614c7c83317
https://github.com/llvm/llvm-project/commit/9790fc2b212b3f558460a00a5245f614c7c83317
Author: David Green <david.green at arm.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
A llvm/test/CodeGen/ARM/load_store_opt_eraseliveregs.mir
Log Message:
-----------
[ARM] Invalidate LiveRegPos when erasing current position (#226937)
The load store optimizer could erase an instruction that is currently
holding the position of the LiveRegPos. Make sure we recalculate
LiveRegs if this happens.
Fixes #223630
Commit: bbdca00c2b27b77af439872f608ad6632edcc97a
https://github.com/llvm/llvm-project/commit/bbdca00c2b27b77af439872f608ad6632edcc97a
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M .github/workflows/libcxx-pr-conformance-tests.yaml
M .github/workflows/libcxx-pr-test-tools.yml
Log Message:
-----------
[Github] Temporary fix for #226230 (#227144)
It seems that with actions/checkout we run into a 5 minute timeout
somewhere (presumably in the websocket that communicates between the
runner and workflow pods), which causes actions/checkout to succeed but
without actually writing anything out, causing the rest of the workflow
to fail. This patch fixes that by forcing verbose output, which should
ensure there is no 5 minute period without any output.
This issue doesn't seem to impact other parts of the workflow due to
progress indicators.
Commit: 98241b05dd7e3d84144baa5192af515e199ed976
https://github.com/llvm/llvm-project/commit/98241b05dd7e3d84144baa5192af515e199ed976
Author: Kseniya Tikhomirova <kseniya.tikhomirova at intel.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M libsycl/src/detail/context_impl.cpp
M libsycl/src/detail/device_image_wrapper.cpp
M libsycl/src/detail/device_image_wrapper.hpp
M libsycl/src/detail/offload/offload_utils.hpp
M libsycl/src/detail/queue_impl.cpp
M libsycl/src/handler.cpp
M libsycl/src/usm_functions.cpp
M libsycl/unittests/common/unittests_helper.hpp
M libsycl/unittests/handler/semantics.cpp
M libsycl/unittests/mock/helpers.hpp
M libsycl/unittests/queue/memcpy.cpp
M libsycl/unittests/queue/prefetch.cpp
M libsycl/unittests/queue/queue.cpp
M libsycl/unittests/usm/alloc.cpp
Log Message:
-----------
[libsycl] Add context to exception's throw. (#224668)
sycl::exception class can contain associated context (see 4.13.2.
Exception class interface).
Specification doesn't declare rules about when context must be
associated and when not.
Passing context to exception ctor in all places where context is
available.
Assisted-by: Claude Code.
---------
Signed-off-by: Tikhomirova, Kseniya <kseniya.tikhomirova at intel.com>
Commit: 27c315830887f3da871d3ccdb4bb403d8be034b6
https://github.com/llvm/llvm-project/commit/27c315830887f3da871d3ccdb4bb403d8be034b6
Author: Nopileos Isemados <xen134 at outlook.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
M llvm/test/Transforms/InstCombine/minmax-fold.ll
Log Message:
-----------
[InstCombine] Use context in select-to-umin nonzero check (#225381)
foldSelectICmpMinMax() queries whether W is nonzero without an
instruction context, missing facts from a preceding llvm.assume or
dominating branch. Querying at the comparison enables the existing
select-to-umin fold.
Fix #225345
Commit: 7759daa2e9a57a4fe6445531b405217096f416bd
https://github.com/llvm/llvm-project/commit/7759daa2e9a57a4fe6445531b405217096f416bd
Author: Joseph Huber <huberjn at outlook.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M clang/lib/Serialization/ASTReader.cpp
M llvm/include/llvm/Support/Compression.h
M llvm/lib/Support/Compression.cpp
M llvm/unittests/Support/CompressionTest.cpp
Log Message:
-----------
[LLVM] Infer compression format from zlib and zstd headers (#222773)
Summary:
This PR adds two routines that allow users to decompress bitstreams
without explicitly specifying the format. This is inferred from the
bytes
of the object, returning an error if it could not be identified. The
Zstd
standard exposes proper magic bytes, while Zlib needs to be inferred
through the two header bytes.
Because this is a raw bytestream, there is a chance that someone
could get bytes that pass this check, giving no 'reason', but since
the decompression routine requires the expected size there is no
chance it will falsely succeed.
Commit: 6f75865e374f55e9953309425b293b0e364533fd
https://github.com/llvm/llvm-project/commit/6f75865e374f55e9953309425b293b0e364533fd
Author: Joseph Huber <huberjn at outlook.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M flang-rt/CMakeLists.txt
M flang-rt/cmake/modules/AddFlangRT.cmake
M flang-rt/lib/runtime/CMakeLists.txt
M offload/CMakeLists.txt
Log Message:
-----------
[flang-rt][Offload] Fix builds using the new amdgpu triple spelling (#227110)
Summary:
The offload cache files, such as `FlangOffload.cmake`, build the AMDGPU
runtimes for `amdgpu-amd-amdhsa`, but flang-rt and offload only
recognize AMDGPU triples beginning with `amdgcn`. Just check both like
we do elsewhere. Eventually this can all be dropped.
Commit: 78aa14e1df4f0fb200c66732c4d06f52baabf69d
https://github.com/llvm/llvm-project/commit/78aa14e1df4f0fb200c66732c4d06f52baabf69d
Author: Igor Wodiany <igor.wodiany at amd.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M llvm/utils/TableGen/Common/CodeGenRegisters.cpp
Log Message:
-----------
[TableGen] Reuse `UnitMaskIdx` lambda in `computeRegUnitLaneMasks` (NFC) (#227249)
This simplifies the code at the expense of losing an assert that checks
that one `SUI` matches more than one `RU`s.
Commit: 2dc95bd763b87ffb563e2a90180bb7e8c49ec16a
https://github.com/llvm/llvm-project/commit/2dc95bd763b87ffb563e2a90180bb7e8c49ec16a
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M clang-tools-extra/clang-tidy/bugprone/NarrowingConversionsCheck.cpp
M clang/include/clang/AST/Expr.h
M clang/lib/AST/ExprConstant.cpp
M clang/lib/Sema/SemaHLSL.cpp
M clang/lib/Sema/SemaOverload.cpp
Log Message:
-----------
[clang][AST] Make Result parameter of `isCXX11ConstantExpr` mandatory (#226493)
We want to discourage people from just checking if something is a
constant expression without using the value, which we always compute
anyways.
There are only three call sites, all in clang, and all pass a value
already. Change the parameter type to a reference to enforce this.
Commit: c7b2f3191aab2d563d9146d828a195df6103292f
https://github.com/llvm/llvm-project/commit/c7b2f3191aab2d563d9146d828a195df6103292f
Author: Joseph Huber <huberjn at outlook.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M openmp/module/CMakeLists.txt
Log Message:
-----------
[OpenMP] Install the Fortran module files with libomp-mod (#227116)
Summary:
The `libomp-mod` install component only contains `omp_lib.h`. The module
files are only installed incidentally as part of the Fortran runtime or
directory copy. Just do this directly. These were intentinoally dropped
in https://github.com/llvm/llvm-project/pull/171515, in favor of the
directory copy. However, this means these are ignored when done through
the specific component target.
Shouldn't affect plain installs.
Commit: a72d784c52d0913e2f3b8e6b6588bf6b769d78dc
https://github.com/llvm/llvm-project/commit/a72d784c52d0913e2f3b8e6b6588bf6b769d78dc
Author: Joseph Huber <huberjn at outlook.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M compiler-rt/cmake/config-ix.cmake
M runtimes/CMakeLists.txt
Log Message:
-----------
[runtimes] Disable sanitizers for configuration checks with --unwindlib=none (#227092)
Summary:
in a sanitized runtimes build, every configuration check is linked with
both -fsanitize=... and --unwindlib=none and fails, because the
sanitizer runtimes need the unwinder. This completes an existing TODO by
suppressing this for the compiler flag checks in this configuration.
This shouldn't affect any existing users. Motivation is compiling
`+asan` multilibs for existing OpenMP/Offloading configurations.
Commit: a3697dc8170d16e07bc4c507bb1d33b9d65a4c3c
https://github.com/llvm/llvm-project/commit/a3697dc8170d16e07bc4c507bb1d33b9d65a4c3c
Author: Joseph Huber <huberjn at outlook.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M compiler-rt/cmake/Modules/AddCompilerRT.cmake
M compiler-rt/cmake/Modules/CompilerRTAIXUtils.cmake
M compiler-rt/cmake/Modules/CompilerRTDarwinUtils.cmake
M compiler-rt/cmake/Modules/CompilerRTUtils.cmake
M compiler-rt/cmake/Modules/SanitizerUtils.cmake
M compiler-rt/lib/asan/CMakeLists.txt
M compiler-rt/lib/asan/scripts/CMakeLists.txt
M compiler-rt/lib/copyprof/CMakeLists.txt
M compiler-rt/lib/dfsan/CMakeLists.txt
M compiler-rt/lib/hwasan/CMakeLists.txt
M compiler-rt/lib/hwasan/scripts/CMakeLists.txt
M compiler-rt/lib/memprof/CMakeLists.txt
M compiler-rt/lib/msan/CMakeLists.txt
M compiler-rt/lib/tsan/rtl/CMakeLists.txt
Log Message:
-----------
[compiler-rt] Give every installed file an install component (#227103)
Summary:
LLVM tries to expose install components to allow distributions to choose
the layers to build. Not all of the compiler-rt artifacts were installed
under this configuration. This PR makes this a consistent rule by
updating the existing helper function to require a parent target for the
component.
Adds things like
```
ninja install-dfsan
```
and ensures this installs everything
```
ninja install-compiler-rt-x86_64-unknown-linux-gnu
```
Commit: bbb61bc6145835abf356b80b0209a462cf6a4486
https://github.com/llvm/llvm-project/commit/bbb61bc6145835abf356b80b0209a462cf6a4486
Author: Joseph Huber <huberjn at outlook.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M offload/CMakeLists.txt
M offload/languages/cuda/CMakeLists.txt
M offload/languages/hip/CMakeLists.txt
M offload/languages/kernel/CMakeLists.txt
M offload/tools/CMakeLists.txt
M offload/tools/deviceinfo/CMakeLists.txt
M offload/tools/kernelreplay/CMakeLists.txt
Log Message:
-----------
[Offload] Fix installing offload through its install components (#227036)
Summary:
Distribution builds install each runtime through its component's install
target rather than the global `install` target. Several pieces of
offload
did not work with this:
- `install-offload` only depended on `omptarget` and `LLVMOffload`, but
the component also installs `LLVMOffloadKernel`. The install failed
unless something else had already built it.
- The CUDA, HIP, and kernel language headers were installed without a
component, so component installs skipped them.
- The offload tools used `add_llvm_tool` which did not build and/or
install. We already removed `add_llvm_library` from the libraries. Now
these use standard `add_execulable`.
Commit: 64055943ed88d6ad9dea11349c4e9aa736b9b493
https://github.com/llvm/llvm-project/commit/64055943ed88d6ad9dea11349c4e9aa736b9b493
Author: Joseph Huber <huberjn at outlook.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M flang-rt/CMakeLists.txt
M flang-rt/cmake/modules/AddFlangRT.cmake
Log Message:
-----------
[flang-rt] Install the runtime libraries under the flang-rt component (#227073)
Summary:
The Flang-RT libraries were installed without a component, so they were
placed in `Unspecified` and there was no `install-flang-rt` target. The
runtimes build forwards `install-flang-rt` for every enabled runtime, so
requesting flang-rt in a distribution failed on the missing target, and
component installs skipped the libraries. Add the component and its
install targets, matching the existing `flang-rt-headers` and
`flang-rt-mod` components.
Commit: 16c9bb2ea958e6ca41f46f48b4bdb738524e9459
https://github.com/llvm/llvm-project/commit/16c9bb2ea958e6ca41f46f48b4bdb738524e9459
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M llvm/test/CodeGen/SPIRV/cbuffer_global_elim.ll
M llvm/test/CodeGen/SPIRV/debug-info/debug-value-typedef-cycle.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_abort/debugtrap-not-translated.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_abort/trap-ext-disabled.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_bit_instructions_remove_cap_if.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_non_semantic_info/preserve-gv-attributes.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_non_semantic_info/preserve-gv-metadata.ll
M llvm/test/CodeGen/SPIRV/get-global-id-non-integer-dim.ll
M llvm/test/CodeGen/SPIRV/linkage/available-externally-global.ll
M llvm/test/CodeGen/SPIRV/malformed-mangled-builtin-name.ll
M llvm/test/CodeGen/SPIRV/transcoding/enqueue_kernel.ll
M llvm/test/CodeGen/SPIRV/vk-pushconstant-layout.ll
Log Message:
-----------
[NFC][SPIR-V] Add spirv-val RUN lines where missing (#227245)
Commit: 48073298f8a637d40eeeb213eac44706bf3f0ea8
https://github.com/llvm/llvm-project/commit/48073298f8a637d40eeeb213eac44706bf3f0ea8
Author: Joseph Huber <huberjn at outlook.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M offload/plugins-nextgen/amdgpu/dynamic_hsa/hsa.cpp
M offload/plugins-nextgen/cuda/dynamic_cuda/cuda.cpp
Log Message:
-----------
[Offload] Try loading dynamic libraries at global scope first (#227020)
Summary:
The intention of the dynamic path is to provide basic linking in cases
where the SDK is not avaialble at the user's build time. Previously this
did a distinct `dlopen` call on the library.
However, in cases where an existing HSA implementation exists at global
scope this can cause multiple instances to be open at the same time.
Specifically this is problematic if mixing with another implementation
(Like HIP or CUDA) or trying to intercept functions (like compiler-rt).
The compiler-rt interceptors currently carry interceptors into `dlsym`
when we should instead just load these at global scope, this makes them
behave more similar to a direct link in these scenarios, which was the
intention.
The fallback remains as the current behavior, should only trigger in
cases where there is an existing HSA in the process.
Commit: 347b2ed7fd5aef25f45b0f2816b49833d1359dca
https://github.com/llvm/llvm-project/commit/347b2ed7fd5aef25f45b0f2816b49833d1359dca
Author: Joseph Huber <huberjn at outlook.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M offload/liboffload/API/Common.td
M offload/liboffload/src/OffloadImpl.cpp
M offload/tools/offload-tblgen/EntryPointGen.cpp
M offload/unittests/OffloadAPI/init/olInit.cpp
Log Message:
-----------
[Offload] Lazily initialize platforms in the Offloading API (#227084)
Summary:
The Offloading library wraps around the underlying plugins. The problem
is that we currently initialize all plugins we find, even if they are
not needed for the program. This is very expensive for trivial uses, as
fully heterogenous usage is quite rare. In practice this means that you
will always pay a 200 ms penalty for having CUDA installed.
This patch changes the behavior to provide accessors into the plugins
and devices that allows them to be initialized lazily. We use a
once_flag, this should properly take a fast-path check while still
blocking on concurrent use.
Making full use of this will require a way to filter platforms more
specifically. I'm thinking of what this would look like as an API.
I'm thinking that we either have an extra iterate function that takes a
callback on the platform, or we just provide a helper to find all the
devices that can run a given image. Maybe both?
Fixes: #159636
Realnd of: https://github.com/llvm/llvm-project/pull/163272
Commit: 0d546ff00281aca3e0aa2b81573665f3ddb8b5b9
https://github.com/llvm/llvm-project/commit/0d546ff00281aca3e0aa2b81573665f3ddb8b5b9
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M libcxx/test/benchmarks/containers/associative/associative_container_benchmarks.h
Log Message:
-----------
[libc++] Fix "leak" of PMR resource in benchmark (#216114)
The benchmark was not releasing the monotonic buffer resource, which
means we'd grow a larger and larger pool as Google Benchmark would go
through more and more iterations of the benchmark.
Commit: 69d96b19d754340e23e5c08acd2ffed0e9920b59
https://github.com/llvm/llvm-project/commit/69d96b19d754340e23e5c08acd2ffed0e9920b59
Author: Ramkumar Ramachandra <artagnon at tenstorrent.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M llvm/include/llvm/Analysis/IVDescriptors.h
M llvm/include/llvm/Analysis/ScalarEvolution.h
M llvm/include/llvm/Analysis/ScalarEvolutionExpressions.h
M llvm/include/llvm/Analysis/ScalarEvolutionPatternMatch.h
M llvm/include/llvm/Transforms/Utils/ScalarEvolutionExpander.h
M llvm/lib/Analysis/IVDescriptors.cpp
M llvm/lib/Analysis/LoopAccessAnalysis.cpp
M llvm/lib/Analysis/LoopCacheAnalysis.cpp
M llvm/lib/Analysis/ScalarEvolution.cpp
M llvm/lib/Analysis/ScalarEvolutionDivision.cpp
M llvm/lib/Transforms/Utils/ScalarEvolutionExpander.cpp
M polly/lib/Support/SCEVAffinator.cpp
Log Message:
-----------
[SCEV] Rename SCEVNoWrapFlags to SCEVFlags (NFC) (#225179)
In preparation to extend the flags that ScalarEvolution can represent,
rename SCEVNoWrapFlags to the more general SCEVFlags. In particular, we
preserve the (get|set)NoWrapFlags interface, which simply masks the
no-wrap flags from the newly-introduced (get|set)Flags.
See also: #225065.
Commit: 96983af41ec1408064d7101c4d49d8f6e5fba1d6
https://github.com/llvm/llvm-project/commit/96983af41ec1408064d7101c4d49d8f6e5fba1d6
Author: Kseniya Tikhomirova <kseniya.tikhomirova at intel.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M libsycl/include/sycl/__spirv/spirv_vars.hpp
Log Message:
-----------
[libsycl] Remove libsycl declarations of spirv builtins (#227031)
Assisted-by: Claude Code.
Signed-off-by: Tikhomirova, Kseniya <kseniya.tikhomirova at intel.com>
Commit: 10fd0a4ec7ff6d23dab3920f09d69b7e46a471fb
https://github.com/llvm/llvm-project/commit/10fd0a4ec7ff6d23dab3920f09d69b7e46a471fb
Author: David Green <david.green at arm.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
Log Message:
-----------
[ARM] Invalidate LiveRegPos when erasing current position (#226937)
The load store optimizer could erase an instruction that is currently
holding the position of the LiveRegPos. Make sure we recalculate
LiveRegs if this happens.
Fixes #223630
Commit: 40666908139b18ca57d2735f6c00827c89837149
https://github.com/llvm/llvm-project/commit/40666908139b18ca57d2735f6c00827c89837149
Author: Tomer Shafir <tomer.shafir8 at gmail.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M llvm/include/llvm/CodeGen/ScheduleDAG.h
M llvm/lib/CodeGen/MachinePipeliner.cpp
M llvm/lib/CodeGen/MachineScheduler.cpp
M llvm/lib/CodeGen/MacroFusion.cpp
M llvm/lib/CodeGen/ScheduleDAG.cpp
M llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
M llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp
M llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
M llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp
M llvm/lib/Target/AMDGPU/GCNILPSched.cpp
M llvm/lib/Target/AMDGPU/GCNMinRegStrategy.cpp
M llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
M llvm/lib/Target/AMDGPU/GCNVOPDUtils.cpp
M llvm/lib/Target/AMDGPU/SIMachineScheduler.cpp
M llvm/lib/Target/RISCV/RISCVMachineScheduler.cpp
M llvm/lib/Target/SystemZ/SystemZHazardRecognizer.cpp
M llvm/lib/Target/SystemZ/SystemZMachineScheduler.cpp
Log Message:
-----------
[MISched] Extract `operator<<` for SUnit(NFC) (#226785)
Establish a consistent API for printing a SUnit, rather than a scattered
duplication.
Commit: 72a712b0a552fe1f6e44fa445ea389f6519ef491
https://github.com/llvm/llvm-project/commit/72a712b0a552fe1f6e44fa445ea389f6519ef491
Author: Balázs Benics <benicsbalazs at gmail.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M clang/include/clang/ScalableStaticAnalysis/Analyses/VirtualMethodFamily/VirtualMethodFamily.h
M clang/include/clang/ScalableStaticAnalysis/BuiltinAnchorSources.def
M clang/lib/ScalableStaticAnalysis/Analyses/CMakeLists.txt
M clang/lib/ScalableStaticAnalysis/Analyses/VirtualMethodFamily/VirtualMethodFamilyAnalysis.cpp
A clang/lib/ScalableStaticAnalysis/Analyses/VirtualMethodFamily/VirtualMethodFamilyFormat.cpp
M clang/unittests/ScalableStaticAnalysis/CMakeLists.txt
A clang/unittests/ScalableStaticAnalysis/Serialization/JSONFormatTest/VirtualMethodFamilyFormatTest.cpp
Log Message:
-----------
[SSAF] Serialize virtual method summaries and families (#213318)
Per-TU summaries and whole-program results cross process boundaries, and
the JSON layer refuses to write a summary kind it has no format for.
Register both sides so
--ssaf-extract-summaries=VirtualMethod becomes usable and the
family result survives a round trip.
Deserialization tolerates a missing override list, since a root virtual
method legitimately has none.
§3 of rdar://179151603
Assisted-By: claude
Commit: 7e19707aeebbd0ae3101ddc7347fef7a865154f4
https://github.com/llvm/llvm-project/commit/7e19707aeebbd0ae3101ddc7347fef7a865154f4
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M mlir/include/mlir/Support/InterfaceSupport.h
M mlir/test/mlir-tblgen/op-interface.td
M mlir/tools/mlir-tblgen/OpInterfacesGen.cpp
Log Message:
-----------
[mlir][ODS] Copy constant generated interface model prototypes (#226323)
Generate constexpr constructors for interface models whose concept is a
table of callbacks. Construct exact generated models from a static
prototype; keep external and fallback models on their existing path.
In OpenMPDialect.cpp this saves about 0.22B compiler instructions and
10.5KB of text.
Assisted-by: Codex
Commit: b7cc7eed1c272a0ba4798891e5867b974d0cae14
https://github.com/llvm/llvm-project/commit/b7cc7eed1c272a0ba4798891e5867b974d0cae14
Author: Alex Duran <alejandro.duran at intel.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M offload/test/offloading/shared_lib_global_var.c
Log Message:
-----------
[offload][omp] Add NVIDIA LTO to unsupported list in shlib global var test (#227315)
Commit: 2bf008c3ad7fc34de4a6c9eb1bd8910457d48a34
https://github.com/llvm/llvm-project/commit/2bf008c3ad7fc34de4a6c9eb1bd8910457d48a34
Author: Akash Manna <akash.manna.mymail at gmail.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M clang/docs/ReleaseNotes.md
M clang/lib/CodeGen/CGStmtOpenMP.cpp
M clang/lib/Sema/SemaOpenMP.cpp
A clang/test/OpenMP/target_global_ref_namespace_scope_lambda.cpp
A clang/test/OpenMP/target_global_ref_namespace_scope_lambda_codegen.cpp
Log Message:
-----------
[clang][OpenMP] Fix crashes on target regions inside namespace-scope lambdas and blocks (#226691)
Fixes #223397
A `target` region inside a lambda or block at namespace scope crashed
clang in two places. In Sema, `isOpenMPCapturedDecl` decides whether a
global must be captured by walking the function scope stack down to the
innermost OpenMP captured region, stopping at an ordinary function
scope. The capture initializers of a directive's outermost region are
built after all of its regions have been popped. Inside a function that
walk ends at the function's scope, but a namespace-scope lambda or block
has nothing underneath it, so the walk ran off the stack and asserted.
This happens for any global reference, such as `int &r = x; auto l = []
{ #pragma omp target r = 1; };`. The self-referential declaration in the
report is incidental. Once past Sema, CodeGen asserted too: it names the
outlined kernel after the region's parent function, and such a region
has none, even without a reference.
In Sema, running out of scopes now means the same as reaching a function
scope, so the variable is not captured from the current scope. That is
what the same lambda already gets inside a function. In CodeGen, a
region with no parent function is named after the function being
emitted.
Commit: 14b01288b6a80666538100f8798fe492297e6d0b
https://github.com/llvm/llvm-project/commit/14b01288b6a80666538100f8798fe492297e6d0b
Author: Delaram Talaashrafi <dtalaashrafi at nvidia.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M mlir/lib/Dialect/OpenACC/Transforms/ACCCGToGPU.cpp
M mlir/test/Dialect/OpenACC/acc-cg-to-gpu-predicate-region-reuse-barrier.mlir
Log Message:
-----------
[mlir][OpenACC] Match reuse barriers to the reused private scope (#225570)
A region that writes both gang- and worker-private slots was considered
to be a gang scope and a barrier was missed. This change keeps the two
store sets separate and pick the barrier from the scope that is actually
reused. Follow-up for
https://github.com/llvm/llvm-project/pull/224437#discussion_r4066418696.
Commit: 0b3eb216bba43c93fb416853aaefd1fb382a7aab
https://github.com/llvm/llvm-project/commit/0b3eb216bba43c93fb416853aaefd1fb382a7aab
Author: Akash Manna <akash.manna.mymail at gmail.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
M llvm/lib/Transforms/Utils/SimplifyLibCalls.cpp
M llvm/test/Transforms/InstCombine/cos-1.ll
M llvm/test/Transforms/InstCombine/cos-sin-intrinsic.ll
Log Message:
-----------
[InstCombine] Don't fold `sin(-x)` to `-sin(x)` if `denormals` may flush to `+0.0` (#227039)
Commit: 7fb36ba334861cb92245f8e4535bc14d068f8776
https://github.com/llvm/llvm-project/commit/7fb36ba334861cb92245f8e4535bc14d068f8776
Author: Kareem Ergawy <kergawy at nvidia.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M flang/include/flang/Lower/PFTBuilder.h
M flang/lib/Lower/PFTBuilder.cpp
A flang/test/Lower/do-loop-infinite-body-cycle.f90
M flang/test/Lower/pre-fir-tree-assigned-goto.f90
A flang/test/Lower/pre-fir-tree-branch-into-body.f90
A flang/test/Lower/pre-fir-tree-unstructured-internals.f90
M flang/test/Lower/trailing-cycle.f90
Log Message:
-----------
[flang] Detect loops whose branching is confined to their body (#225757)
A DO loop is classified as either structured or unstructured, and a
single raw branch anywhere in its body forces the loop -- and every
construct enclosing it -- onto the unstructured path.
That is stronger than necessary. A loop keeps its structured control
flow as long as its branching neither leaves its body nor enters it from
outside. Classify such a loop separately from a fully unstructured one.
This only classifies: lowering is unchanged. PFT dumps mark the new
classification with '~', which is what the tests key on.
Commit: 13b63a519fcc542667e0ebaa7ffa930e821b531c
https://github.com/llvm/llvm-project/commit/13b63a519fcc542667e0ebaa7ffa930e821b531c
Author: Shravan Sheth <shrashet at qti.qualcomm.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M llvm/test/CodeGen/Hexagon/live-vars/live-outs.ll
Log Message:
-----------
[Hexagon] Add missing -mtriple to live-outs test (#227079)
This test's RUN command did not specify a target triple, so lit could
execute it using the host target.
This causes the test to fail when LLVM is built with only the Hexagon
target enabled. Add -mtriple=hexagon so the test consistently runs as a
Hexagon test.
Commit: 236e0ee3d763814d16b3d7947ba740fe4d4e31be
https://github.com/llvm/llvm-project/commit/236e0ee3d763814d16b3d7947ba740fe4d4e31be
Author: John Brawn <john.brawn at arm.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Scalar/SROA.cpp
M llvm/test/Transforms/SROA/load-store-overlap.ll
Log Message:
-----------
[SROA] Remove splitSliceTails loop in presplitLoadsAndStores (#227061)
The asserts in this loop can trigger when we presplit an overlapping
load/store pair, and the extra splits it adds don't appear to have any
benefit: we only get them when we have an unsplittable slice that's
fully enclosed inside a splittable slice, and in the test I've managed
to create for this (no_move_enclosed_unsplittable_store, and there are
no existing tests for this) the final SROA output is the same (except
that the variables end up with different names).
Commit: fb1a7d048b4eb2f9a855e961f59c0a4b7bd5ee8b
https://github.com/llvm/llvm-project/commit/fb1a7d048b4eb2f9a855e961f59c0a4b7bd5ee8b
Author: David Sherwood <david.sherwood at arm.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M llvm/test/Transforms/LoopVectorize/ARM/tail-folding-scalar-epilogue-fallback.ll
M llvm/test/Transforms/LoopVectorize/X86/induction-costs.ll
M llvm/test/Transforms/LoopVectorize/optimal-epilog-vectorization-liveout.ll
M llvm/test/Transforms/LoopVectorize/pr59319-loop-access-info-invalidation.ll
M llvm/test/Transforms/LoopVectorize/select-last-index-fp.ll
M llvm/test/Transforms/PhaseOrdering/AArch64/hoist-runtime-checks.ll
Log Message:
-----------
[LV] Regenerate some CHECK lines (#226468)
Commit: 0cf09fc077d86dd454a58a292da8c047efe64af9
https://github.com/llvm/llvm-project/commit/0cf09fc077d86dd454a58a292da8c047efe64af9
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
A llvm/test/CodeGen/X86/twoaddr-reschedule-copy-chain.mir
Log Message:
-----------
TwoAddressInstructions: Move the rescheduled copy chain back to front (#227289)
rescheduleMIBelowKill sinks an instruction below the kill of its tied
source, along with the run of copies that follows it. With LiveIntervals
the copies are spliced one at a time so handleMove sees a well-formed
block, but they were visited front to back and each inserted before the
previously moved one. This reversed them, and transiently moved a copy
below its use, asserting in handleMoveDown.
Walk them back to front instead, which also preserves the original
order.
Exposed by #225174, which made LiveIntervals available here by default.
Co-authored-by: Claude Opus 5 <noreply at anthropic.com>
Commit: 34ba34d7f9bd2c756db7df96d3a5be39f006aa19
https://github.com/llvm/llvm-project/commit/34ba34d7f9bd2c756db7df96d3a5be39f006aa19
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
M llvm/test/Transforms/InstCombine/bitreverse.ll
M llvm/utils/profcheck-xfail.txt
Log Message:
-----------
[InstCombine] Fix ProfCheck for optimizing bitreverse (#227189)
Commit: 15ec5f2940998ddd77be1571a0d4b932b5a2878a
https://github.com/llvm/llvm-project/commit/15ec5f2940998ddd77be1571a0d4b932b5a2878a
Author: Jeffrey Byrnes <jeffrey.byrnes at amd.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/bitcast-vector-extract.ll
Log Message:
-----------
[AMDGPU] Replace GCN-NOT with autogen checks in test (#227148)
The assembly has many v_mov_b32s, so minor scheduling changes can
trigger failure on the GCN-NOT. It seems the test is designed to show
CSE behavior, which still holds even if minor scheduling changes break
the NOT checks.
Commit: e15e5e67f6d5e0fc44c011381a53357a2bd843bf
https://github.com/llvm/llvm-project/commit/e15e5e67f6d5e0fc44c011381a53357a2bd843bf
Author: Folkert de Vries <folkert at folkertdev.nl>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M llvm/include/llvm/CodeGen/BasicTTIImpl.h
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/test/Analysis/CostModel/AArch64/clmul-fixed.ll
M llvm/test/Analysis/CostModel/AArch64/clmul-scalable.ll
M llvm/test/Analysis/CostModel/X86/clmul.ll
M llvm/test/CodeGen/AArch64/clmul-scalable.ll
M llvm/test/CodeGen/AArch64/clmul.ll
M llvm/test/CodeGen/PowerPC/clmul-vector.ll
M llvm/test/CodeGen/RISCV/clmul.ll
M llvm/test/CodeGen/RISCV/clmulh.ll
M llvm/test/CodeGen/RISCV/clmulr.ll
M llvm/test/CodeGen/RISCV/rvv/clmul-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/clmulh-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-clmul.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-clmulh.ll
M llvm/test/CodeGen/Thumb2/mve-clmul.ll
M llvm/test/CodeGen/X86/clmul-vector-256.ll
M llvm/test/CodeGen/X86/clmul-vector-512.ll
M llvm/test/CodeGen/X86/clmul-vector.ll
M llvm/test/CodeGen/X86/clmul.ll
Log Message:
-----------
[ISel] Improve `clmul` fallback implementation (#204802)
Generalize the approach from
https://github.com/llvm/llvm-project/pull/203727 to narrower and wider
integers.
We still need the fallback for when multiplication isn't available, and
it turns out that for some widths the fallback emits fewer instructions,
the naive fallback is still used for `i1`, `i3`, `i4` and `i9`. I've
also now enabled wider integers (`i128` and `i256` have uses in
cryptography).
Based on my local experiments, the Karatsuba approach (e.g. as in
https://github.com/rust-lang/rust/pull/152132#discussion_r2778609222) is
not actually better than zero extending the input and using
multiplication with holes on the wider type.
CC https://github.com/llvm/llvm-project/issues/203694
CC: @eisenwave
Commit: 09cdef016cfc756b29002cd7870c63b7f1b09c6b
https://github.com/llvm/llvm-project/commit/09cdef016cfc756b29002cd7870c63b7f1b09c6b
Author: DylanFleming-arm <85629460+DylanFleming-arm at users.noreply.github.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M libc/src/__support/math/CMakeLists.txt
M libc/src/__support/math/cosf.h
A libc/src/__support/math/cosf_double_eval.h
A libc/src/__support/math/cosf_float_eval.h
M libc/src/__support/math/sinf.h
A libc/src/__support/math/sinf_double_eval.h
A libc/src/__support/math/sinf_float_eval.h
M libc/test/src/math/CMakeLists.txt
R libc/test/src/math/cosf_float_test.cpp
M libc/test/src/math/cosf_test.cpp
M libc/test/src/math/exhaustive/CMakeLists.txt
R libc/test/src/math/exhaustive/cosf_float_test.cpp
M libc/test/src/math/exhaustive/cosf_test.cpp
R libc/test/src/math/exhaustive/sinf_float_test.cpp
M libc/test/src/math/exhaustive/sinf_test.cpp
R libc/test/src/math/sinf_float_test.cpp
M libc/test/src/math/sinf_test.cpp
Log Message:
-----------
[libc][math] Reorganize sinf and cosf function selection (#226529)
Reorganises sinf and cosf similarly to #224735 such that:
src/__support/math/func.h selects implementation, and
src/__support/math/func_<type>_eval.h implements func with <type> as the
intermediate computational type.
Commit: 1b5f644b9e3f9dbd9ce061dbfaf9188510cf82cf
https://github.com/llvm/llvm-project/commit/1b5f644b9e3f9dbd9ce061dbfaf9188510cf82cf
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
Log Message:
-----------
[libc++] Encode the standard version in the ABI tag (#218527)
This prevents ODR mismatch issues from biting us across standard
versions. The order of elements in the ABI tag is now: libc++ version,
hardening mode, assertion semantic, exceptions, standard version.
Fixes #218524
Commit: 6cd0f021ec7372be132b00ff2847822a77966a57
https://github.com/llvm/llvm-project/commit/6cd0f021ec7372be132b00ff2847822a77966a57
Author: Spencer Bryngelson <sbryngelson at gmail.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M flang-rt/cmake/modules/AddFlangRTOffload.cmake
M flang-rt/include/flang-rt/runtime/io-stmt.h
M flang-rt/include/flang-rt/runtime/work-queue.h
M flang-rt/lib/runtime/CMakeLists.txt
M flang-rt/lib/runtime/io-api-common.h
M flang/include/flang/Common/api-attrs.h
Log Message:
-----------
[flang-rt] Use thin I/O in the native GPU builds (#226307)
The amdgcn libflang_rt.runtime.a has undefined references to the DescriptorIoTicket/DerivedIoTicket methods and to flang_rt_verbose_abort. The tickets live in descriptor-io.cpp, which isn't in gpu_sources, but the work queue still refers to them. Any device code that ends up in the work queue (e.g. ALLOCATE of a derived type with default initialization in a target region) then fails to link.
The CUDA PTX build already avoids this with a thin I/O mode. This renames `RT_CUDA_THIN_IO` to `RT_THIN_IO`, defines it in api-attrs.h for the native GPU builds (`RT_GPU_TARGET` without `RT_DEVICE_COMPILATION`), and keeps the CMake define for the CUDA PTX library under the new name. flang_rt_verbose_abort is defined in stl-overrides.cpp, so that's added to gpu_sources.
Tested on gfx90a. The amdgcn library no longer has those undefined symbols, gains only the flang_rt_verbose_abort definition, and doesn't lose any others. A small reproducer (derived type with default init allocated inside a target region) links and runs, and scalar PRINT from device code gives the same output as before. The host library's symbols are identical to before. I haven't built nvptx or the CUDA offload configuration.
Downstream report: ROCm/llvm-project#3517
Commit: 5274c3a051776d95c0314d80ffd84b45be1539d3
https://github.com/llvm/llvm-project/commit/5274c3a051776d95c0314d80ffd84b45be1539d3
Author: Spencer Bryngelson <sbryngelson at gmail.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
Log Message:
-----------
[flang-rt] Use thin I/O in the native GPU builds (#226307)
Commit: b6d343888fb725a8d98d2ca56607ef754664baa9
https://github.com/llvm/llvm-project/commit/b6d343888fb725a8d98d2ca56607ef754664baa9
Author: mssefat <syadus.sefat at gmail.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M .ci/green-dragon/lldb-windows.groovy
M .github/workflows/bazel-checks.yml
M .github/workflows/build-ci-container-tooling.yml
M .github/workflows/build-ci-container-windows.yml
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M flang/docs/OpenMPSupport.md
M flang/include/flang/Common/api-attrs.h
M flang/include/flang/Lower/PFTBuilder.h
M flang/include/flang/Lower/PFTDefs.h
M flang/include/flang/Optimizer/Builder/CUDAIntrinsicCall.h
M flang/include/flang/Optimizer/Builder/CUFCommon.h
M flang/include/flang/Optimizer/Dialect/CUF/CUFDialect.td
M flang/include/flang/Optimizer/Dialect/CUF/CUFOps.td
M flang/include/flang/Optimizer/Dialect/FIRCG/CGOps.td
M flang/include/flang/Optimizer/Dialect/FIRDialect.td
M flang/include/flang/Optimizer/Dialect/MIF/MIFDialect.td
M flang/include/flang/Optimizer/HLFIR/HLFIROpBase.td
M flang/include/flang/Optimizer/Transforms/Passes.td
M flang/include/flang/Support/Fortran-features.h
M flang/lib/Lower/OpenMP/ClauseProcessor.cpp
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/lib/Lower/OpenMP/Utils.cpp
M flang/lib/Lower/OpenMP/Utils.h
M flang/lib/Lower/PFTBuilder.cpp
M flang/lib/Optimizer/Builder/CUDAIntrinsicCall.cpp
M flang/lib/Optimizer/Builder/CUFCommon.cpp
M flang/lib/Optimizer/Transforms/CMakeLists.txt
R flang/lib/Optimizer/Transforms/CUDA/CUFFunctionRewrite.cpp
M flang/lib/Optimizer/Transforms/CUDA/CUFOpConversion.cpp
M flang/lib/Optimizer/Transforms/CUDA/CUFOpConversionLate.cpp
M flang/lib/Optimizer/Transforms/LoopInvariantCodeMotion.cpp
M flang/lib/Parser/openacc-parsers.cpp
M flang/lib/Semantics/check-acc-structure.cpp
M flang/lib/Semantics/check-acc-structure.h
M flang/lib/Semantics/check-declarations.cpp
M flang/lib/Semantics/check-omp-structure.cpp
R flang/test/Fir/CUDA/cuda-function-rewrite.mlir
A flang/test/Fir/CUDA/cuda-on-device.mlir
M flang/test/Fir/cuf.mlir
A flang/test/Integration/OpenMP/allocate-clause-equivalence.f90
A flang/test/Integration/OpenMP/scope-allocate-clause.f90
A flang/test/Lower/CUDA/cuda-on-device.cuf
M flang/test/Lower/OpenMP/Todo/allocate-clause-unsupported.f90
A flang/test/Lower/OpenMP/Todo/scope-allocate-clause-unsupported.f90
R flang/test/Lower/OpenMP/Todo/taskwait-nowait.f90
M flang/test/Lower/OpenMP/declare-mapper.f90
M flang/test/Lower/OpenMP/scope.f90
A flang/test/Lower/OpenMP/target-map-nested-dtype-allocatable-member.f90
M flang/test/Lower/OpenMP/target-scope.f90
M flang/test/Lower/assigned-goto-labeled-end.f90
A flang/test/Lower/do-loop-infinite-body-cycle.f90
M flang/test/Lower/ifconvert.f90
M flang/test/Lower/pre-fir-tree-assigned-goto.f90
A flang/test/Lower/pre-fir-tree-branch-into-body.f90
A flang/test/Lower/pre-fir-tree-incoming-branches.f90
A flang/test/Lower/pre-fir-tree-unstructured-internals.f90
M flang/test/Lower/trailing-cycle.f90
M flang/test/Parser/acc-label-do.f90
A flang/test/Semantics/OpenACC/acc-routine-loop-nesting.f90
A flang/test/Semantics/OpenMP/taskwait-nowait.f90
A flang/test/Semantics/bind-c20.f90
A flang/test/Semantics/bind-c21.f90
A flang/test/Transforms/licm-acc-captured-ref.fir
A flang/test/Transforms/licm-acc-compute-only.fir
A flang/test/Transforms/licm-scope.fir
M libc/config/linux/aarch64/entrypoints.txt
M libc/config/linux/arm/entrypoints.txt
M libc/config/linux/i386/entrypoints.txt
M libc/config/linux/riscv/entrypoints.txt
M libc/config/linux/x86_64/entrypoints.txt
M libc/include/fcntl.yaml
M libc/include/grp.yaml
M libc/include/llvm-libc-macros/linux/fcntl-macros.h
M libc/include/pwd.yaml
M libc/src/__support/FPUtil/FEnvImpl.h
M libc/src/__support/OSUtil/linux/syscall_wrappers/close.h
M libc/src/__support/OSUtil/linux/syscall_wrappers/dup.h
M libc/src/__support/OSUtil/linux/syscall_wrappers/dup2.h
M libc/src/__support/OSUtil/linux/syscall_wrappers/dup3.h
M libc/src/__support/OSUtil/linux/syscall_wrappers/fcntl.h
M libc/src/__support/OSUtil/linux/syscall_wrappers/fsync.h
M libc/src/__support/OSUtil/linux/syscall_wrappers/ftruncate.h
M libc/src/__support/OSUtil/linux/syscall_wrappers/lseek.h
M libc/src/__support/OSUtil/linux/syscall_wrappers/memfd_create.h
M libc/src/__support/OSUtil/linux/syscall_wrappers/read.h
M libc/src/__support/OSUtil/linux/syscall_wrappers/write.h
M libc/src/__support/math/CMakeLists.txt
M libc/src/__support/math/cosf.h
A libc/src/__support/math/cosf_double_eval.h
A libc/src/__support/math/cosf_float_eval.h
M libc/src/__support/math/sinf.h
A libc/src/__support/math/sinf_double_eval.h
A libc/src/__support/math/sinf_float_eval.h
M libc/src/__support/printf_core/float_dec_converter.h
M libc/src/__support/printf_core/float_dec_converter_limited.h
M libc/src/__support/printf_core/float_hex_converter.h
M libc/src/__support/printf_core/float_inf_nan_converter.h
M libc/src/__support/pwd/flat_file_db.h
M libc/src/grp/CMakeLists.txt
A libc/src/grp/getgrouplist.cpp
A libc/src/grp/getgrouplist.h
M libc/src/grp/grp_utils.cpp
M libc/src/grp/grp_utils.h
M libc/src/pwd/CMakeLists.txt
A libc/src/pwd/getpwent_r.cpp
A libc/src/pwd/getpwent_r.h
M libc/src/pwd/pwd_utils.cpp
M libc/src/pwd/pwd_utils.h
M libc/src/stdlib/str_from_util.h
M libc/src/stdlib/strfromd.cpp
M libc/src/stdlib/strfromf.cpp
M libc/src/stdlib/strfroml.cpp
M libc/test/src/grp/CMakeLists.txt
A libc/test/src/grp/getgrouplist_test.cpp
M libc/test/src/math/CMakeLists.txt
R libc/test/src/math/cosf_float_test.cpp
M libc/test/src/math/cosf_test.cpp
M libc/test/src/math/exhaustive/CMakeLists.txt
R libc/test/src/math/exhaustive/cosf_float_test.cpp
M libc/test/src/math/exhaustive/cosf_test.cpp
R libc/test/src/math/exhaustive/sinf_float_test.cpp
M libc/test/src/math/exhaustive/sinf_test.cpp
R libc/test/src/math/sinf_float_test.cpp
M libc/test/src/math/sinf_test.cpp
M libc/test/src/pwd/CMakeLists.txt
A libc/test/src/pwd/getpwent_r_test.cpp
M libc/test/src/stdlib/strfromf_test.cpp
A libcxx/docs/ABIGuarantees.md
R libcxx/docs/ABIGuarantees.rst
A libcxx/docs/AddingNewCIJobs.md
R libcxx/docs/AddingNewCIJobs.rst
A libcxx/docs/CodingGuidelines.md
R libcxx/docs/CodingGuidelines.rst
A libcxx/docs/Contributing.md
R libcxx/docs/Contributing.rst
A libcxx/docs/Contributing/NewStandardProcedure.md
R libcxx/docs/Contributing/NewStandardProcedure.rst
A libcxx/docs/Contributing/PostMeetingProcedure.md
R libcxx/docs/Contributing/PostMeetingProcedure.rst
A libcxx/docs/Contributing/ReleaseProcedure.md
R libcxx/docs/Contributing/ReleaseProcedure.rst
A libcxx/docs/DesignDocs/ABIVersioning.md
R libcxx/docs/DesignDocs/ABIVersioning.rst
A libcxx/docs/DesignDocs/AtomicDesign.md
R libcxx/docs/DesignDocs/AtomicDesign.rst
A libcxx/docs/DesignDocs/CapturingConfigInfo.md
R libcxx/docs/DesignDocs/CapturingConfigInfo.rst
A libcxx/docs/DesignDocs/ExperimentalFeatures.md
R libcxx/docs/DesignDocs/ExperimentalFeatures.rst
A libcxx/docs/DesignDocs/ExtendedCXX03Support.md
R libcxx/docs/DesignDocs/ExtendedCXX03Support.rst
A libcxx/docs/DesignDocs/FeatureTestMacros.md
R libcxx/docs/DesignDocs/FeatureTestMacros.rst
A libcxx/docs/DesignDocs/FileTimeType.md
R libcxx/docs/DesignDocs/FileTimeType.rst
A libcxx/docs/DesignDocs/HeaderRemovalPolicy.md
R libcxx/docs/DesignDocs/HeaderRemovalPolicy.rst
M libcxx/docs/Hardening.rst
M libcxx/docs/conf.py
M libcxx/include/CMakeLists.txt
M libcxx/include/__algorithm/pstl.h
M libcxx/include/__chrono/convert_to_tm.h
M libcxx/include/__chrono/duration.h
M libcxx/include/__configuration/abi.h
M libcxx/include/__configuration/attributes.h
M libcxx/include/__format/buffer.h
M libcxx/include/__ostream/print.h
M libcxx/include/__pstl/backend_fwd.h
M libcxx/include/__pstl/backends/default.h
M libcxx/include/__pstl/backends/libdispatch.h
M libcxx/include/__pstl/backends/serial.h
M libcxx/include/__pstl/backends/std_thread.h
A libcxx/include/__pstl/cpu_algos/swap_ranges.h
M libcxx/include/__ranges/adjacent_transform_view.h
M libcxx/include/__ranges/adjacent_view.h
M libcxx/include/__ranges/chunk_by_view.h
M libcxx/include/__ranges/common_view.h
M libcxx/include/__ranges/concat_view.h
M libcxx/include/__ranges/counted.h
M libcxx/include/__ranges/drop_view.h
M libcxx/include/__ranges/drop_while_view.h
M libcxx/include/__ranges/elements_view.h
M libcxx/include/__ranges/empty_view.h
M libcxx/include/__ranges/enumerate_view.h
M libcxx/include/__ranges/filter_view.h
M libcxx/include/__ranges/iota_view.h
M libcxx/include/__ranges/join_view.h
M libcxx/include/__ranges/join_with_view.h
M libcxx/include/__ranges/lazy_split_view.h
M libcxx/include/__ranges/movable_box.h
M libcxx/include/__ranges/non_propagating_cache.h
M libcxx/include/__ranges/rbegin.h
M libcxx/include/__ranges/rend.h
M libcxx/include/__ranges/reverse_view.h
M libcxx/include/__ranges/single_view.h
M libcxx/include/__ranges/split_view.h
M libcxx/include/__ranges/stride_view.h
M libcxx/include/__ranges/take_view.h
M libcxx/include/__ranges/take_while_view.h
M libcxx/include/__ranges/to.h
M libcxx/include/__ranges/transform_view.h
M libcxx/include/__ranges/views.h
M libcxx/include/__ranges/zip_transform_view.h
M libcxx/include/__ranges/zip_view.h
M libcxx/include/complex
M libcxx/include/module.modulemap.in
M libcxx/include/valarray
A libcxx/test/benchmarks/algorithms/nonmodifying/pstl.find.bench.cpp
A libcxx/test/benchmarks/algorithms/sorting/pstl.sort.bench.cpp
M libcxx/test/benchmarks/containers/associative/associative_container_benchmarks.h
M libcxx/test/benchmarks/containers/string.bench.cpp
A libcxx/test/benchmarks/numeric/pstl.transform_reduce.bench.cpp
M libcxx/test/configs/ibm-libc++-shared.cfg.in
M libcxx/test/libcxx/algorithms/pstl.iterator-requirements.verify.cpp
A libcxx/test/std/algorithms/alg.modifying.operations/alg.swap/pstl.swap_ranges.pass.cpp
M libcxx/test/std/algorithms/pstl.exception_handling.pass.cpp
A libcxx/test/std/numerics/complex.number/complex/complex_requires_cv_unqualified_object.verify.cpp
A libcxx/test/std/numerics/numarray/template.valarray/valarray_requires_cv_unqualified_object.verify.cpp
M libcxx/test/std/time/months.pass.cpp
M libcxx/test/std/time/years.pass.cpp
A libcxx/test/std/utilities/format/format.functions/bug_154670.pass.cpp
M libcxx/utils/ci/docker/linux-builder.dockerfile
R libcxx/utils/ci/images/libcxx_next_runners.txt
R libcxx/utils/ci/images/libcxx_release_runners.txt
R libcxx/utils/ci/images/libcxx_runners.txt
M libcxx/utils/ci/lnt/README.md
M libcxx/utils/ci/lnt/machines.json
M libcxx/utils/ci/lnt/run-benchmarks
A libcxx/utils/ci/lnt/run-libstdcxx-benchmarks
R libcxx/utils/ci/lnt/schema.yaml
A libcxx/utils/ci/lnt/schemas/libcxx.yaml
A libcxx/utils/ci/lnt/schemas/libstdcxx.yaml
M libcxx/utils/ci/run-buildbot
M libcxxabi/src/cxa_personality.cpp
M libsycl/include/sycl/__spirv/spirv_vars.hpp
M libsycl/src/detail/context_impl.cpp
M libsycl/src/detail/device_image_wrapper.cpp
M libsycl/src/detail/device_image_wrapper.hpp
M libsycl/src/detail/offload/offload_utils.hpp
M libsycl/src/detail/queue_impl.cpp
M libsycl/src/handler.cpp
M libsycl/src/usm_functions.cpp
M libsycl/unittests/common/unittests_helper.hpp
M libsycl/unittests/handler/semantics.cpp
M libsycl/unittests/mock/helpers.hpp
M libsycl/unittests/queue/memcpy.cpp
M libsycl/unittests/queue/prefetch.cpp
M libsycl/unittests/queue/queue.cpp
M libsycl/unittests/usm/alloc.cpp
M libunwind/include/unwind_wasm.h
M libunwind/src/Unwind-wasm.c
M lld/test/ELF/lto/riscv-target-abi.ll
M lld/test/ELF/pre_init_fini_array.s
M lld/test/Unit/lit.cfg.py
M lld/test/wasm/check-arch-32-in-64.test
M lld/test/wasm/check-arch-64-in-32.test
M lld/test/wasm/dylink.s
M lld/test/wasm/emit-relocs.s
M lld/test/wasm/locals-duplicate.test
M lld/test/wasm/lto/relocatable-undefined.ll
M lld/test/wasm/pie.s
M lld/test/wasm/relocatable.ll
M lld/test/wasm/rpath.s
M lld/test/wasm/shared-needed.s
M lld/test/wasm/shared-weak-undefined.s
M lld/test/wasm/shared.s
M lld/test/wasm/shared64.s
M lld/test/wasm/signature-mismatch-relocatable.s
M lld/test/wasm/signature-mismatch.s
M lld/test/wasm/stack-pointer.s
M lld/test/wasm/tls-export.s
M lld/test/wasm/weak-alias.s
M lld/unittests/AsLibELF/CMakeLists.txt
M lld/unittests/AsLibELF/OutputStream.cpp
M lld/unittests/AsLibELF/ROCm.cpp
M lld/wasm/InputFiles.cpp
M lld/wasm/SyntheticSections.cpp
M lldb/docs/dil-expr-lang.ebnf
M lldb/examples/python/templates/scripted_process.py
M lldb/include/lldb/API/SBBreakpoint.h
M lldb/include/lldb/Breakpoint/Breakpoint.h
M lldb/include/lldb/Breakpoint/BreakpointLocation.h
M lldb/include/lldb/Breakpoint/StopCondition.h
M lldb/include/lldb/Interpreter/CommandOptionArgumentTable.h
M lldb/include/lldb/Target/Process.h
M lldb/include/lldb/Target/Target.h
M lldb/include/lldb/Utility/StructuredData.h
M lldb/include/lldb/lldb-enumerations.h
M lldb/packages/Python/lldbsuite/test/lldbinline.py
M lldb/packages/Python/lldbsuite/test/lldbplatform.py
M lldb/packages/Python/lldbsuite/test/lldbplatformutil.py
M lldb/packages/Python/lldbsuite/test/lldbtest.py
M lldb/source/API/SBBreakpoint.cpp
M lldb/source/API/SBProcess.cpp
M lldb/source/Breakpoint/Breakpoint.cpp
M lldb/source/Breakpoint/BreakpointLocation.cpp
M lldb/source/Commands/CommandObjectBreakpoint.cpp
M lldb/source/Commands/CommandObjectVersion.cpp
M lldb/source/Commands/Options.td
M lldb/source/Plugins/TypeSystem/CMakeLists.txt
A lldb/source/Plugins/TypeSystem/Clike/CMakeLists.txt
A lldb/source/Plugins/TypeSystem/Clike/TypeSystemClike.cpp
A lldb/source/Plugins/TypeSystem/Clike/TypeSystemClike.h
M lldb/source/Target/Process.cpp
M lldb/source/Target/Target.cpp
M lldb/source/Target/TargetProperties.td
M lldb/source/Utility/StructuredData.cpp
M lldb/source/ValueObject/DILParser.cpp
M lldb/test/API/api/multiple-debuggers/multi-process-driver.cpp
M lldb/test/API/api/multithreaded/common.h
M lldb/test/API/api/multithreaded/test_listener_event_description.cpp
M lldb/test/API/api/multithreaded/test_listener_event_process_state.cpp
M lldb/test/API/api/multithreaded/test_listener_resume.cpp
M lldb/test/API/functionalities/breakpoint/breakpoint_conditions/TestBreakpointConditions.py
M lldb/test/API/functionalities/scripted_frame_provider/pass_through_prefix/TestFrameProviderPassThroughPrefix.py
M lldb/test/API/functionalities/scripted_frame_provider/pass_through_prefix/frame_provider.py
M lldb/test/API/functionalities/scripted_frame_provider/thread_filter/TestFrameProviderThreadFilter.py
M lldb/test/API/python_api/event/TestEvents.py
M lldb/test/API/python_api/process/address-masks/TestAddressMasks.py
M lldb/unittests/ObjectContainer/ObjectContainerClangOffloadBundleTest.cpp
M llvm/cmake/modules/GetLibraryName.cmake
M llvm/docs/CommandLine.md
M llvm/docs/Lexicon.md
M llvm/docs/ORCv2.md
M llvm/docs/SphinxQuickstartTemplate.md
M llvm/examples/Kaleidoscope/MCJIT/cached/genk-timing.py
M llvm/examples/Kaleidoscope/MCJIT/cached/split-lib.py
M llvm/examples/Kaleidoscope/MCJIT/complete/genk-timing.py
M llvm/examples/Kaleidoscope/MCJIT/complete/split-lib.py
M llvm/examples/Kaleidoscope/MCJIT/lazy/genk-timing.py
M llvm/include/llvm-c/DebugInfo.h
M llvm/include/llvm/ADT/DenseMap.h
M llvm/include/llvm/ADT/DenseMapInfo.h
M llvm/include/llvm/Analysis/BranchProbabilityInfo.h
M llvm/include/llvm/Analysis/IVDescriptors.h
M llvm/include/llvm/Analysis/LoopAccessAnalysis.h
M llvm/include/llvm/Analysis/ScalarEvolution.h
M llvm/include/llvm/Analysis/ScalarEvolutionExpressions.h
M llvm/include/llvm/Analysis/ScalarEvolutionPatternMatch.h
M llvm/include/llvm/Analysis/TargetTransformInfo.h
M llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
M llvm/include/llvm/AsmParser/LLParser.h
M llvm/include/llvm/BinaryFormat/Dwarf.def
M llvm/include/llvm/BinaryFormat/Dwarf.h
M llvm/include/llvm/BinaryFormat/ELF.h
M llvm/include/llvm/BinaryFormat/Wasm.h
M llvm/include/llvm/CGData/CodeGenData.h
M llvm/include/llvm/CGData/CodeGenDataReader.h
M llvm/include/llvm/CodeGen/AsmPrinter.h
M llvm/include/llvm/CodeGen/BasicTTIImpl.h
M llvm/include/llvm/CodeGen/SDPatternMatch.h
M llvm/include/llvm/CodeGen/ScheduleDAG.h
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/include/llvm/CodeGen/TargetLoweringObjectFileImpl.h
M llvm/include/llvm/ExecutionEngine/Orc/Core.h
M llvm/include/llvm/ExecutionEngine/Orc/Debugging/PerfSupportPlugin.h
M llvm/include/llvm/ExecutionEngine/Orc/Debugging/VTuneSupportPlugin.h
M llvm/include/llvm/ExecutionEngine/Orc/ExecutorProcessControl.h
M llvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h
M llvm/include/llvm/IR/AutoUpgrade.h
M llvm/include/llvm/IR/IRBuilder.h
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/include/llvm/IR/IntrinsicsDirectX.td
M llvm/include/llvm/IR/IntrinsicsNVVM.td
M llvm/include/llvm/IR/IntrinsicsRISCV.td
M llvm/include/llvm/IR/IntrinsicsSPIRV.td
M llvm/include/llvm/IR/RuntimeLibcalls.td
M llvm/include/llvm/IR/Verifier.h
M llvm/include/llvm/Object/ELFTypes.h
M llvm/include/llvm/ObjectYAML/COFFYAML.h
M llvm/include/llvm/ObjectYAML/WasmYAML.h
M llvm/include/llvm/ProfileData/InstrProf.h
M llvm/include/llvm/ProfileData/SampleProf.h
M llvm/include/llvm/ProfileData/SampleProfWriter.h
M llvm/include/llvm/Support/AArch64MemoryHints.h
M llvm/include/llvm/Support/CommandLine.h
M llvm/include/llvm/Support/Compression.h
M llvm/include/llvm/Target/CGPassBuilderOption.h
M llvm/include/llvm/Target/TargetMachine.h
M llvm/include/llvm/TargetParser/Triple.h
M llvm/include/llvm/Transforms/IPO/InstrumentorUtils.h
M llvm/include/llvm/Transforms/Scalar/GVN.h
A llvm/include/llvm/Transforms/Scalar/GVNHoist.h
A llvm/include/llvm/Transforms/Scalar/GVNSink.h
A llvm/include/llvm/Transforms/Scalar/GVNValueTable.h
M llvm/include/llvm/Transforms/Utils/LoopUtils.h
M llvm/include/llvm/Transforms/Utils/ScalarEvolutionExpander.h
M llvm/include/llvm/Transforms/Vectorize/SLPVectorizer.h
M llvm/lib/Analysis/BasicAliasAnalysis.cpp
M llvm/lib/Analysis/BlockFrequencyInfoImpl.cpp
M llvm/lib/Analysis/BranchProbabilityInfo.cpp
M llvm/lib/Analysis/IVDescriptors.cpp
M llvm/lib/Analysis/LoopAccessAnalysis.cpp
M llvm/lib/Analysis/LoopCacheAnalysis.cpp
M llvm/lib/Analysis/ScalarEvolution.cpp
M llvm/lib/Analysis/ScalarEvolutionDivision.cpp
M llvm/lib/Analysis/TargetTransformInfo.cpp
M llvm/lib/Analysis/TypeBasedAliasAnalysis.cpp
M llvm/lib/Analysis/VectorUtils.cpp
M llvm/lib/AsmParser/LLParser.cpp
M llvm/lib/BinaryFormat/Dwarf.cpp
M llvm/lib/Bitcode/Reader/MetadataLoader.cpp
M llvm/lib/CAS/UnifiedOnDiskCache.cpp
M llvm/lib/CGData/CodeGenData.cpp
M llvm/lib/CGData/CodeGenDataReader.cpp
M llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
M llvm/lib/CodeGen/CodeGenPrepare.cpp
M llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
M llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
M llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp
M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
M llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp
M llvm/lib/CodeGen/MachineBasicBlock.cpp
M llvm/lib/CodeGen/MachinePipeliner.cpp
M llvm/lib/CodeGen/MachineScheduler.cpp
M llvm/lib/CodeGen/MacroFusion.cpp
M llvm/lib/CodeGen/ScheduleDAG.cpp
M llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
M llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/lib/CodeGen/TargetLoweringBase.cpp
M llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
M llvm/lib/CodeGen/TargetPassConfig.cpp
M llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
M llvm/lib/CodeGen/WasmEHPrepare.cpp
M llvm/lib/DebugInfo/PDB/Native/LinePrinter.cpp
M llvm/lib/ExecutionEngine/Orc/Debugging/PerfSupportPlugin.cpp
M llvm/lib/ExecutionEngine/Orc/Debugging/VTuneSupportPlugin.cpp
M llvm/lib/ExecutionEngine/Orc/ELFNixPlatform.cpp
M llvm/lib/ExecutionEngine/Orc/MachOPlatform.cpp
M llvm/lib/Frontend/OpenMP/OMPDescriptors.inc
M llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
M llvm/lib/IR/AutoUpgrade.cpp
M llvm/lib/IR/ConstantRange.cpp
M llvm/lib/IR/Verifier.cpp
M llvm/lib/LTO/LTO.cpp
M llvm/lib/Linker/IRMover.cpp
M llvm/lib/MC/ELFObjectWriter.cpp
M llvm/lib/MC/MCDwarf.cpp
M llvm/lib/MC/WasmObjectWriter.cpp
M llvm/lib/Object/WasmObjectFile.cpp
M llvm/lib/ObjectYAML/COFFEmitter.cpp
M llvm/lib/ObjectYAML/COFFYAML.cpp
M llvm/lib/ObjectYAML/DWARFEmitter.cpp
M llvm/lib/ObjectYAML/WasmEmitter.cpp
M llvm/lib/ObjectYAML/WasmYAML.cpp
M llvm/lib/Passes/CodeGenPassBuilder.cpp
M llvm/lib/Passes/PassBuilder.cpp
M llvm/lib/Passes/PassBuilderPipelines.cpp
M llvm/lib/ProfileData/InstrProf.cpp
M llvm/lib/ProfileData/SampleProfWriter.cpp
M llvm/lib/Support/CMakeLists.txt
M llvm/lib/Support/Compression.cpp
A llvm/lib/Support/DenseMap.cpp
M llvm/lib/Support/StringRef.cpp
M llvm/lib/Support/raw_socket_stream.cpp
M llvm/lib/Target/AArch64/AArch64CodeLayoutOpt.cpp
M llvm/lib/Target/AArch64/AArch64Combine.td
M llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.h
M llvm/lib/Target/AArch64/AArch64PerfectShuffle.h
M llvm/lib/Target/AArch64/AArch64TargetMachine.h
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
M llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
M llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
M llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
M llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
M llvm/lib/Target/AMDGPU/AMDGPULaneMaskUtils.h
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPURewriteAGPRCopyMFMA.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
M llvm/lib/Target/AMDGPU/GCNHazardRecognizer.h
M llvm/lib/Target/AMDGPU/GCNILPSched.cpp
M llvm/lib/Target/AMDGPU/GCNMinRegStrategy.cpp
M llvm/lib/Target/AMDGPU/GCNPreRAAntiHints.cpp
M llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
M llvm/lib/Target/AMDGPU/GCNSubtarget.cpp
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/GCNVOPDUtils.cpp
M llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.h
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.h
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/SIMachineScheduler.cpp
M llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/lib/Target/ARM/ARMAsmPrinter.cpp
M llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
M llvm/lib/Target/ARM/ARMBlockPlacement.cpp
M llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
M llvm/lib/Target/ARM/ARMFixCortexA57AES1742098Pass.cpp
M llvm/lib/Target/ARM/ARMInstructionSelector.cpp
M llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
M llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
M llvm/lib/Target/ARM/ARMTargetMachine.cpp
M llvm/lib/Target/ARM/ARMTargetMachine.h
M llvm/lib/Target/ARM/ARMTargetObjectFile.cpp
M llvm/lib/Target/ARM/ARMTargetObjectFile.h
M llvm/lib/Target/ARM/MVETPAndVPTOptimisationsPass.cpp
M llvm/lib/Target/ARM/MVETailPredUtils.h
M llvm/lib/Target/ARM/Thumb1FrameLowering.cpp
M llvm/lib/Target/ARM/Thumb1InstrInfo.cpp
M llvm/lib/Target/AVR/AVRAsmPrinter.cpp
M llvm/lib/Target/AVR/AVRDevices.td
M llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp
M llvm/lib/Target/AVR/AVRISelLowering.cpp
M llvm/lib/Target/AVR/AVRInstrInfo.cpp
M llvm/lib/Target/AVR/AVRInstrInfo.td
M llvm/lib/Target/AVR/AVRRegisterInfo.cpp
M llvm/lib/Target/AVR/AVRTargetMachine.h
M llvm/lib/Target/AVR/MCTargetDesc/AVRMCAsmInfo.cpp
M llvm/lib/Target/AVR/MCTargetDesc/AVRMCTargetDesc.h
R llvm/lib/Target/AVR/TODO.md
M llvm/lib/Target/DirectX/DXIL.td
M llvm/lib/Target/DirectX/DXILDataScalarization.cpp
M llvm/lib/Target/DirectX/DXILFlattenArrays.cpp
M llvm/lib/Target/DirectX/DXILLegalizePass.cpp
M llvm/lib/Target/DirectX/DXILMemIntrinsics.cpp
M llvm/lib/Target/DirectX/DXILOpBuilder.cpp
M llvm/lib/Target/DirectX/DXILOpLowering.cpp
M llvm/lib/Target/DirectX/DXILShaderFlags.cpp
M llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp
M llvm/lib/Target/Hexagon/HexagonDepInstrInfo.td
M llvm/lib/Target/Hexagon/HexagonTargetMachine.h
M llvm/lib/Target/LoongArch/LoongArchAsmPrinter.cpp
M llvm/lib/Target/LoongArch/LoongArchAsmPrinter.h
M llvm/lib/Target/LoongArch/LoongArchTargetMachine.h
M llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCTargetDesc.cpp
M llvm/lib/Target/M68k/M68kExpandPseudo.cpp
M llvm/lib/Target/M68k/M68kInstrArithmetic.td
M llvm/lib/Target/M68k/M68kInstrData.td
M llvm/lib/Target/M68k/M68kInstrInfo.cpp
M llvm/lib/Target/M68k/M68kInstrInfo.h
M llvm/lib/Target/M68k/M68kTargetObjectFile.cpp
M llvm/lib/Target/M68k/M68kTargetObjectFile.h
M llvm/lib/Target/MSP430/MSP430AsmPrinter.cpp
M llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
M llvm/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp
M llvm/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.h
M llvm/lib/Target/Mips/MipsAsmPrinter.cpp
M llvm/lib/Target/Mips/MipsAsmPrinter.h
M llvm/lib/Target/Mips/MipsBranchExpansion.cpp
M llvm/lib/Target/Mips/MipsCallLowering.cpp
M llvm/lib/Target/Mips/MipsFastISel.cpp
M llvm/lib/Target/Mips/MipsISelLowering.cpp
M llvm/lib/Target/Mips/MipsMSAInstrInfo.td
M llvm/lib/Target/Mips/MipsMachineFunction.cpp
M llvm/lib/Target/Mips/MipsOptimizePICCall.cpp
M llvm/lib/Target/Mips/MipsRegisterInfo.cpp
M llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
M llvm/lib/Target/Mips/MipsSEISelLowering.cpp
M llvm/lib/Target/Mips/MipsSERegisterInfo.cpp
M llvm/lib/Target/Mips/MipsSubtarget.cpp
M llvm/lib/Target/Mips/MipsSubtarget.h
M llvm/lib/Target/Mips/MipsTargetMachine.cpp
M llvm/lib/Target/Mips/MipsTargetMachine.h
M llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
M llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
M llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
M llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.h
M llvm/lib/Target/NVPTX/NVPTXUtilities.h
M llvm/lib/Target/PowerPC/PPC.h
M llvm/lib/Target/PowerPC/PPCTargetMachine.h
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.h
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.h
M llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
M llvm/lib/Target/RISCV/RISCVExpandPseudoPostRA.cpp
M llvm/lib/Target/RISCV/RISCVExpandPseudoPreEmit.cpp
M llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoP.td
M llvm/lib/Target/RISCV/RISCVLoadStoreOptimizer.cpp
M llvm/lib/Target/RISCV/RISCVMachineScheduler.cpp
M llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
M llvm/lib/Target/RISCV/RISCVTargetMachine.h
M llvm/lib/Target/RISCV/RISCVZilsdOptimizer.cpp
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
M llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
M llvm/lib/Target/SPIRV/SPIRVSubtarget.cpp
M llvm/lib/Target/Sparc/SparcISelLowering.cpp
M llvm/lib/Target/SystemZ/SystemZFrameLowering.cpp
M llvm/lib/Target/SystemZ/SystemZHazardRecognizer.cpp
M llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
M llvm/lib/Target/SystemZ/SystemZMachineScheduler.cpp
M llvm/lib/Target/SystemZ/SystemZXPLINKAsmPrinter.cpp
M llvm/lib/Target/VE/VEISelLowering.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
M llvm/lib/Target/X86/GISel/X86LegalizerInfo.cpp
M llvm/lib/Target/X86/X86FastISel.cpp
M llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86InstCombineIntrinsic.cpp
M llvm/lib/Target/X86/X86RegisterInfo.td
M llvm/lib/Target/X86/X86TargetMachine.cpp
M llvm/lib/Target/X86/X86TargetMachine.h
M llvm/lib/Transforms/IPO/FunctionAttrs.cpp
M llvm/lib/Transforms/IPO/Instrumentor.cpp
M llvm/lib/Transforms/IPO/MemProfContextDisambiguation.cpp
M llvm/lib/Transforms/IPO/MergeFunctions.cpp
M llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
M llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
M llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp
M llvm/lib/Transforms/Instrumentation/InstrProfiling.cpp
M llvm/lib/Transforms/Instrumentation/MemProfUse.cpp
M llvm/lib/Transforms/Instrumentation/PGOInstrumentation.cpp
M llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
M llvm/lib/Transforms/Scalar/GVN.cpp
M llvm/lib/Transforms/Scalar/GVNHoist.cpp
M llvm/lib/Transforms/Scalar/GVNSink.cpp
M llvm/lib/Transforms/Scalar/InferAddressSpaces.cpp
M llvm/lib/Transforms/Scalar/JumpTableToSwitch.cpp
M llvm/lib/Transforms/Scalar/LICM.cpp
M llvm/lib/Transforms/Scalar/LoopFuse.cpp
M llvm/lib/Transforms/Scalar/SROA.cpp
M llvm/lib/Transforms/Scalar/TailRecursionElimination.cpp
M llvm/lib/Transforms/Utils/BuildLibCalls.cpp
M llvm/lib/Transforms/Utils/CodeExtractor.cpp
M llvm/lib/Transforms/Utils/LoopUnroll.cpp
M llvm/lib/Transforms/Utils/LoopUtils.cpp
M llvm/lib/Transforms/Utils/ScalarEvolutionExpander.cpp
M llvm/lib/Transforms/Utils/SimplifyCFG.cpp
M llvm/lib/Transforms/Utils/SimplifyLibCalls.cpp
M llvm/lib/Transforms/Vectorize/LoopIdiomVectorize.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPCompatibilityAnalysis.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPShuffleAnalysis.h
M llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPUtils.cpp
M llvm/lib/Transforms/Vectorize/VPlan.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
M llvm/lib/Transforms/Vectorize/VPlanHelpers.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.h
M llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
M llvm/lib/Transforms/Vectorize/VPlanUtils.h
M llvm/lib/Transforms/Vectorize/VPlanVerifier.cpp
M llvm/lib/Transforms/Vectorize/VectorCombine.cpp
M llvm/runtimes/CMakeLists.txt
A llvm/test/Analysis/BlockFrequencyInfo/many-successors-order.ll
M llvm/test/Analysis/CostModel/AArch64/cast.ll
M llvm/test/Analysis/CostModel/AArch64/clmul-fixed.ll
M llvm/test/Analysis/CostModel/AArch64/clmul-scalable.ll
M llvm/test/Analysis/CostModel/AArch64/speculative-load.ll
M llvm/test/Analysis/CostModel/AArch64/sve-cast.ll
M llvm/test/Analysis/CostModel/X86/arith-fp.ll
M llvm/test/Analysis/CostModel/X86/clmul.ll
M llvm/test/Analysis/CostModel/X86/speculative-load.ll
A llvm/test/Analysis/ScalarEvolution/trip-count-variable-stride-predicate.ll
M llvm/test/Assembler/auto_upgrade_nvvm_intrinsics.ll
A llvm/test/Assembler/invalid-diexpression-arg-negative.ll
A llvm/test/Bitcode/upgrade-tbaa-struct.ll
A llvm/test/Bitcode/upgrade-tbaa-struct.ll.bc
M llvm/test/Bitcode/upgrade-tbaa.ll
A llvm/test/Bitcode/upgrade-tbaa.ll.bc
M llvm/test/CodeGen/AArch64/GlobalISel/arm64-callingconv-ios.ll
M llvm/test/CodeGen/AArch64/GlobalISel/arm64-callingconv.ll
M llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-switch.ll
M llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
M llvm/test/CodeGen/AArch64/GlobalISel/arm64-this-return.ll
M llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-alias.ll
M llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-ifunc.ll
M llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-signext.ll
M llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-sret-demotion.ll
M llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-vectors.ll
M llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-zeroext.ll
M llvm/test/CodeGen/AArch64/GlobalISel/call-translator-tail-call-sret.ll
M llvm/test/CodeGen/AArch64/GlobalISel/call-translator-tail-call-weak.ll
M llvm/test/CodeGen/AArch64/GlobalISel/call-translator-tail-call.ll
M llvm/test/CodeGen/AArch64/GlobalISel/call-translator.ll
M llvm/test/CodeGen/AArch64/GlobalISel/combiner-load-store-indexing.ll
M llvm/test/CodeGen/AArch64/GlobalISel/integration-shuffle-vector.ll
M llvm/test/CodeGen/AArch64/GlobalISel/invoke-region.ll
M llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-arguments.ll
M llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-delayed-stack-protector.ll
M llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-exceptions.ll
M llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-hoisted-constants.ll
M llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-inline-asm.ll
M llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-localescape.ll
M llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-stack-protector-trap-unreachable.ll
M llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-unreachable.ll
M llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-unwind-inline-asm.ll
A llvm/test/CodeGen/AArch64/GlobalISel/knownbits-freeze.mir
M llvm/test/CodeGen/AArch64/GlobalISel/knownfpclass-ops.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-atan2.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-bzero.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-exceptions.ll
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-exp.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-fexp2.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-fmaxnum.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-fminnum.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-fpenv.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-fpmode.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-memcpy-et-al.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-memlib-debug-loc.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-modf.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-pow.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-rem.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-s128-div.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-sin.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-sinh.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-undef.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-sadde.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-saddo.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-ssube.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-ssubo.mir
A llvm/test/CodeGen/AArch64/GlobalISel/select-tls-macho.ll
M llvm/test/CodeGen/AArch64/GlobalISel/select-uadde.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-uaddo.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-usube.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-usubo.mir
M llvm/test/CodeGen/AArch64/O3-pipeline.ll
M llvm/test/CodeGen/AArch64/aarch64-sme2-asm.ll
M llvm/test/CodeGen/AArch64/aarch64-za-clobber.ll
M llvm/test/CodeGen/AArch64/add.ll
M llvm/test/CodeGen/AArch64/andorxor.ll
M llvm/test/CodeGen/AArch64/arm64-rev.ll
M llvm/test/CodeGen/AArch64/arm64-storebytesmerge.ll
M llvm/test/CodeGen/AArch64/binopshuffles.ll
M llvm/test/CodeGen/AArch64/bitcast.ll
M llvm/test/CodeGen/AArch64/clmul-scalable.ll
M llvm/test/CodeGen/AArch64/clmul.ll
M llvm/test/CodeGen/AArch64/coalescer-empty-subrange-early-lis.ll
M llvm/test/CodeGen/AArch64/ctlz.ll
M llvm/test/CodeGen/AArch64/ctpop.ll
M llvm/test/CodeGen/AArch64/cttz.ll
M llvm/test/CodeGen/AArch64/fp-intrinsics-vector.ll
M llvm/test/CodeGen/AArch64/itofp-bf16.ll
M llvm/test/CodeGen/AArch64/ldexp.ll
M llvm/test/CodeGen/AArch64/ldst-opt.ll
M llvm/test/CodeGen/AArch64/lowmaskedlanes.ll
M llvm/test/CodeGen/AArch64/mul.ll
M llvm/test/CodeGen/AArch64/named-vector-shuffle-reverse-sve.ll
M llvm/test/CodeGen/AArch64/neon-rshrn.ll
M llvm/test/CodeGen/AArch64/neon-truncstore.ll
M llvm/test/CodeGen/AArch64/pr161420.ll
M llvm/test/CodeGen/AArch64/sadd_sat_vec.ll
M llvm/test/CodeGen/AArch64/shufflevector.ll
M llvm/test/CodeGen/AArch64/ssub_sat_vec.ll
M llvm/test/CodeGen/AArch64/store.ll
M llvm/test/CodeGen/AArch64/sub.ll
M llvm/test/CodeGen/AArch64/sve-extract-vector-to-predicate-store.ll
A llvm/test/CodeGen/AArch64/sve-fixed-length-shuffle-reverse.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-trunc.ll
M llvm/test/CodeGen/AArch64/uadd_sat_vec.ll
M llvm/test/CodeGen/AArch64/usub_sat_vec.ll
M llvm/test/CodeGen/AArch64/vec3-loads-ext-trunc-stores.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/dereferenceable-declaration.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/dropped_debug_info_assert.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-assert-align.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-abi-attribute-hints.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-implicit-args.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-non-fixed.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-return-values.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-sret.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-indirect-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-inline-asm.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-sibling-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/twoaddr-extract-dyn-v7f64.mir
M llvm/test/CodeGen/AMDGPU/a-v-flat-atomic-cmpxchg.ll
M llvm/test/CodeGen/AMDGPU/acc-ldst.ll
M llvm/test/CodeGen/AMDGPU/add_i128.ll
M llvm/test/CodeGen/AMDGPU/add_i64.ll
M llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.160bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.224bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.288bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.32bit.ll
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M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.384bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.448bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.48bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.576bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.640bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.64bit.ll
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M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll
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M llvm/test/CodeGen/AMDGPU/amdgpu-mul24-knownbits.ll
M llvm/test/CodeGen/AMDGPU/and.ll
M llvm/test/CodeGen/AMDGPU/any_extend_vector_inreg.ll
M llvm/test/CodeGen/AMDGPU/anyext.ll
M llvm/test/CodeGen/AMDGPU/asyncmark-gfx12plus.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomicrmw_usub_sat.ll
M llvm/test/CodeGen/AMDGPU/atomics-system-scope.ll
M llvm/test/CodeGen/AMDGPU/av-split-dead-valno-crash.ll
M llvm/test/CodeGen/AMDGPU/bf16-conversions.ll
M llvm/test/CodeGen/AMDGPU/bf16.ll
M llvm/test/CodeGen/AMDGPU/bitcast-vector-extract.ll
M llvm/test/CodeGen/AMDGPU/bitinsert-bitextract-fp.ll
M llvm/test/CodeGen/AMDGPU/bitinsert-bitextract.ll
M llvm/test/CodeGen/AMDGPU/bitreverse.ll
M llvm/test/CodeGen/AMDGPU/branch-folding-implicit-def-subreg.ll
M llvm/test/CodeGen/AMDGPU/bswap.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointers-memcpy.ll
M llvm/test/CodeGen/AMDGPU/bypass-div.ll
M llvm/test/CodeGen/AMDGPU/call-c-function.ll
M llvm/test/CodeGen/AMDGPU/call-constant.ll
M llvm/test/CodeGen/AMDGPU/call-defs-mode-register.ll
M llvm/test/CodeGen/AMDGPU/clmul.ll
M llvm/test/CodeGen/AMDGPU/coexec-sched-flavor-classification.mir
M llvm/test/CodeGen/AMDGPU/consecutive-loads-in-branch.ll
M llvm/test/CodeGen/AMDGPU/copy-illegal-type.ll
M llvm/test/CodeGen/AMDGPU/copy-to-reg-scc-clobber.ll
M llvm/test/CodeGen/AMDGPU/ctlz.ll
M llvm/test/CodeGen/AMDGPU/ctlz_zero_poison.ll
M llvm/test/CodeGen/AMDGPU/ctpop.ll
M llvm/test/CodeGen/AMDGPU/ctpop16.ll
M llvm/test/CodeGen/AMDGPU/ctpop64.ll
M llvm/test/CodeGen/AMDGPU/cttz.ll
M llvm/test/CodeGen/AMDGPU/cttz_zero_poison.ll
M llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
M llvm/test/CodeGen/AMDGPU/dead-lane.mir
M llvm/test/CodeGen/AMDGPU/div_v2i128.ll
M llvm/test/CodeGen/AMDGPU/ds_gws_align.ll
M llvm/test/CodeGen/AMDGPU/dvgpr-vgpr-count-propagation-direct-chain.ll
M llvm/test/CodeGen/AMDGPU/dvgpr-vgpr-count-propagation.ll
A llvm/test/CodeGen/AMDGPU/dynamic-vgpr-entry-register-pressure.ll
A llvm/test/CodeGen/AMDGPU/dynamic-vgpr-entry-vgpr-limit.ll
M llvm/test/CodeGen/AMDGPU/dynamic-vgpr-reserve-stack-for-cwsr.ll
M llvm/test/CodeGen/AMDGPU/extract-subvector-16bit.ll
M llvm/test/CodeGen/AMDGPU/fadd.f16.ll
M llvm/test/CodeGen/AMDGPU/fceil64.ll
M llvm/test/CodeGen/AMDGPU/fcmp.f16.ll
M llvm/test/CodeGen/AMDGPU/fcopysign.bf16.ll
A llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-scc-cmp-wave32.mir
A llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-scc-cmp.mir
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64_noprivate.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system.ll
M llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp-fp8-hw.ll
M llvm/test/CodeGen/AMDGPU/fmax_legacy.f64.ll
M llvm/test/CodeGen/AMDGPU/fmin_legacy.f64.ll
M llvm/test/CodeGen/AMDGPU/fmul.f16.ll
M llvm/test/CodeGen/AMDGPU/fnearbyint.ll
M llvm/test/CodeGen/AMDGPU/fneg-combines.new.ll
M llvm/test/CodeGen/AMDGPU/fneg-modifier-casting.ll
M llvm/test/CodeGen/AMDGPU/fp-classify.ll
M llvm/test/CodeGen/AMDGPU/fp_to_sint.ll
M llvm/test/CodeGen/AMDGPU/fp_to_uint.ll
M llvm/test/CodeGen/AMDGPU/fpow.ll
M llvm/test/CodeGen/AMDGPU/fptoi.i128.ll
M llvm/test/CodeGen/AMDGPU/fptosi-sat-scalar.ll
M llvm/test/CodeGen/AMDGPU/fptosi.f16.ll
M llvm/test/CodeGen/AMDGPU/fptoui.f16.ll
M llvm/test/CodeGen/AMDGPU/fptrunc.ll
M llvm/test/CodeGen/AMDGPU/freeze.ll
M llvm/test/CodeGen/AMDGPU/frem.ll
M llvm/test/CodeGen/AMDGPU/fshl.ll
M llvm/test/CodeGen/AMDGPU/fsqrt.f64.ll
M llvm/test/CodeGen/AMDGPU/fsub.f16.ll
M llvm/test/CodeGen/AMDGPU/gfx-callable-return-types.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/global-load-xcnt.ll
M llvm/test/CodeGen/AMDGPU/half.ll
M llvm/test/CodeGen/AMDGPU/hsa-metadata-kernel-code-props.ll
M llvm/test/CodeGen/AMDGPU/identical-subrange-spill-infloop.ll
M llvm/test/CodeGen/AMDGPU/idot2.ll
M llvm/test/CodeGen/AMDGPU/idot4s.ll
M llvm/test/CodeGen/AMDGPU/idot4u.ll
M llvm/test/CodeGen/AMDGPU/idot8u.ll
M llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll
M llvm/test/CodeGen/AMDGPU/indirect-call.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_elt.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll
M llvm/test/CodeGen/AMDGPU/invalid-addrspacecast.ll
M llvm/test/CodeGen/AMDGPU/irtranslator-whole-wave-functions.ll
M llvm/test/CodeGen/AMDGPU/isel-amdgpu-cs-chain-cc.ll
M llvm/test/CodeGen/AMDGPU/isel-whole-wave-functions.ll
M llvm/test/CodeGen/AMDGPU/lds-misaligned-bug.ll
M llvm/test/CodeGen/AMDGPU/licm-wwm.mir
M llvm/test/CodeGen/AMDGPU/literal64.ll
M llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll
M llvm/test/CodeGen/AMDGPU/llc-pipeline.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.class.f16.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scale.pk32.gfx13.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dual_intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.atomic.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.dim.gfx90a.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.dim.gfx90a.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.scale.f32.32x32x64.f8f6f4.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fadd.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fsub.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.set.inactive.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.smfmac.gfx950.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp10.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp10.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp2.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp2.ll
M llvm/test/CodeGen/AMDGPU/llvm.fma.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.ll
M llvm/test/CodeGen/AMDGPU/llvm.log.ll
M llvm/test/CodeGen/AMDGPU/llvm.log10.ll
M llvm/test/CodeGen/AMDGPU/llvm.log2.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.maxnum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.minimum.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.minnum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.round.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.round.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i16.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i32.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i64.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i8.ll
M llvm/test/CodeGen/AMDGPU/load-global-f32.ll
M llvm/test/CodeGen/AMDGPU/load-global-i16.ll
M llvm/test/CodeGen/AMDGPU/load-global-i32.ll
M llvm/test/CodeGen/AMDGPU/load-global-i8.ll
M llvm/test/CodeGen/AMDGPU/load-local-i16.ll
M llvm/test/CodeGen/AMDGPU/lower-control-flow-live-variables-update.mir
M llvm/test/CodeGen/AMDGPU/lower-ctor-dtor.ll
M llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-pal.ll
M llvm/test/CodeGen/AMDGPU/machine-sink-temporal-divergence-swdev407790.ll
M llvm/test/CodeGen/AMDGPU/mad-combine.ll
M llvm/test/CodeGen/AMDGPU/mad_uint24.ll
M llvm/test/CodeGen/AMDGPU/mai-hazards-gfx90a.mir
M llvm/test/CodeGen/AMDGPU/mai-hazards-gfx942.mir
M llvm/test/CodeGen/AMDGPU/max.ll
M llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll
M llvm/test/CodeGen/AMDGPU/merge-stores.ll
M llvm/test/CodeGen/AMDGPU/mfma-cd-select.ll
M llvm/test/CodeGen/AMDGPU/mfma-no-register-aliasing.ll
M llvm/test/CodeGen/AMDGPU/min.ll
M llvm/test/CodeGen/AMDGPU/mixed-vmem-types.ll
M llvm/test/CodeGen/AMDGPU/mmra.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-atomicrmw-system.ll
M llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands-non-ptr-intrinsics.ll
M llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands.ll
M llvm/test/CodeGen/AMDGPU/mul.ll
M llvm/test/CodeGen/AMDGPU/mul_uint24-amdgcn.ll
M llvm/test/CodeGen/AMDGPU/no-remat-indirect-mov.mir
M llvm/test/CodeGen/AMDGPU/operand-folding.ll
M llvm/test/CodeGen/AMDGPU/or.ll
M llvm/test/CodeGen/AMDGPU/packed-fp32.ll
M llvm/test/CodeGen/AMDGPU/packed-fp64.ll
M llvm/test/CodeGen/AMDGPU/packed-u64.ll
A llvm/test/CodeGen/AMDGPU/phi-elimination-split-critical-edge-subranges.mir
M llvm/test/CodeGen/AMDGPU/promote-alloca-vgpr-ratio.ll
M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll
M llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.ll
M llvm/test/CodeGen/AMDGPU/rewrite-mfma-single-exit-copy.ll
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-reserved-wwm-vgpr.ll
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-spill-joint-dom.ll
A llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-spill-multi-store-codegen.ll
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-spill-multi-store.ll
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr.ll
M llvm/test/CodeGen/AMDGPU/rsq.f64.ll
M llvm/test/CodeGen/AMDGPU/saddo.ll
M llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll
M llvm/test/CodeGen/AMDGPU/schedule-relaxed-occupancy.ll
M llvm/test/CodeGen/AMDGPU/scmp.ll
M llvm/test/CodeGen/AMDGPU/scratch-simple.ll
M llvm/test/CodeGen/AMDGPU/sdiv.ll
M llvm/test/CodeGen/AMDGPU/select.f16.ll
M llvm/test/CodeGen/AMDGPU/setcc-f64-hi32mask.ll
M llvm/test/CodeGen/AMDGPU/shift-and-i64-ubfe.ll
M llvm/test/CodeGen/AMDGPU/shl.ll
M llvm/test/CodeGen/AMDGPU/shl.v2i64.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll
M llvm/test/CodeGen/AMDGPU/si-init-whole-wave.mir
M llvm/test/CodeGen/AMDGPU/sint_to_fp.i64.ll
M llvm/test/CodeGen/AMDGPU/sminmax.v2i16.ll
M llvm/test/CodeGen/AMDGPU/spill-scavenge-offset.ll
M llvm/test/CodeGen/AMDGPU/spill-vgpr.ll
M llvm/test/CodeGen/AMDGPU/splitkit-getsubrangeformask-phi-extend.ll
M llvm/test/CodeGen/AMDGPU/sra.ll
M llvm/test/CodeGen/AMDGPU/srem.ll
M llvm/test/CodeGen/AMDGPU/srl.ll
M llvm/test/CodeGen/AMDGPU/ssubo.ll
M llvm/test/CodeGen/AMDGPU/sub.ll
M llvm/test/CodeGen/AMDGPU/twoaddr-constrain.ll
M llvm/test/CodeGen/AMDGPU/ucmp.ll
M llvm/test/CodeGen/AMDGPU/udiv.ll
M llvm/test/CodeGen/AMDGPU/uint_to_fp.i64.ll
M llvm/test/CodeGen/AMDGPU/umin-sub-to-usubo-select-combine.ll
M llvm/test/CodeGen/AMDGPU/undef-handling-crash-in-ra.ll
M llvm/test/CodeGen/AMDGPU/undefined-subreg-liverange.ll
M llvm/test/CodeGen/AMDGPU/unspill-vgpr-after-rewrite-vgpr-mfma.ll
M llvm/test/CodeGen/AMDGPU/urem64.ll
M llvm/test/CodeGen/AMDGPU/v_madak_f16.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fmaximum.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fminimum.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-smax.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-smin.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-umax.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-umin.ll
M llvm/test/CodeGen/AMDGPU/vgpr-mark-last-scratch-load.ll
M llvm/test/CodeGen/AMDGPU/vni8-across-blocks.ll
M llvm/test/CodeGen/AMDGPU/vselect.ll
M llvm/test/CodeGen/AMDGPU/waitcnt-loop-ds-prefetch-pattern.ll
M llvm/test/CodeGen/AMDGPU/wave32.ll
M llvm/test/CodeGen/AMDGPU/widen-vselect-and-mask.ll
M llvm/test/CodeGen/AMDGPU/wqm-debug-instr-terminator.mir
M llvm/test/CodeGen/AMDGPU/wqm-debug-instr.mir
M llvm/test/CodeGen/AMDGPU/wqm-propagate-for-execz-side-effect.mir
M llvm/test/CodeGen/AMDGPU/wqm-terminators.mir
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M llvm/test/CodeGen/AMDGPU/wqm.mir
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M llvm/test/CodeGen/ARM/O3-pipeline.ll
M llvm/test/CodeGen/ARM/fp-intrinsics-vector.ll
M llvm/test/CodeGen/ARM/inlineasm-operand-implicit-cast.ll
M llvm/test/CodeGen/ARM/llvm.modf.ll
M llvm/test/CodeGen/ARM/llvm.sincos.ll
A llvm/test/CodeGen/ARM/load_store_opt_eraseliveregs.mir
M llvm/test/CodeGen/ARM/module-target-abi.ll
M llvm/test/CodeGen/ARM/signext-inreg.ll
M llvm/test/CodeGen/ARM/vldlane.ll
M llvm/test/CodeGen/DirectX/LoadInput.ll
A llvm/test/CodeGen/DirectX/LongVector/wave-readlane-first.ll
M llvm/test/CodeGen/DirectX/ShaderFlags/wave-ops.ll
M llvm/test/CodeGen/DirectX/StoreOutput.ll
A llvm/test/CodeGen/DirectX/WaveReadLaneFirst.ll
A llvm/test/CodeGen/DirectX/WaveReadLaneFirst_mat.ll
M llvm/test/CodeGen/DirectX/bugfix_150050_data_scalarize_const_gep.ll
M llvm/test/CodeGen/DirectX/flatten-array.ll
M llvm/test/CodeGen/DirectX/flatten-bug-117273.ll
M llvm/test/CodeGen/DirectX/legalize-i8.ll
M llvm/test/CodeGen/DirectX/llc-vector-load-scalarize.ll
M llvm/test/CodeGen/DirectX/scalar-store.ll
M llvm/test/CodeGen/DirectX/scalarize-static-array-of-float-vectors.ll
M llvm/test/CodeGen/Hexagon/addh.ll
M llvm/test/CodeGen/Hexagon/cttz-elts-widen.ll
M llvm/test/CodeGen/Hexagon/isel-extload-i1.ll
M llvm/test/CodeGen/Hexagon/live-vars/live-outs.ll
M llvm/test/CodeGen/Hexagon/mulhs.ll
M llvm/test/CodeGen/Hexagon/swp-vect-dotprod.ll
A llvm/test/CodeGen/LoongArch/module-target-abi.ll
A llvm/test/CodeGen/LoongArch/null-streamer.ll
M llvm/test/CodeGen/LoongArch/opt-pipeline.ll
M llvm/test/CodeGen/M68k/Arith/divide-by-constant.ll
M llvm/test/CodeGen/M68k/Arith/smul-with-overflow.ll
M llvm/test/CodeGen/M68k/Arith/umul-with-overflow.ll
M llvm/test/CodeGen/M68k/Bits/btst.ll
M llvm/test/CodeGen/M68k/Control/cmp.ll
M llvm/test/CodeGen/M68k/Control/non-cmov-switch.ll
M llvm/test/CodeGen/M68k/Control/setcc.ll
M llvm/test/CodeGen/M68k/Data/load-extend.ll
M llvm/test/CodeGen/M68k/Data/sext-i1.ll
M llvm/test/CodeGen/M68k/pipeline.ll
M llvm/test/CodeGen/M68k/register-spills.ll
A llvm/test/CodeGen/Mips/Fast-ISel/mul-dead-hilo.ll
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M llvm/test/CodeGen/Mips/GlobalISel/irtranslator/extend_args.ll
M llvm/test/CodeGen/Mips/GlobalISel/irtranslator/float_args.ll
M llvm/test/CodeGen/Mips/GlobalISel/irtranslator/global_address.ll
M llvm/test/CodeGen/Mips/GlobalISel/irtranslator/global_address_pic.ll
M llvm/test/CodeGen/Mips/GlobalISel/irtranslator/sret_pointer.ll
M llvm/test/CodeGen/Mips/GlobalISel/irtranslator/stack_args.ll
M llvm/test/CodeGen/Mips/GlobalISel/irtranslator/var_arg.ll
M llvm/test/CodeGen/Mips/GlobalISel/legalizer/ceil_and_floor.mir
M llvm/test/CodeGen/Mips/GlobalISel/legalizer/dyn_stackalloc.mir
M llvm/test/CodeGen/Mips/GlobalISel/legalizer/fptosi_and_fptoui.mir
M llvm/test/CodeGen/Mips/GlobalISel/legalizer/rem_and_div.mir
M llvm/test/CodeGen/Mips/GlobalISel/legalizer/sitofp_and_uitofp.mir
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M llvm/test/CodeGen/Mips/msa/bitcast.ll
A llvm/test/CodeGen/Mips/msa/f16vec-shuffle.ll
A llvm/test/CodeGen/Mips/optimize-pic-call-dead-gp.ll
A llvm/test/CodeGen/Mips/target-abi-module-flag.ll
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M llvm/test/CodeGen/NVPTX/callchain.ll
A llvm/test/CodeGen/NVPTX/convert-fp4-pzo.ll
M llvm/test/CodeGen/NVPTX/empty-type.ll
M llvm/test/CodeGen/NVPTX/forward-ld-param.ll
A llvm/test/CodeGen/NVPTX/fp-global.ll
M llvm/test/CodeGen/NVPTX/i1-param.ll
A llvm/test/CodeGen/NVPTX/infer-volatile-address-spaces.ll
M llvm/test/CodeGen/NVPTX/local-stack-frame.ll
M llvm/test/CodeGen/NVPTX/lower-byval-args.ll
M llvm/test/CodeGen/NVPTX/managed.ll
M llvm/test/CodeGen/NVPTX/mulhi-intrins.ll
M llvm/test/CodeGen/NVPTX/noreturn.ll
A llvm/test/CodeGen/NVPTX/odd-integer-width.ll
M llvm/test/CodeGen/NVPTX/param-align.ll
A llvm/test/CodeGen/NVPTX/ptr-global.ll
M llvm/test/CodeGen/NVPTX/vector-global.ll
M llvm/test/CodeGen/PowerPC/O3-pipeline.ll
M llvm/test/CodeGen/PowerPC/clmul-vector.ll
M llvm/test/CodeGen/PowerPC/dmr-copy.ll
M llvm/test/CodeGen/PowerPC/dmr-enable.ll
M llvm/test/CodeGen/PowerPC/no-rlwimi-trivial-commute.mir
M llvm/test/CodeGen/PowerPC/pr47155-47156.ll
M llvm/test/CodeGen/RISCV/GlobalISel/irtranslator-inline-asm.ll
M llvm/test/CodeGen/RISCV/O3-newpm-pipeline.ll
M llvm/test/CodeGen/RISCV/O3-pipeline.ll
M llvm/test/CodeGen/RISCV/clmul.ll
M llvm/test/CodeGen/RISCV/clmulh.ll
M llvm/test/CodeGen/RISCV/clmulr.ll
M llvm/test/CodeGen/RISCV/module-asm-features.ll
M llvm/test/CodeGen/RISCV/riscv-func-target-feature.ll
M llvm/test/CodeGen/RISCV/rvp-simd-32.ll
A llvm/test/CodeGen/RISCV/rvp-widening-shift.ll
M llvm/test/CodeGen/RISCV/rvv/clmul-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/clmulh-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-clmul.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-clmulh.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-subvector.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll
M llvm/test/CodeGen/RISCV/rvv/fmaximum-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fminimum-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/trunc-select-to-max-usat.ll
M llvm/test/CodeGen/RISCV/rvv/vfmsub-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vwadd.w.ll
M llvm/test/CodeGen/SPIRV/cbuffer_global_elim.ll
M llvm/test/CodeGen/SPIRV/debug-info/debug-value-typedef-cycle.ll
A llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_long_vector/wave-readlane-first.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_abort/debugtrap-not-translated.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_abort/trap-ext-disabled.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_bit_instructions_remove_cap_if.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_non_semantic_info/preserve-gv-attributes.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_non_semantic_info/preserve-gv-metadata.ll
M llvm/test/CodeGen/SPIRV/get-global-id-non-integer-dim.ll
A llvm/test/CodeGen/SPIRV/hlsl-intrinsics/WaveReadLaneFirst.ll
A llvm/test/CodeGen/SPIRV/hlsl-intrinsics/WaveReadLaneFirst_mat.ll
M llvm/test/CodeGen/SPIRV/legalization/signed-narrow-int.ll
M llvm/test/CodeGen/SPIRV/linkage/available-externally-global.ll
M llvm/test/CodeGen/SPIRV/llvm-intrinsics/ldexp.ll
M llvm/test/CodeGen/SPIRV/malformed-mangled-builtin-name.ll
M llvm/test/CodeGen/SPIRV/transcoding/enqueue_kernel.ll
M llvm/test/CodeGen/SPIRV/vk-pushconstant-layout.ll
M llvm/test/CodeGen/SystemZ/atomicrmw-ops-i128.ll
M llvm/test/CodeGen/SystemZ/atomicrmw-xchg-07.ll
M llvm/test/CodeGen/SystemZ/rot-02.ll
M llvm/test/CodeGen/SystemZ/subregliveness-01.ll
A llvm/test/CodeGen/SystemZ/zos-frame-callee-saved.ll
M llvm/test/CodeGen/SystemZ/zos-frameaddr.ll
M llvm/test/CodeGen/SystemZ/zos-ret-addr.ll
M llvm/test/CodeGen/Thumb/emergency-spill-slot.ll
M llvm/test/CodeGen/Thumb2/mve-clmul.ll
M llvm/test/CodeGen/Thumb2/mve-complex-deinterleaving-f64-add.ll
M llvm/test/CodeGen/Thumb2/mve-complex-deinterleaving-f64-mul.ll
M llvm/test/CodeGen/Thumb2/mve-complex-deinterleaving-mixed-cases.ll
M llvm/test/CodeGen/Thumb2/mve-complex-deinterleaving-uniform-cases.ll
M llvm/test/CodeGen/Thumb2/mve-ctlz.ll
M llvm/test/CodeGen/Thumb2/mve-fmath.ll
M llvm/test/CodeGen/Thumb2/mve-insertshuffleload.ll
M llvm/test/CodeGen/Thumb2/mve-laneinterleaving-cost.ll
M llvm/test/CodeGen/Thumb2/mve-laneinterleaving.ll
M llvm/test/CodeGen/Thumb2/mve-multivec-spill.ll
M llvm/test/CodeGen/Thumb2/mve-pred-shuffle.ll
M llvm/test/CodeGen/Thumb2/mve-saturating-arith.ll
M llvm/test/CodeGen/Thumb2/mve-sext-masked-load.ll
M llvm/test/CodeGen/Thumb2/mve-shuffle-fp16.ll
M llvm/test/CodeGen/Thumb2/mve-shuffle.ll
M llvm/test/CodeGen/Thumb2/mve-shuffleext.ll
M llvm/test/CodeGen/Thumb2/mve-shufflemov.ll
M llvm/test/CodeGen/Thumb2/mve-vabdus.ll
M llvm/test/CodeGen/Thumb2/mve-vcvt16.ll
M llvm/test/CodeGen/Thumb2/mve-vld2.ll
M llvm/test/CodeGen/Thumb2/mve-vld3.ll
M llvm/test/CodeGen/Thumb2/mve-vld4-post.ll
M llvm/test/CodeGen/Thumb2/mve-vld4.ll
M llvm/test/CodeGen/Thumb2/mve-vldst4.ll
M llvm/test/CodeGen/Thumb2/mve-vst2.ll
M llvm/test/CodeGen/Thumb2/mve-vst3.ll
M llvm/test/CodeGen/Thumb2/mve-vst4-post.ll
M llvm/test/CodeGen/Thumb2/mve-vst4.ll
M llvm/test/CodeGen/Thumb2/mve-zext-masked-load.ll
M llvm/test/CodeGen/WebAssembly/eh-lsda.ll
M llvm/test/CodeGen/WebAssembly/exception-legacy.ll
M llvm/test/CodeGen/WebAssembly/exception.ll
M llvm/test/CodeGen/WebAssembly/profile.ll
M llvm/test/CodeGen/WebAssembly/wasm-eh-prepare.ll
M llvm/test/CodeGen/X86/active_lane_mask.ll
M llvm/test/CodeGen/X86/addcarry.ll
A llvm/test/CodeGen/X86/apx/bls-egpr.ll
A llvm/test/CodeGen/X86/apx/ccmp-flag-source.ll
M llvm/test/CodeGen/X86/apx/mul-i1024.ll
M llvm/test/CodeGen/X86/apx/pr191368.ll
M llvm/test/CodeGen/X86/apx/push2-pop2.ll
M llvm/test/CodeGen/X86/bit-manip-i512.ll
M llvm/test/CodeGen/X86/bitselect.ll
A llvm/test/CodeGen/X86/bzhi-standalone-mask.ll
M llvm/test/CodeGen/X86/cfi-xmm.ll
M llvm/test/CodeGen/X86/clmul-vector-256.ll
M llvm/test/CodeGen/X86/clmul-vector-512.ll
M llvm/test/CodeGen/X86/clmul-vector.ll
M llvm/test/CodeGen/X86/clmul.ll
M llvm/test/CodeGen/X86/cmp-shiftX-maskX.ll
A llvm/test/CodeGen/X86/cmp-shrink-unsigned.ll
M llvm/test/CodeGen/X86/combine-bitselect.ll
M llvm/test/CodeGen/X86/combine-or.ll
M llvm/test/CodeGen/X86/combine-rotates.ll
M llvm/test/CodeGen/X86/div-rem-pair-recomposition-unsigned.ll
A llvm/test/CodeGen/X86/fast-isel-divrem-dead-defs.ll
A llvm/test/CodeGen/X86/fast-isel-sext-dead-eflags.ll
A llvm/test/CodeGen/X86/fast-isel-shift.ll
M llvm/test/CodeGen/X86/fp-intrinsics-flags.ll
M llvm/test/CodeGen/X86/fpclamptosat_vec.ll
A llvm/test/CodeGen/X86/fpcw-dead-eflags.ll
M llvm/test/CodeGen/X86/ftrunc.ll
M llvm/test/CodeGen/X86/funnel-shift-i512.ll
M llvm/test/CodeGen/X86/half.ll
M llvm/test/CodeGen/X86/i128-udiv.ll
M llvm/test/CodeGen/X86/icmp-abs-C.ll
M llvm/test/CodeGen/X86/inline-asm-A-constraint.ll
M llvm/test/CodeGen/X86/inline-asm-avx512f-x-constraint.ll
M llvm/test/CodeGen/X86/inline-asm-default-clobbers.ll
M llvm/test/CodeGen/X86/ldexp-avx512.ll
M llvm/test/CodeGen/X86/ldexp.ll
M llvm/test/CodeGen/X86/llc-pipeline-npm.ll
M llvm/test/CodeGen/X86/llvm.frexp.ll
M llvm/test/CodeGen/X86/machine-combiner-int-vec.ll
M llvm/test/CodeGen/X86/machine-cse.ll
M llvm/test/CodeGen/X86/masked-urem.ll
M llvm/test/CodeGen/X86/midpoint-int-vec-128.ll
M llvm/test/CodeGen/X86/midpoint-int.ll
M llvm/test/CodeGen/X86/mul-i1024.ll
M llvm/test/CodeGen/X86/mul-i256.ll
M llvm/test/CodeGen/X86/mul-i512.ll
M llvm/test/CodeGen/X86/mul-shift-reassoc.ll
M llvm/test/CodeGen/X86/mul128.ll
M llvm/test/CodeGen/X86/neg-abs.ll
M llvm/test/CodeGen/X86/oddshuffles.ll
M llvm/test/CodeGen/X86/opt-pipeline.ll
M llvm/test/CodeGen/X86/pr46877.ll
M llvm/test/CodeGen/X86/scalar-minmax-simd.ll
M llvm/test/CodeGen/X86/shift-amount-mod.ll
M llvm/test/CodeGen/X86/shift-and.ll
M llvm/test/CodeGen/X86/statepoint-cmp-sunk-past-statepoint.ll
M llvm/test/CodeGen/X86/statepoint-relocate-eh.ll
M llvm/test/CodeGen/X86/statepoint-vreg-unlimited-tied-opnds.ll
M llvm/test/CodeGen/X86/tail-dup-asm-goto.ll
M llvm/test/CodeGen/X86/ternlog.ll
M llvm/test/CodeGen/X86/two-address-subreg-to-reg-kill.mir
M llvm/test/CodeGen/X86/twoaddr-lea-eflags-liveintervals.ll
A llvm/test/CodeGen/X86/twoaddr-reschedule-copy-chain.mir
M llvm/test/CodeGen/X86/ucmp.ll
M llvm/test/CodeGen/X86/unfold-masked-merge-vector-variablemask.ll
M llvm/test/CodeGen/X86/vec_umulo.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-3.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-3.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-3.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-8.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-3.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-8.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-3.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-8.ll
M llvm/test/CodeGen/X86/vector-lzcnt-128.ll
M llvm/test/CodeGen/X86/vector-partial-reduce-sumla.ll
M llvm/test/CodeGen/X86/vector-partial-reduce-umla.ll
M llvm/test/CodeGen/X86/vector-reduce-ctpop.ll
M llvm/test/CodeGen/X86/vector-reduce-smax.ll
M llvm/test/CodeGen/X86/vector-reduce-smin.ll
M llvm/test/CodeGen/X86/vector-reduce-umax.ll
M llvm/test/CodeGen/X86/vector-reduce-umin.ll
M llvm/test/CodeGen/X86/vector-trunc-packus.ll
M llvm/test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll
M llvm/test/CodeGen/X86/widen_arith-2.ll
M llvm/test/CodeGen/X86/widen_bitcnt.ll
M llvm/test/CodeGen/X86/zext-trunc.ll
A llvm/test/DebugInfo/AArch64/dbg-value-arg-index-out-of-range.ll
A llvm/test/DebugInfo/Generic/compileunit-source-language-name-roc.ll
M llvm/test/DebugInfo/Inputs/check-fake-use.py
M llvm/test/DebugInfo/MIR/X86/mlicm-hoist-post-regalloc.mir
M llvm/test/DebugInfo/NVPTX/debug-info.ll
M llvm/test/Instrumentation/cgprofile.ll
M llvm/test/LTO/RISCV/module-asm.ll
M llvm/test/MC/AMDGPU/gfx13_asm_vop3-fake16.s
M llvm/test/MC/AMDGPU/gfx13_asm_vop3.s
A llvm/test/MC/AMDGPU/gfx13_asm_vop3_from_vop1_err-fake16.s
A llvm/test/MC/AMDGPU/gfx13_asm_vop3_from_vop1_err.s
M llvm/test/MC/AMDGPU/misaligned-vgpr-tuples-err.s
M llvm/test/MC/AMDGPU/out-of-range-registers.s
M llvm/test/MC/AsmParser/section_names.s
M llvm/test/MC/ELF/section.s
A llvm/test/MC/Hexagon/eh-frame.s
A llvm/test/MC/Hexagon/v79-nontemporal.s
A llvm/test/MC/Mips/eva/set-eva-directive.s
A llvm/test/MC/Mips/eva/set-noeva-directive.s
M llvm/test/MC/RISCV/mapping-across-sections.s
M llvm/test/MC/WebAssembly/assembler-binary.ll
M llvm/test/MC/WebAssembly/call-indirect-relocs.s
M llvm/test/MC/WebAssembly/comdat.ll
M llvm/test/MC/WebAssembly/common.s
M llvm/test/MC/WebAssembly/custom-sections.ll
M llvm/test/MC/WebAssembly/data-section.s
M llvm/test/MC/WebAssembly/debug-info.ll
M llvm/test/MC/WebAssembly/debug-info64.ll
M llvm/test/MC/WebAssembly/export-name.s
M llvm/test/MC/WebAssembly/function-sections.ll
M llvm/test/MC/WebAssembly/global-ctor-dtor.ll
M llvm/test/MC/WebAssembly/globals.s
M llvm/test/MC/WebAssembly/init-array-label.s
M llvm/test/MC/WebAssembly/init-array.s
M llvm/test/MC/WebAssembly/reloc-pic.s
M llvm/test/MC/WebAssembly/reloc-pic64.s
M llvm/test/MC/WebAssembly/tables.s
M llvm/test/MC/WebAssembly/tag-section.s
M llvm/test/MC/WebAssembly/tls.s
M llvm/test/MC/WebAssembly/tls64.s
M llvm/test/MC/WebAssembly/type-index.s
M llvm/test/MC/WebAssembly/unnamed-data.ll
M llvm/test/MC/WebAssembly/wasm64.s
M llvm/test/MC/WebAssembly/weak-alias.s
M llvm/test/ObjectYAML/wasm/dylink_section.yaml
M llvm/test/ObjectYAML/wasm/linking_section.yaml
M llvm/test/Other/opt-bisect-helper.py
M llvm/test/TableGen/JSON-check.py
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-i16.ll
M llvm/test/Transforms/ConstraintElimination/analysis-invalidation.ll
M llvm/test/Transforms/FunctionAttrs/noalias.ll
A llvm/test/Transforms/HotColdSplit/split-out-dbg-val-arglist.ll
A llvm/test/Transforms/InferAddressSpaces/NVPTX/volatile.ll
M llvm/test/Transforms/InferFunctionAttrs/annotate.ll
M llvm/test/Transforms/InstCombine/AMDGPU/llvm.amdgcn.dot.ll
M llvm/test/Transforms/InstCombine/AMDGPU/llvm.amdgcn.sudot.ll
M llvm/test/Transforms/InstCombine/X86/x86-avx512-inseltpoison.ll
M llvm/test/Transforms/InstCombine/bitreverse.ll
M llvm/test/Transforms/InstCombine/cos-1.ll
M llvm/test/Transforms/InstCombine/cos-sin-intrinsic.ll
M llvm/test/Transforms/InstCombine/minmax-fold.ll
A llvm/test/Transforms/InstCombine/pr226504-commuted.ll
A llvm/test/Transforms/InstCombine/pr226504.ll
M llvm/test/Transforms/InstCombine/struct-assign-tbaa.ll
M llvm/test/Transforms/InstCombine/truncating-saturate.ll
M llvm/test/Transforms/JumpTableToSwitch/profile-no-guid-metadata.ll
M llvm/test/Transforms/JumpThreading/thread-prob-1.ll
M llvm/test/Transforms/LICM/hoist-binop.ll
A llvm/test/Transforms/LoopFusion/guard_skip_empty_block.ll
A llvm/test/Transforms/LoopIdiom/AArch64/find-first-byte-nested.ll
M llvm/test/Transforms/LoopVectorize/AArch64/conditional-scalar-assignment-fold-tail.ll
M llvm/test/Transforms/LoopVectorize/AArch64/conditional-scalar-assignment.ll
A llvm/test/Transforms/LoopVectorize/AArch64/diff-checks-force-interleave-count.ll
M llvm/test/Transforms/LoopVectorize/AArch64/epilog-vectorization-widen-inductions.ll
M llvm/test/Transforms/LoopVectorize/AArch64/findlast-epilogue-loop.ll
M llvm/test/Transforms/LoopVectorize/AArch64/induction-costs.ll
A llvm/test/Transforms/LoopVectorize/AArch64/low-trip-count-fixed-vf-no-epilogue.ll
M llvm/test/Transforms/LoopVectorize/AArch64/predicated-costs.ll
M llvm/test/Transforms/LoopVectorize/AArch64/reduction-cost.ll
A llvm/test/Transforms/LoopVectorize/AArch64/sve-induction-wrapflags.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-low-trip-count.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-select-cmp.ll
M llvm/test/Transforms/LoopVectorize/ARM/tail-folding-scalar-epilogue-fallback.ll
M llvm/test/Transforms/LoopVectorize/RISCV/blocks-with-dead-instructions.ll
M llvm/test/Transforms/LoopVectorize/RISCV/conditional-scalar-assignment-fold-tail.ll
M llvm/test/Transforms/LoopVectorize/RISCV/conditional-scalar-assignment.ll
M llvm/test/Transforms/LoopVectorize/RISCV/countable-early-exit-no-epilogue.ll
M llvm/test/Transforms/LoopVectorize/RISCV/dead-ops-cost.ll
M llvm/test/Transforms/LoopVectorize/RISCV/induction-costs.ll
M llvm/test/Transforms/LoopVectorize/RISCV/iv-select-cmp.ll
M llvm/test/Transforms/LoopVectorize/RISCV/select-cmp-reduction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/short-trip-count.ll
M llvm/test/Transforms/LoopVectorize/RISCV/truncate-to-minimal-bitwidth-cost.ll
M llvm/test/Transforms/LoopVectorize/RISCV/type-info-cache-evl-crash.ll
M llvm/test/Transforms/LoopVectorize/VPlan/conditional-scalar-assignment-vplan.ll
M llvm/test/Transforms/LoopVectorize/VPlan/execution-frequencies-match-bfi.ll
M llvm/test/Transforms/LoopVectorize/VPlan/interleave-conditional-scalar-assignment-vplan.ll
M llvm/test/Transforms/LoopVectorize/VPlan/memory-checks.ll
M llvm/test/Transforms/LoopVectorize/VPlan/record-execution-frequencies.ll
M llvm/test/Transforms/LoopVectorize/VPlan/vplan-based-stride-mv.ll
M llvm/test/Transforms/LoopVectorize/VPlan/vplan-printing-branch-weights.ll
M llvm/test/Transforms/LoopVectorize/X86/conditional-scalar-assignment.ll
M llvm/test/Transforms/LoopVectorize/X86/cost-model.ll
M llvm/test/Transforms/LoopVectorize/X86/induction-costs.ll
M llvm/test/Transforms/LoopVectorize/X86/interleave-cost.ll
M llvm/test/Transforms/LoopVectorize/X86/pr36524.ll
M llvm/test/Transforms/LoopVectorize/X86/predicated-instruction-cost.ll
M llvm/test/Transforms/LoopVectorize/alias-mask.ll
M llvm/test/Transforms/LoopVectorize/conditional-scalar-assignment-interleave-only.ll
M llvm/test/Transforms/LoopVectorize/consecutive-ptr-uniforms.ll
M llvm/test/Transforms/LoopVectorize/find-last-iv-sinkable-expr-tail-folding.ll
M llvm/test/Transforms/LoopVectorize/find-last-iv-sinkable-expr.ll
M llvm/test/Transforms/LoopVectorize/find-last-iv-sinkable-load.ll
M llvm/test/Transforms/LoopVectorize/find-last-ptr-induction.ll
M llvm/test/Transforms/LoopVectorize/find-last.ll
M llvm/test/Transforms/LoopVectorize/if-conversion.ll
M llvm/test/Transforms/LoopVectorize/induction-wrapflags.ll
M llvm/test/Transforms/LoopVectorize/induction.ll
M llvm/test/Transforms/LoopVectorize/interleaved-accesses-metadata.ll
M llvm/test/Transforms/LoopVectorize/intrinsic.ll
M llvm/test/Transforms/LoopVectorize/invariant-store-vectorization-2.ll
M llvm/test/Transforms/LoopVectorize/invariant-store-vectorization.ll
M llvm/test/Transforms/LoopVectorize/iv-select-cmp-fold-tail.ll
M llvm/test/Transforms/LoopVectorize/iv-select-cmp-non-const-iv-start.ll
M llvm/test/Transforms/LoopVectorize/iv-select-cmp-trunc.ll
M llvm/test/Transforms/LoopVectorize/iv-select-cmp.ll
M llvm/test/Transforms/LoopVectorize/metadata.ll
M llvm/test/Transforms/LoopVectorize/opaque-ptr.ll
M llvm/test/Transforms/LoopVectorize/optimal-epilog-vectorization-liveout.ll
M llvm/test/Transforms/LoopVectorize/pointer-select-runtime-checks.ll
M llvm/test/Transforms/LoopVectorize/pr30654-phiscev-sext-trunc.ll
M llvm/test/Transforms/LoopVectorize/pr35773.ll
M llvm/test/Transforms/LoopVectorize/pr59319-loop-access-info-invalidation.ll
M llvm/test/Transforms/LoopVectorize/predicated-inductions-vs-first-order-recurrences.ll
M llvm/test/Transforms/LoopVectorize/predicated-inductions.ll
M llvm/test/Transforms/LoopVectorize/replicate-region-branch-weights.ll
M llvm/test/Transforms/LoopVectorize/runtime-check.ll
A llvm/test/Transforms/LoopVectorize/scev-variable-stride-predicate.ll
M llvm/test/Transforms/LoopVectorize/select-cmp.ll
M llvm/test/Transforms/LoopVectorize/select-last-index-fp.ll
M llvm/test/Transforms/LoopVectorize/single-value-blend-phis.ll
A llvm/test/Transforms/MergeFunc/redirect-call-debug-loc.ll
M llvm/test/Transforms/PGOProfile/Inputs/cspgo_bar_sample.ll
M llvm/test/Transforms/PGOProfile/Inputs/thinlto_cspgo_bar_gen.ll
M llvm/test/Transforms/PGOProfile/Inputs/thinlto_cspgo_bar_use.ll
M llvm/test/Transforms/PGOProfile/icp_invoke.ll
M llvm/test/Transforms/PGOProfile/icp_invoke_nouse.ll
M llvm/test/Transforms/PGOProfile/thinlto_indirect_call_promotion.ll
M llvm/test/Transforms/PhaseOrdering/AArch64/hoist-runtime-checks.ll
M llvm/test/Transforms/PhaseOrdering/AArch64/reassociate-fma-pairs.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/extracts-folded-into-fmul-users-no-credit.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/fadd-with-gathered-fmul-operands.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/fma-candidates-after-store-chains.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/fma-chain-no-alt-node-reduction.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/fmul-constant-lane-fmuladd-combine.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/hor-fp-reduction-instcount.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/lcssa-phi-extract-scale.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/loop-accumulator-reduction.ll
A llvm/test/Transforms/SLPVectorizer/AArch64/ordered-reduction-of-loads.ll
A llvm/test/Transforms/SLPVectorizer/AArch64/reduced-value-next-to-fused-fmul.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/reduction-root-multi-use-fma.ll
A llvm/test/Transforms/SLPVectorizer/AArch64/trimmed-subtree-schedule-operands.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/vec3-reorder-reshuffle.ll
A llvm/test/Transforms/SLPVectorizer/AMDGPU/cross-block-fmul-fadd.ll
A llvm/test/Transforms/SLPVectorizer/AMDGPU/fmul-sunk-into-fadd-block.ll
M llvm/test/Transforms/SLPVectorizer/NVPTX/ordered-reduction-fma-fusion.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/ordered-reduction.ll
A llvm/test/Transforms/SLPVectorizer/RISCV/trimmed-node-matching-gather.ll
A llvm/test/Transforms/SLPVectorizer/X86/extracted-subfields-shifted-trunc.ll
M llvm/test/Transforms/SLPVectorizer/X86/extracted-subfields.ll
M llvm/test/Transforms/SLPVectorizer/X86/fmul-fused-into-scalar-fadd.ll
M llvm/test/Transforms/SLPVectorizer/X86/fsub-fmul-rhs-combine.ll
A llvm/test/Transforms/SLPVectorizer/X86/narrowed-reduction-gathered-leftover-leaf.ll
A llvm/test/Transforms/SLPVectorizer/X86/narrowed-reduction-minbw-root.ll
M llvm/test/Transforms/SLPVectorizer/X86/runtime-alias-checks.ll
M llvm/test/Transforms/SLPVectorizer/X86/slp-fma-loss-ordered.ll
A llvm/test/Transforms/SLPVectorizer/X86/strength-reducible-address.ll
A llvm/test/Transforms/SLPVectorizer/X86/trimmed-node-matching-gather-emitted-first.ll
M llvm/test/Transforms/SLPVectorizer/consecutive-access.ll
M llvm/test/Transforms/SROA/load-store-overlap.ll
M llvm/test/Transforms/SampleProfile/pseudo-probe-twoaddr.ll
A llvm/test/Transforms/SimplifyCFG/AArch64/speculate-vector-phi-select-cost.ll
A llvm/test/Transforms/SimplifyCFG/ARM/speculate-vector-phi-select-cost.ll
A llvm/test/Transforms/SimplifyCFG/RISCV/speculate-mask-phi-select-cost.ll
A llvm/test/Transforms/SimplifyCFG/X86/speculate-mask-phi-select-cost.ll
M llvm/test/Transforms/SimplifyCFG/hoist-common-skip.ll
A llvm/test/Transforms/TailCallElim/return-value-select-pgo.ll
M llvm/test/Transforms/VectorCombine/binop-scalarize.ll
A llvm/test/Transforms/VectorCombine/cmp-scalarize.ll
M llvm/test/Transforms/VectorCombine/unary-op-scalarize.ll
A llvm/test/Verifier/dbg-record-expression-arg-out-of-range.ll
M llvm/test/Verifier/tbaa-struct.ll
M llvm/test/lit.cfg.py
M llvm/test/tools/dxil-dis/constantexpr-gep.ll
M llvm/test/tools/gold/X86/Inputs/thinlto_cspgo_bar.ll
A llvm/test/tools/llubi/intr_speculative_load.ll
A llvm/test/tools/llubi/intr_speculative_load_ub.ll
A llvm/test/tools/llvm-cas/validate-if-needed.test
A llvm/test/tools/llvm-profdata/Inputs/guid-roundtrip.c
A llvm/test/tools/llvm-profdata/Inputs/guid-roundtrip.proftext
A llvm/test/tools/llvm-profdata/guid-roundtrip.test
M llvm/test/tools/llvm-profdata/profile-symbol-list.test
R llvm/test/tools/llvm-readobj/ELF/RISCV/eflags-abi.test
A llvm/test/tools/llvm-readobj/ELF/RISCV/eflags.test
M llvm/test/tools/llvm-reduce/Inputs/sleep-and-check-stores.py
A llvm/test/tools/llvm-strings/chunk-boundary.test
A llvm/test/tools/yaml2obj/COFF/bb-addr-map-pgo-analysis-map.yaml
A llvm/test/tools/yaml2obj/COFF/bb-addr-map.yaml
A llvm/test/tools/yaml2obj/COFF/section-semantic-content.yaml
M llvm/tools/dsymutil/DwarfLinkerForBinary.h
M llvm/tools/llubi/lib/Interpreter.cpp
M llvm/tools/llvm-cgdata/llvm-cgdata.cpp
M llvm/tools/llvm-cov/CodeCoverage.cpp
M llvm/tools/llvm-jitlink/llvm-jitlink.cpp
M llvm/tools/llvm-objdump/COFFDump.h
M llvm/tools/llvm-objdump/ELFDump.h
M llvm/tools/llvm-objdump/OffloadDump.cpp
M llvm/tools/llvm-objdump/WasmDump.h
M llvm/tools/llvm-profgen/PerfReader.cpp
M llvm/tools/llvm-profgen/PerfReader.h
M llvm/tools/llvm-strings/llvm-strings.cpp
M llvm/tools/obj2yaml/wasm2yaml.cpp
M llvm/tools/opt-viewer/extract-reproducers.py
M llvm/tools/opt-viewer/opt-diff.py
M llvm/tools/opt-viewer/opt-stats.py
M llvm/tools/opt-viewer/opt-viewer.py
M llvm/tools/opt-viewer/optrecord.py
M llvm/unittests/ADT/DenseMapTest.cpp
M llvm/unittests/ADT/StringRefTest.cpp
M llvm/unittests/CodeGen/GlobalISel/LegalizerHelperTest.cpp
M llvm/unittests/CodeGen/SelectionDAGPatternMatchTest.cpp
M llvm/unittests/ExecutionEngine/Orc/ExecutionSessionWrapperFunctionCallsTest.cpp
M llvm/unittests/IR/ConstantRangeTest.cpp
M llvm/unittests/ProfileData/InstrProfTest.cpp
M llvm/unittests/ProfileData/SampleProfTest.cpp
M llvm/unittests/Support/CommandLineTest.cpp
M llvm/unittests/Support/CompressionTest.cpp
M llvm/unittests/Support/LLVMToolSession/LLVMToolSessionTest.cpp
M llvm/unittests/Support/raw_socket_stream_test.cpp
M llvm/unittests/Transforms/Vectorize/VPlanVerifierTest.cpp
M llvm/utils/DSAclean.py
M llvm/utils/DSAextract.py
M llvm/utils/LLVMVisualizers/llvm.natvis
M llvm/utils/Misc/zkill
M llvm/utils/TableGen/Common/CodeGenRegisters.cpp
M llvm/utils/TableGen/FastISelEmitter.cpp
M llvm/utils/Target/ARM/analyze-match-table.py
M llvm/utils/abtest.py
M llvm/utils/bisect
M llvm/utils/chunk-print-before-all.py
M llvm/utils/clang-parse-diagnostics-file
M llvm/utils/convert-constraint-log-to-z3.py
M llvm/utils/create_ladder_graph.py
M llvm/utils/docker/scripts/llvm_checksum/llvm_checksum.py
M llvm/utils/extract-section.py
M llvm/utils/extract_symbols.py
M llvm/utils/extract_vplan.py
M llvm/utils/gdb-scripts/prettyprinters.py
M llvm/utils/gn/build/BUILD.gn
M llvm/utils/gn/build/BUILDCONFIG.gn
M llvm/utils/gn/build/mac_sdk.gni
M llvm/utils/gn/secondary/clang/include/clang/Config/BUILD.gn
M llvm/utils/gn/secondary/clang/lib/ScalableStaticAnalysis/Analyses/BUILD.gn
M llvm/utils/gn/secondary/clang/tools/clang-repl/BUILD.gn
M llvm/utils/gn/secondary/clang/unittests/Basic/BUILD.gn
M llvm/utils/gn/secondary/clang/unittests/Interpreter/BUILD.gn
M llvm/utils/gn/secondary/clang/unittests/ScalableStaticAnalysis/BUILD.gn
M llvm/utils/gn/secondary/libcxx/include/BUILD.gn
M llvm/utils/gn/secondary/lld/unittests/AsLibELF/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/Support/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/Target/AMDGPU/BUILD.gn
M llvm/utils/gn/secondary/llvm/tools/llc/BUILD.gn
M llvm/utils/gn/secondary/llvm/tools/lli/BUILD.gn
M llvm/utils/gn/secondary/llvm/tools/llvm-jitlink/BUILD.gn
M llvm/utils/gn/secondary/llvm/tools/opt/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/Analysis/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/CodeGen/CGPluginTest/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/DebugInfo/LogicalView/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/DebugInfo/PDB/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/ExecutionEngine/Orc/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/Passes/Plugins/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/Support/DynamicLibrary/BUILD.gn
M llvm/utils/gn/secondary/third-party/unittest/unittest.gni
M llvm/utils/indirect_calls.py
M llvm/utils/lint/common_lint.py
M llvm/utils/lint/cpp_lint.py
M llvm/utils/lint/generic_lint.py
M llvm/utils/lit/lit/ProgressBar.py
M llvm/utils/lit/tests/Inputs/check_path.py
M llvm/utils/lit/tests/Inputs/fake-externals/cd
M llvm/utils/lit/tests/Inputs/fake-externals/diff
M llvm/utils/lit/tests/Inputs/fake-externals/env
M llvm/utils/lit/tests/Inputs/fake-externals/export
M llvm/utils/lit/tests/Inputs/fake-externals/mkdir
M llvm/utils/lit/tests/Inputs/fake-externals/rm
M llvm/utils/lit/tests/Inputs/googletest-crash/DummySubDir/OneTest.py
M llvm/utils/lit/tests/Inputs/googletest-detect-duplicate/DummySubDir/OneTest.py
M llvm/utils/lit/tests/Inputs/googletest-discovery-failed/subdir/OneTest.py
M llvm/utils/lit/tests/Inputs/googletest-format-respect-gtest-sharding-env-vars/DummySubDir/OneTest.py
M llvm/utils/lit/tests/Inputs/googletest-format/DummySubDir/OneTest.py
M llvm/utils/lit/tests/Inputs/googletest-no-sharding/DummySubDir/OneTest.py
M llvm/utils/lit/tests/Inputs/googletest-prefix/DummySubDir/test_one.py
M llvm/utils/lit/tests/Inputs/googletest-sanitizer-error/DummySubDir/OneTest.py
M llvm/utils/lit/tests/Inputs/googletest-timeout/DummySubDir/OneTest.py
M llvm/utils/lit/tests/Inputs/shtest-format/write-bad-encoding.py
M llvm/utils/lit/tests/Inputs/shtest-format/write-control-chars.py
M llvm/utils/lit/tests/Inputs/shtest-not-posix/fail-signal.py
M llvm/utils/lit/tests/Inputs/shtest-not/fail.py
M llvm/utils/lit/tests/Inputs/shtest-not/fail2.py
M llvm/utils/lit/tests/Inputs/shtest-not/pass.py
M llvm/utils/lit/tests/Inputs/shtest-output-printing/write-a-lot.py
M llvm/utils/lit/tests/Inputs/shtest-shell/check_args.py
M llvm/utils/lit/tests/Inputs/shtest-shell/write-to-stderr.py
M llvm/utils/lit/tests/Inputs/shtest-shell/write-to-stdout-and-stderr.py
M llvm/utils/lit/tests/check-tested-lit-timeout-ability
M llvm/utils/lldbDataFormatters.py
M llvm/utils/llvm-gisel-cov.py
M llvm/utils/llvm-original-di-preservation.py
M llvm/utils/merge-json.py
M llvm/utils/profcheck-xfail.txt
M llvm/utils/release/findRegressions-nightly.py
M llvm/utils/release/findRegressions-simple.py
M llvm/utils/remote-exec.py
M llvm/utils/schedcover.py
M llvm/utils/shuffle_fuzz.py
M llvm/utils/shuffle_select_fuzz_tester.py
M llvm/utils/sort_includes.py
M llvm/utils/testgen/mc-bundling-x86-gen.py
M llvm/utils/unicode-case-fold.py
M llvm/utils/wciia.py
M mlir/docs/DefiningDialects/Operations.md
M mlir/docs/DefiningDialects/_index.md
M mlir/docs/Interfaces.md
M mlir/docs/ReleaseNotes.md
M mlir/docs/Tools/mlir-reduce.md
M mlir/examples/toy/Ch4/include/toy/Ops.td
M mlir/examples/toy/Ch5/include/toy/Ops.td
M mlir/examples/toy/Ch6/include/toy/Ops.td
M mlir/examples/toy/Ch7/include/toy/Ops.td
M mlir/include/mlir/Conversion/Passes.td
M mlir/include/mlir/Conversion/TosaToLinalg/TosaToLinalg.h
M mlir/include/mlir/Dialect/AMDGPU/IR/AMDGPUBase.td
M mlir/include/mlir/Dialect/Affine/IR/AffineOps.td
M mlir/include/mlir/Dialect/Arith/IR/ArithBase.td
M mlir/include/mlir/Dialect/ArmNeon/ArmNeon.td
M mlir/include/mlir/Dialect/ArmSME/IR/ArmSME.td
M mlir/include/mlir/Dialect/ArmSVE/IR/ArmSVE.td
M mlir/include/mlir/Dialect/Async/IR/AsyncDialect.td
M mlir/include/mlir/Dialect/Bufferization/IR/BufferizationBase.td
M mlir/include/mlir/Dialect/Complex/IR/ComplexBase.td
M mlir/include/mlir/Dialect/ControlFlow/IR/ControlFlowOps.td
M mlir/include/mlir/Dialect/DLTI/DLTIBase.td
M mlir/include/mlir/Dialect/EmitC/IR/EmitCBase.td
M mlir/include/mlir/Dialect/Func/IR/FuncOps.td
M mlir/include/mlir/Dialect/GPU/IR/GPUBase.td
M mlir/include/mlir/Dialect/IRDL/IR/IRDL.td
M mlir/include/mlir/Dialect/Index/IR/IndexDialect.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMDialect.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMIntrinsicOps.td
M mlir/include/mlir/Dialect/LLVMIR/NVVMDialect.td
M mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
M mlir/include/mlir/Dialect/LLVMIR/ROCDLDialect.td
M mlir/include/mlir/Dialect/LLVMIR/VCIXOps.td
M mlir/include/mlir/Dialect/LLVMIR/XeVMOps.td
M mlir/include/mlir/Dialect/Linalg/IR/LinalgBase.td
M mlir/include/mlir/Dialect/Linalg/IR/LinalgInterfaces.td
M mlir/include/mlir/Dialect/Linalg/TransformOps/LinalgTransformOps.td
M mlir/include/mlir/Dialect/MLProgram/IR/MLProgramBase.td
M mlir/include/mlir/Dialect/MPI/IR/MPI.td
M mlir/include/mlir/Dialect/Math/IR/MathBase.td
M mlir/include/mlir/Dialect/MemRef/IR/MemRefBase.td
M mlir/include/mlir/Dialect/NVGPU/IR/NVGPU.td
M mlir/include/mlir/Dialect/OpenACC/OpenACCBase.td
M mlir/include/mlir/Dialect/OpenACC/OpenACCCGAttributes.td
M mlir/include/mlir/Dialect/OpenACC/OpenACCOpsInterfaces.td
M mlir/include/mlir/Dialect/OpenACC/OpenACCUtilsCG.h
M mlir/include/mlir/Dialect/OpenACC/Transforms/Passes.td
M mlir/include/mlir/Dialect/OpenMP/OpenMPDialect.td
M mlir/include/mlir/Dialect/OpenMP/OpenMPOpsInterfaces.td
M mlir/include/mlir/Dialect/PDL/IR/PDLDialect.td
M mlir/include/mlir/Dialect/PDLInterp/IR/PDLInterpOps.td
M mlir/include/mlir/Dialect/Ptr/IR/PtrDialect.td
M mlir/include/mlir/Dialect/Quant/IR/QuantBase.td
M mlir/include/mlir/Dialect/SCF/IR/SCFOps.td
M mlir/include/mlir/Dialect/SMT/IR/SMTDialect.td
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBase.td
M mlir/include/mlir/Dialect/Shape/IR/ShapeBase.td
M mlir/include/mlir/Dialect/Shard/IR/ShardBase.td
M mlir/include/mlir/Dialect/SparseTensor/IR/SparseTensorBase.td
M mlir/include/mlir/Dialect/SparseTensor/IR/SparseTensorInterfaces.td
M mlir/include/mlir/Dialect/Tensor/IR/TensorBase.td
M mlir/include/mlir/Dialect/Tosa/IR/TosaOpBase.td
M mlir/include/mlir/Dialect/Tosa/IR/TosaOps.td
M mlir/include/mlir/Dialect/Transform/IR/TransformDialect.td
M mlir/include/mlir/Dialect/UB/IR/UBOps.td
M mlir/include/mlir/Dialect/Utils/StaticValueUtils.h
M mlir/include/mlir/Dialect/Vector/IR/Vector.td
M mlir/include/mlir/Dialect/WasmSSA/IR/WasmSSABase.td
M mlir/include/mlir/Dialect/WasmSSA/IR/WasmSSAInterfaces.td
M mlir/include/mlir/Dialect/X86/X86.td
M mlir/include/mlir/Dialect/XeGPU/IR/XeGPUDialect.td
M mlir/include/mlir/IR/BuiltinDialect.td
M mlir/include/mlir/IR/Diagnostics.h
M mlir/include/mlir/IR/DialectBase.td
M mlir/include/mlir/IR/SymbolTable.h
M mlir/include/mlir/Interfaces/ControlFlowInterfaces.td
M mlir/include/mlir/Support/InterfaceSupport.h
M mlir/include/mlir/Target/Cpp/CppEmitter.h
M mlir/lib/Conversion/SCFToControlFlow/SCFToControlFlow.cpp
M mlir/lib/Conversion/SCFToGPU/SCFToGPU.cpp
M mlir/lib/Conversion/SCFToOpenMP/SCFToOpenMP.cpp
M mlir/lib/Conversion/TosaToLinalg/TosaToLinalg.cpp
M mlir/lib/Conversion/TosaToLinalg/TosaToLinalgPass.cpp
M mlir/lib/Dialect/Async/Transforms/AsyncParallelFor.cpp
M mlir/lib/Dialect/ControlFlow/IR/ControlFlowOps.cpp
M mlir/lib/Dialect/GPU/CMakeLists.txt
M mlir/lib/Dialect/GPU/Transforms/DecomposeMemRefs.cpp
M mlir/lib/Dialect/IRDL/IR/IRDL.cpp
M mlir/lib/Dialect/LLVMIR/IR/NVVMDialect.cpp
M mlir/lib/Dialect/Linalg/TransformOps/LinalgTransformOps.cpp
M mlir/lib/Dialect/MemRef/IR/MemRefOps.cpp
M mlir/lib/Dialect/MemRef/Transforms/ExpandStridedMetadata.cpp
M mlir/lib/Dialect/OpenACC/Transforms/ACCBindRoutine.cpp
M mlir/lib/Dialect/OpenACC/Transforms/ACCCGToGPU.cpp
M mlir/lib/Dialect/OpenACC/Transforms/ACCComputeLowering.cpp
M mlir/lib/Dialect/OpenACC/Utils/OpenACCUtilsCG.cpp
M mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp
M mlir/lib/Dialect/SCF/IR/SCF.cpp
M mlir/lib/Dialect/SCF/Transforms/ParallelForToNestedFors.cpp
M mlir/lib/Dialect/SCF/Transforms/ParallelLoopCollapsing.cpp
M mlir/lib/Dialect/SCF/Transforms/ParallelLoopFusion.cpp
M mlir/lib/Dialect/SCF/Transforms/ParallelLoopTiling.cpp
M mlir/lib/Dialect/Tosa/Transforms/TosaNarrowTypes.cpp
M mlir/lib/Dialect/Utils/StaticValueUtils.cpp
M mlir/lib/IR/BuiltinTypes.cpp
M mlir/lib/IR/Diagnostics.cpp
M mlir/lib/IR/SymbolTable.cpp
M mlir/lib/Reducer/ReductionNode.cpp
M mlir/lib/Target/Cpp/TranslateToCpp.cpp
M mlir/lib/Target/IRDLToCpp/IRDLToCpp.cpp
M mlir/lib/Target/LLVMIR/Dialect/LLVMIR/LLVMToLLVMIRTranslation.cpp
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
M mlir/lib/Tools/mlir-opt/MlirOptMain.cpp
M mlir/lib/Transforms/RemoveDeadValues.cpp
M mlir/python/mlir/dialects/ext.py
M mlir/test/Analysis/DataFlow/test-last-modified-callgraph.mlir
M mlir/test/Analysis/DataFlow/test-last-modified.mlir
M mlir/test/Analysis/DataFlow/test-next-access.mlir
M mlir/test/Analysis/DataFlow/test-strided-metadata-range-analysis.mlir
M mlir/test/Conversion/MemRefToSPIRV/memref-to-spirv.mlir
M mlir/test/Conversion/SCFToControlFlow/convert-to-cfg.mlir
M mlir/test/Conversion/SCFToGPU/parallel_loop.mlir
A mlir/test/Conversion/SCFToOpenMP/scf-to-openmp-unsigned.mlir
M mlir/test/Conversion/TosaToLinalg/tosa-to-linalg.mlir
M mlir/test/Conversion/TosaToSPIRVTosa/graph-constant-mark.mlir
M mlir/test/Dialect/Affine/affine-loop-normalize.mlir
M mlir/test/Dialect/Affine/int-range-interface.mlir
M mlir/test/Dialect/Affine/simplify-min-max-ops.mlir
M mlir/test/Dialect/Affine/simplify-with-bounds.mlir
M mlir/test/Dialect/Affine/transform-op-simplify-min-max-ops.mlir
M mlir/test/Dialect/Arith/int-range-analysis-convergence.mlir
M mlir/test/Dialect/Arith/int-range-interface.mlir
M mlir/test/Dialect/Arith/int-range-loop-iter-args.mlir
M mlir/test/Dialect/Arith/int-range-narrowing.mlir
M mlir/test/Dialect/Arith/int-range-opts-bug-119045.mlir
M mlir/test/Dialect/Arith/int-range-opts.mlir
M mlir/test/Dialect/Async/async-parallel-for-async-dispatch.mlir
M mlir/test/Dialect/ControlFlow/canonicalize.mlir
M mlir/test/Dialect/ControlFlow/invalid.mlir
M mlir/test/Dialect/ControlFlow/ops.mlir
M mlir/test/Dialect/GPU/decompose-memrefs.mlir
M mlir/test/Dialect/GPU/int-range-interface-cluster.mlir
M mlir/test/Dialect/GPU/int-range-interface.mlir
M mlir/test/Dialect/LLVMIR/nvvm_check_target_sm.mlir
M mlir/test/Dialect/LLVMIR/roundtrip.mlir
M mlir/test/Dialect/Linalg/erase-unused-operands-and-results.mlir
M mlir/test/Dialect/Linalg/swap-extract-slice-with-fill.mlir
A mlir/test/Dialect/Linalg/td/erase-unused-operands-and-results.mlir
A mlir/test/Dialect/Linalg/td/swap-extract-slice-with-fill.mlir
R mlir/test/Dialect/Linalg/transform-op-swap-extract-slice-with-fill.mlir
M mlir/test/Dialect/MLProgram/pipeline-globals.mlir
M mlir/test/Dialect/MemRef/canonicalize.mlir
M mlir/test/Dialect/MemRef/elide-reinterpret-cast-load.mlir
M mlir/test/Dialect/MemRef/expand-strided-metadata.mlir
M mlir/test/Dialect/MemRef/int-range-inference.mlir
M mlir/test/Dialect/MemRef/ops.mlir
A mlir/test/Dialect/OpenACC/acc-bind-routine-missing-materialization.mlir
M mlir/test/Dialect/OpenACC/acc-bind-routine.mlir
M mlir/test/Dialect/OpenACC/acc-cg-to-gpu-bound-routine-call.mlir
M mlir/test/Dialect/OpenACC/acc-cg-to-gpu-predicate-region-reuse-barrier.mlir
M mlir/test/Dialect/OpenACC/acc-cg-to-gpu-thread-private-storage-remark.mlir
M mlir/test/Dialect/OpenACC/acc-compute-lowering-loop.mlir
M mlir/test/Dialect/OpenACC/acc-implicit-routine.mlir
A mlir/test/Dialect/OpenACC/acc-materialize-routine-bind-targets-invalid.mlir
M mlir/test/Dialect/OpenMP/invalid.mlir
M mlir/test/Dialect/OpenMP/ops.mlir
M mlir/test/Dialect/SCF/ops.mlir
M mlir/test/Dialect/SCF/parallel-loop-fusion.mlir
M mlir/test/Dialect/SCF/parallel-loop-tiling-inbound-check.mlir
M mlir/test/Dialect/SCF/parallel-to-nested-fors.mlir
M mlir/test/Dialect/Tensor/int-range-inference.mlir
M mlir/test/Dialect/Tosa/canonicalize.mlir
M mlir/test/Dialect/Tosa/constant_folding.mlir
M mlir/test/Dialect/Tosa/ops.mlir
M mlir/test/Dialect/Tosa/tosa-arith-const-to-tosa-const.mlir
M mlir/test/Dialect/Tosa/tosa-convert-integer-type-to-signless.mlir
M mlir/test/Dialect/Tosa/tosa-decompose-depthwise.mlir
M mlir/test/Dialect/Tosa/tosa-decompose-transpose-conv.mlir
M mlir/test/Dialect/Tosa/tosa-gather-scatter-hardening.mlir
M mlir/test/Dialect/Tosa/tosa-infer-shapes.mlir
M mlir/test/Dialect/Tosa/tosa-layerwise-constant-fold-dense-resource.mlir
M mlir/test/Dialect/Tosa/tosa-layerwise-constant-fold.mlir
M mlir/test/Dialect/Tosa/tosa-narrow-f32-to-f16-aggressive.mlir
M mlir/test/Dialect/Tosa/tosa-narrow-f32-to-f16.mlir
M mlir/test/Dialect/Tosa/tosa-narrow-f64-to-f32-aggressive.mlir
M mlir/test/Dialect/Tosa/tosa-narrow-f64-to-f32.mlir
M mlir/test/Dialect/Tosa/tosa-narrow-i64-to-i32-aggressive.mlir
M mlir/test/Dialect/Tosa/tosa-narrow-i64-to-i32.mlir
M mlir/test/Dialect/Tosa/tosa-reduce-transposes.mlir
M mlir/test/Dialect/Vector/int-range-interface.mlir
M mlir/test/IR/attribute.mlir
M mlir/test/Interfaces/InferIntRangeInterface/infer-int-range-test-ops-invalid.mlir
M mlir/test/Interfaces/InferIntRangeInterface/infer-int-range-test-ops.mlir
A mlir/test/Pass/remark-final-verify-diagnostics.mlir
M mlir/test/Target/Cpp/expressions.mlir
M mlir/test/Target/LLVMIR/Import/intrinsic.ll
M mlir/test/Target/LLVMIR/llvmir-intrinsics.mlir
M mlir/test/Target/LLVMIR/llvmir-invalid.mlir
M mlir/test/Target/LLVMIR/llvmir.mlir
M mlir/test/Target/LLVMIR/nvvm/convert_fp4x2.mlir
M mlir/test/Target/LLVMIR/openmp-allocate-clause.mlir
A mlir/test/Target/LLVMIR/openmp-scope-allocate-clause.mlir
M mlir/test/Target/LLVMIR/openmp-taskwait-depend.mlir
M mlir/test/Target/LLVMIR/openmp-todo.mlir
M mlir/test/Transforms/loop-invariant-code-motion.mlir
M mlir/test/Transforms/make-composed-folded-affine-apply.mlir
A mlir/test/Transforms/parallel-loop-collapsing-unsigned.mlir
A mlir/test/Transforms/remove-dead-values-symbol-scope.mlir
M mlir/test/lib/Dialect/Test/TestOps.td
M mlir/test/lib/Dialect/Test/TestOpsSyntax.td
M mlir/test/lib/Dialect/TestIRDLToCpp/test_irdl_to_cpp.irdl.mlir
M mlir/test/mlir-reduce/reduction-tree/doc-example.mlir
A mlir/test/mlir-reduce/reduction-tree/except-last.mlir
A mlir/test/mlir-reduce/script/except-last.sh
M mlir/test/mlir-tblgen/constant-str-attr-invalid.mlir
M mlir/test/mlir-tblgen/op-format-invalid.td
M mlir/test/mlir-tblgen/op-format.mlir
M mlir/test/mlir-tblgen/op-format.td
M mlir/test/mlir-tblgen/op-interface.td
M mlir/test/mlir-tblgen/pattern.mlir
M mlir/test/python/dialects/ext.py
M mlir/test/python/dialects/python_test.py
M mlir/test/python/dialects/transform.py
M mlir/test/python/python_test_ops.td
M mlir/tools/mlir-tblgen/OpInterfacesGen.cpp
M mlir/unittests/Dialect/OpenACC/OpenACCUtilsCGTest.cpp
M mlir/unittests/IR/Diagnostic.cpp
M mlir/unittests/IR/SymbolTableTest.cpp
M offload/CMakeLists.txt
M offload/include/Shared/SourceInfo.h
M offload/languages/cuda/CMakeLists.txt
M offload/languages/hip/CMakeLists.txt
M offload/languages/kernel/CMakeLists.txt
M offload/liboffload/API/Common.td
M offload/liboffload/src/OffloadImpl.cpp
M offload/plugins-nextgen/amdgpu/dynamic_hsa/hsa.cpp
M offload/plugins-nextgen/cuda/dynamic_cuda/cuda.cpp
M offload/plugins-nextgen/level_zero/src/L0Program.cpp
M offload/test/offloading/info.c
A offload/test/offloading/shared_lib_global_var.c
M offload/tools/CMakeLists.txt
M offload/tools/deviceinfo/CMakeLists.txt
M offload/tools/kernelreplay/CMakeLists.txt
M offload/tools/offload-tblgen/EntryPointGen.cpp
M offload/unittests/OffloadAPI/init/olInit.cpp
M openmp/docs/ReleaseNotes.md
M openmp/module/CMakeLists.txt
M orc-rt/cmake/OrcRTTesting.cmake
M orc-rt/include/CMakeLists.txt
A orc-rt/include/orc-rt-c/support/LogLevel.h
M orc-rt/include/orc-rt-c/support/Logging.h
M orc-rt/include/orc-rt/bedrock/ConnectorRegistry.h
M orc-rt/include/orc-rt/bedrock/Session.h
M orc-rt/include/orc-rt/bedrock/sps/SimpleRemoteCAOverSocket.h
M orc-rt/include/orc-rt/support/bind.h
M orc-rt/lib/bedrock/ConnectorRegistry.cpp
M orc-rt/lib/bedrock/Session.cpp
M orc-rt/lib/bedrock/sys/posix/SocketConnector.cpp
M orc-rt/lib/bedrock/sys/posix/sps/SimpleRemoteCAOverSocket.cpp
A orc-rt/lib/bedrock/sys/windows/SocketConnector.cpp
M orc-rt/test/regression/README.md
M orc-rt/test/regression/jit-free-foundations/check-rt-process-info.test
M orc-rt/test/regression/jit-free-foundations/lit.local.cfg
A orc-rt/test/regression/languages/c/addressing/cross-object/global-array-element-pointer-in-data.test
A orc-rt/test/regression/languages/c/addressing/cross-object/global-data-load.test
A orc-rt/test/regression/languages/c/addressing/cross-object/hidden-data-load.test
A orc-rt/test/regression/languages/c/addressing/same-object/global-data-pointer-in-data.c
A orc-rt/test/regression/languages/c/addressing/same-object/global-data-store.c
A orc-rt/test/regression/languages/c/addressing/same-object/static-array-element-load.c
A orc-rt/test/regression/languages/c/addressing/same-object/static-data-load.c
M orc-rt/test/regression/languages/c/lit.local.cfg
M orc-rt/test/regression/languages/c/return-zero.c
M orc-rt/test/regression/lit.cfg.py
M orc-rt/test/regression/object-formats/lit.local.cfg
M orc-rt/test/regression/object-formats/mach-o/arm64/return-zero.s
M orc-rt/test/tools/orc-rt-process-info-check.cpp
M orc-rt/test/unit/CMakeLists.txt
M orc-rt/test/unit/CommonTestUtils.h
M orc-rt/test/unit/bedrock/InProcessControllerAccessTest.cpp
M orc-rt/test/unit/bedrock/SessionTest.cpp
R orc-rt/test/unit/bedrock/SocketConnectorTest.cpp
M orc-rt/test/unit/bedrock/SocketTestUtils.h
M orc-rt/test/unit/bedrock/sps/SimpleRemoteCAOverSocketTest.cpp
A orc-rt/test/unit/bedrock/sys/posix/SocketConnectorTest.cpp
M orc-rt/test/unit/bedrock/sys/posix/SocketTestUtils.cpp
M orc-rt/test/unit/support/LoggingTest.cpp
M orc-rt/test/unit/support/bind-test.cpp
M orc-rt/tools/ogre/CMakeLists.txt
M orc-rt/tools/ogre/ogre.cpp
M polly/lib/Support/SCEVAffinator.cpp
M polly/lib/Transform/ScheduleOptimizer.cpp
M polly/test/CodeGen/OpenMP/single_loop_with_loop_invariant_baseptr.ll
A polly/test/ScheduleOptimizer/simplify_deps_bounded_proximity.ll
M runtimes/CMakeLists.txt
M utils/bazel/MODULE.bazel.lock
M utils/bazel/linux_uapi.bzl
M utils/bazel/llvm-project-overlay/flang/lib/Optimizer/Builder/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/libc_build_rules.bzl
M utils/bazel/llvm-project-overlay/libc/startup/linux/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/startup/linux/x86_64/BUILD.bazel
A utils/bazel/llvm-project-overlay/lld/unittests/BUILD.bazel
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
M utils/docs/llvm_sphinx/ext/absolute_links.py
M utils/docs/llvm_sphinx/ext/absolute_links_test/markdown.md
Log Message:
-----------
Merge remote-tracking branch 'upstream/main' into users/mssefat/anti-hints-pr4-amdgpu-pre-ra
Commit: a6429f0089098f848a2a8bc8c60fd851052511f9
https://github.com/llvm/llvm-project/commit/a6429f0089098f848a2a8bc8c60fd851052511f9
Author: mssefat <syadus.sefat at gmail.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/anti-hints-mfma-waw.mir
Log Message:
-----------
Added new tests
Compare: https://github.com/llvm/llvm-project/compare/ab12cf92f6b1...a6429f008909
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