[all-commits] [llvm/llvm-project] abf102: [NFC][AMDGPU] Add tests for SCC live into a frame ...

[Domenic Nutile via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: abf10296ea7fcb250a6cfae307df39903ddad21d
      https://github.com/llvm/llvm-project/commit/abf10296ea7fcb250a6cfae307df39903ddad21d
  Author: Domenic Nutile <domenic.nutile at gmail.com>
  Date:   2026-09-29 (Tue, 29 Sep 2026)

  Changed paths:
    M llvm/test/CodeGen/AMDGPU/sgpr-spill-to-vmem-scc-clobber-reserved-exec-copy.mir

  Log Message:
  -----------
  [NFC][AMDGPU] Add tests for SCC live into a frame index user (#225196)

Pre-commit tests for the case where SCC is live into a frame index user
and
no SGPR is free to hold the V_READFIRSTLANE_B32 result. Scavenging one
emergency-spills an SGPR, and an SGPR spill flips EXEC with S_NOT_B64,
so the
EXEC flips land between the S_CMP_EQ_U32 that defines SCC and the read
of SCC
that follows, clobbering it in between.

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  Commit: a3ea30af9f485e0561cdb91221ea1663cba82813
      https://github.com/llvm/llvm-project/commit/a3ea30af9f485e0561cdb91221ea1663cba82813
  Author: Domenic Nutile <domenic.nutile at gmail.com>
  Date:   2026-09-29 (Tue, 29 Sep 2026)

  Changed paths:
    M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
    M llvm/test/CodeGen/AMDGPU/sgpr-spill-to-vmem-scc-clobber-reserved-exec-copy.mir

  Log Message:
  -----------
  [AMDGPU] Don't spill an SGPR while SCC is live in frame index lowering (#224080)

When SCC is live into a scalar frame index user, the scaling path avoids
SALU ops that write SCC by computing the address in a VGPR and reading
it
back with V_READFIRSTLANE_B32. If the destination of that readfirstlane
is
scavenged with spilling allowed, an AMDGPU SGPR spill writes inactive
lanes, so it flips EXEC with S_NOT_B64 and clobbers SCC. Instead,
scavenge
that register with AllowSpill=false.

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Compare: https://github.com/llvm/llvm-project/compare/92cdaa21f4f1...a3ea30af9f48

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