[all-commits] [llvm/llvm-project] cdbca6: [InferAddressSpaces] Check volatile support in the...
Alexey Bataev via All-commits
all-commits at lists.llvm.org
Tue Sep 29 04:04:04 PDT 2026
Branch: refs/heads/users/alexey-bataev/spr/slpsupport-runtime-alias-checks-versioning-for-blocks-in-loops
Home: https://github.com/llvm/llvm-project
Commit: cdbca60c7d5f41ec7f332341f97f16e4e2e221cb
https://github.com/llvm/llvm-project/commit/cdbca60c7d5f41ec7f332341f97f16e4e2e221cb
Author: Alex MacLean <amaclean at nvidia.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.h
M llvm/lib/Transforms/Scalar/InferAddressSpaces.cpp
M llvm/test/CodeGen/NVPTX/forward-ld-param.ll
A llvm/test/CodeGen/NVPTX/infer-volatile-address-spaces.ll
M llvm/test/CodeGen/NVPTX/local-stack-frame.ll
M llvm/test/CodeGen/NVPTX/lower-byval-args.ll
A llvm/test/Transforms/InferAddressSpaces/NVPTX/volatile.ll
Log Message:
-----------
[InferAddressSpaces] Check volatile support in the destination AS (#224702)
Perviously we nonsensically checked the old address space...
Avoid introducing a regression by adding ADDRESS_SPACE_SHARED_CLUSTER to
NVPTX hasVolatileVariant.
Commit: dc306a24fefef0e3cbde890bc25e30d4b753498f
https://github.com/llvm/llvm-project/commit/dc306a24fefef0e3cbde890bc25e30d4b753498f
Author: Farzon Lotfi <farzonlotfi at microsoft.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M clang/lib/CodeGen/CGExprScalar.cpp
M clang/test/CodeGenHLSL/BasicFeatures/MatrixElementTypeCast.hlsl
M clang/test/CodeGenHLSL/BasicFeatures/VectorElementwiseCast.hlsl
Log Message:
-----------
[HLSL] Build elementwise cast results from poison (#225591)
I noticed this unnecessary alloca while doing this pr:
https://github.com/llvm/llvm-project/pull/225519
The change is to initialize vector and matrix elementwise cast results
with poison instead of loading uninitialized temporary storage.
We do this because every result element is overwritten before use,
making the temporary allocation and load unnecessary.
Commit: c5f99a117bd799b43cd26880a9dccb96b33767ff
https://github.com/llvm/llvm-project/commit/c5f99a117bd799b43cd26880a9dccb96b33767ff
Author: Borys Perski <borys.perski at intel.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M clang/test/CodeGen/X86/sse41-builtins-constrained.c
M clang/test/CodeGen/X86/sse41-builtins.c
Log Message:
-----------
[clang][X86] Fix round builtins tests (#226708)
Fixed minor issues in round builtins tests. Noticed them while working on #215787.
Commit: a69848d73eb5134b86c56ed9937b6a91d84472f9
https://github.com/llvm/llvm-project/commit/a69848d73eb5134b86c56ed9937b6a91d84472f9
Author: Mircea Trofin <mtrofin at google.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M llvm/utils/profcheck-xfail.txt
Log Message:
-----------
[profcheck] Exclude find-first-byte-nested.ll (#227121)
We only fixed x86 for LoopIdiom. PR #225576 added a test that looks like
it's just exposing existing propagation issues.
Commit: 285a8656517a05596a91a8f104c9c6b592b8e144
https://github.com/llvm/llvm-project/commit/285a8656517a05596a91a8f104c9c6b592b8e144
Author: Nico Weber <thakis at chromium.org>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M llvm/utils/gn/build/BUILD.gn
M llvm/utils/gn/build/BUILDCONFIG.gn
M llvm/utils/gn/secondary/clang/tools/clang-repl/BUILD.gn
M llvm/utils/gn/secondary/clang/unittests/Interpreter/BUILD.gn
M llvm/utils/gn/secondary/llvm/tools/llc/BUILD.gn
M llvm/utils/gn/secondary/llvm/tools/lli/BUILD.gn
M llvm/utils/gn/secondary/llvm/tools/llvm-jitlink/BUILD.gn
M llvm/utils/gn/secondary/llvm/tools/opt/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/Analysis/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/CodeGen/CGPluginTest/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/ExecutionEngine/Orc/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/Passes/Plugins/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/Support/DynamicLibrary/BUILD.gn
M llvm/utils/gn/secondary/third-party/unittest/unittest.gni
Log Message:
-----------
[gn] Build executables without exported symbols on macOS (#227120)
Speeds up `clang --version` from 12 ms to 4 ms on my system. 8 ms faster
startup isn't a lot, but there's also no reason not to do it.
No intended behavior change.
Commit: a8debc5a8610b955b2756ea349630a00724450bc
https://github.com/llvm/llvm-project/commit/a8debc5a8610b955b2756ea349630a00724450bc
Author: Jeremy Kun <jkun at google.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M mlir/include/mlir/Target/Cpp/CppEmitter.h
Log Message:
-----------
Add registerToCppTranslation to CppEmmitter.h (#226337)
Currently if one wants to register `mlir-to-cpp` out of tree, they must
include `mlir/InitAllTranslations.h` and depend transitively on all
translation targets (in bazel, `@llvm-project//mlir:AllTranslations`).
This change adds the registration declaration to `CppEmitter.h` so that
one can depend just on the `MLIRTargetCpp` target (or
`@llvm-project//mlir:TargetCpp` in bazel).
This matches the organization of the SMTLib codegen registration in
`mlir/include/mlir/Target/SMTLIB/ExportSMTLIB.h` (though some other
targets like `IRDLToCpp` do it differently).
Commit: 6ab3be2e5efa370c8ca539b1f5a312d7e9b2fb65
https://github.com/llvm/llvm-project/commit/6ab3be2e5efa370c8ca539b1f5a312d7e9b2fb65
Author: Nico Weber <thakis at chromium.org>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M llvm/utils/gn/build/mac_sdk.gni
Log Message:
-----------
[gn] bump deployment target to macOS 13 (#227124)
macOS 13 is four years old by now.
This has the effect that lld starts defaulting to chained fixups with
this. Chained fixups reduces `clang --version` from 4 ms to 3.2 ms. (Not
that it matters.)
(Without #227120, chained fixups reduce `clang --version` from 12.5 ms
to 10.9 ms.)
No behavior change.
Commit: 4ca8a56ba3c579c01c3a9e30c6b972b8baaad208
https://github.com/llvm/llvm-project/commit/4ca8a56ba3c579c01c3a9e30c6b972b8baaad208
Author: Hugo Melder <service at hugomelder.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M clang/lib/CodeGen/CGObjCRuntime.cpp
A clang/test/CodeGenObjC/exceptions-seh.m
Log Message:
-----------
[ObjC][SEH] Fix clang crash when using finally statements (#176779)
When targeting a platform that does not have funclet-based EH, we push
the finally cleanup (normal edge) and catchall (unwind edge) onto the
EHStack _before_ pushing all catch handlers. The try statement is then
emitted and catch handlers popped from EHStack. Last, the finally
cleanup is popped from EHStack.
For funclet-based EH, we outline and push the finally funclet (of type
`NormalAndEHCleanup`) onto the EHStack _after_ pushing the catch
handlers and never pop it. This results in a crash during codegen when
we try to emit the catch handlers. Not popping the finally cleanup from
the EHStack results in incorrect calls to cleanup handlers in nested
try/catch/finally statements.
I fixed the two issues by:
1. Pushing the finally cleanup first, and
2. Popping it at the end of `CGObjCRuntime::EmitTryCatchStmt`.
Fixes #51899
Commit: c021bb407f8eb2e3dac57cae5760a258a4564f5c
https://github.com/llvm/llvm-project/commit/c021bb407f8eb2e3dac57cae5760a258a4564f5c
Author: Nico Weber <thakis at chromium.org>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
Log Message:
-----------
[gn] bump deployment target to macOS 13 (#227124)
macOS 13 is four years old by now.
This has the effect that lld starts defaulting to chained fixups with
this. Chained fixups reduces `clang --version` from 4 ms to 3.2 ms. (Not
that it matters.)
(Without #227120, chained fixups reduce `clang --version` from 12.5 ms
to 10.9 ms.)
No behavior change.
Commit: c87ad07c33661ca39ec512c834d01f17375673f4
https://github.com/llvm/llvm-project/commit/c87ad07c33661ca39ec512c834d01f17375673f4
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPMemoryUtils.cpp
Log Message:
-----------
[SLP][NFC]Fix build for MSVC compiler, NFC
Reported in https://lab.llvm.org/buildbot/#/builders/46/builds/42017
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/227129
Commit: 64907b6d3201f1755a149d029b3a65c4e0ee663f
https://github.com/llvm/llvm-project/commit/64907b6d3201f1755a149d029b3a65c4e0ee663f
Author: Joel Dice <joel.dice at akamai.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M libcxxabi/src/cxa_personality.cpp
M libunwind/include/unwind_wasm.h
M libunwind/src/Unwind-wasm.c
M llvm/include/llvm/IR/RuntimeLibcalls.td
M llvm/lib/CodeGen/WasmEHPrepare.cpp
M llvm/test/CodeGen/WebAssembly/eh-lsda.ll
M llvm/test/CodeGen/WebAssembly/exception-legacy.ll
M llvm/test/CodeGen/WebAssembly/exception.ll
M llvm/test/CodeGen/WebAssembly/wasm-eh-prepare.ll
Log Message:
-----------
fix Wasm exceptions + coop threading + shared libraries (#222747)
Prior to this commit, the combination of Wasm exception handling,
cooperative multithreading, and shared libraries was broken.
Specifically, the code generation in `WasmEHPrepare.cpp` involved
direct, cross-library access to `libunwind.so`'s thread-local
`__wasm_lpad_context` variable. However, the ABI used for cooperative
multithreading does not support cross-library access to thread-local
variables.
The solution used here is to add a new `_Unwind_GetWasmLPadContext`
function to `libunwind.so` and use that to get address of the
`__wasm_lpad_context` for the current thread, both in the code generated
by `WasmEHPrepare.cpp` and in the `__gxx_wasm_personality_v0` function
defined in `cxa_personality.cpp`. I've used this strategy
unconditionally for all targets, regardless of whether cooperative
multithreading and/or position-independent are enabled. If desired (e.g.
for performance or code complexity reasons), I could make it conditional
on both of those features being enabled and fall back to using
`__wasm_lpad_context` directly otherwise.
Co-authored-by: Derek Schuff <dschuff at chromium.org>
Commit: c6b15d38928d586064932c3cc26d8c777e104196
https://github.com/llvm/llvm-project/commit/c6b15d38928d586064932c3cc26d8c777e104196
Author: Sam Clegg <sbc at chromium.org>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M lld/test/wasm/check-arch-32-in-64.test
M lld/test/wasm/check-arch-64-in-32.test
M lld/wasm/InputFiles.cpp
Log Message:
-----------
[lld][WebAssembly] Fix error message when linking wasm64 file with -mwasm32 (#227091)
When `-mwasm32` is explicitly passed and a wasm64 object file is linked,
the error message previously stated:
"wasm32 object file can't be linked in wasm64 mode". Fix this to report
that the wasm64 object file cannot be linked in wasm32 mode.
Commit: 60f717946cb5ca911b6be22169b9bd646225c59f
https://github.com/llvm/llvm-project/commit/60f717946cb5ca911b6be22169b9bd646225c59f
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M .github/workflows/libcxx-pr-benchmark.yml
M .github/workflows/libcxx-pr-test-tools.yml
Log Message:
-----------
[libc++] Move test tools CI job back to k8s runner sets (#226564)
While the issue with k8s runners in #226230 is still not resolved, it is
better to target the k8s runners and get transient failures than to
target the old runners and have the jobs hang forever (there seems to be
no runners registered in llvm-premerge-libcxx-runners).
Co-authored-by: Aiden Grossman <aidengrossman at google.com>
Commit: 6fee55d8425e735e652968007ee0d6bc35aa6f26
https://github.com/llvm/llvm-project/commit/6fee55d8425e735e652968007ee0d6bc35aa6f26
Author: Ron Green [NVIDIA] <rogreen at nvidia.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M flang/include/flang/Support/Fortran-features.h
M flang/lib/Semantics/check-declarations.cpp
A flang/test/Semantics/bind-c20.f90
A flang/test/Semantics/bind-c21.f90
Log Message:
-----------
[flang][Semantics] Warn on BIND(C) interfaces with assumed-shape/rank dummies (#225965)
## Motivation
Fortran 2018 §18.3.6 requires assumed-shape, deferred-shape, and
assumed-rank `BIND(C)` dummy arguments to be passed using a CFI
descriptor (`CFI_cdesc_t`). Some existing C/C++ interfaces predate this
requirement and expect such an argument to be passed by bare address
instead. Declaring a `BIND(C)` Fortran interface against such code
currently produces a silent calling-convention mismatch — no diagnostic
warns the user that the ABI they've declared doesn't match what
pre-2018 C/C++ code expects.
## What this PR does
Adds a portability warning in `CheckSubprogram`
(`flang/lib/Semantics/check-declarations.cpp`) that fires when a
`BIND(C)` interface declares an assumed-shape or assumed-rank dummy
argument, under a new `UsageWarning` category, `BindCArrayDescriptor`.
The warning is **off by default** and enabled by `-pedantic` (or
individually via `-Wbind-c-array-descriptor`), matching the existing
precedent set by other portability-only categories in the same enum
(e.g. `CharacterInteroperability`, `LogicalVsCBool`).
To avoid firing on compiler-provided runtime libraries that
legitimately dispatch through CFI-descriptor-consuming `BIND(C)`
wrappers (e.g. an OpenACC runtime module's internal specific procedures
for generic entry points like `acc_copyin`), the warning is suppressed
when the `BIND(C)` binding name — explicit or the implicit default —
starts with `_`, which marks an implementation-internal interface
rather than genuine external interoperability.
This is a **pure diagnostic** — no lowering, `LoweringOptions`, or
codegen changes of any kind. It does not alter how any argument is
actually passed.
## Test plan
- `flang/test/Semantics/bind-c20.f90`: assumed-shape and assumed-rank
dummies warn under `-pedantic` (both default and explicit `BIND(C)
NAME=`); explicit-shape dummies and a leading-underscore binding name
do not.
- `flang/test/Semantics/bind-c21.f90`: the same
assumed-shape/assumed-rank
interfaces produce no diagnostic without `-pedantic`.
- Existing `flang/test/Semantics` and `flang/test/Lower/HLFIR` lit
suites
(1752 tests) pass.
- Verified no false positives against real OpenACC (`use openacc`,
`-acc=gpu`) and CUDA Fortran (`use cudafor`, `-cuda`) runtime API
calls, plus a static scan of all `cu*.mod` runtime interface modules
confirming none use the assumed-shape/rank `BIND(C)` pattern this
warning targets outside the excluded underscore-prefixed convention.
- Full `precommit.py` regression run found zero regressions
attributable to this change (all observed failures traced to an
unrelated, pre-existing upstream crash, confirmed via an A/B control
build with this change fully reverted).
🤖 Generated with [Claude Code](https://claude.com/claude-code)
Commit: f95e5ea5a5eb719e05754de235aaba8e20e6a36b
https://github.com/llvm/llvm-project/commit/f95e5ea5a5eb719e05754de235aaba8e20e6a36b
Author: Nico Weber <thakis at chromium.org>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M llvm/utils/gn/secondary/clang/include/clang/Config/BUILD.gn
Log Message:
-----------
[gn] Fix Interpreter/emulated-tls.cpp on mac (#227132)
In, #225475 (5dfe8605911e), CLANG_HAVE_EMUTLS_GET_ADDRESS got hardcoded
to 0 in the GN build, while the CMake build has a config-time check for
__emutls_get_address.
On mac and linux, compiler-rt provides that symbol, so set
CLANG_HAVE_EMUTLS_GET_ADDRESS to 1 there. That way, __emutls_get_address
is force-linked as absolute symbol and things are happy.
(With it set to 0. clang-repl dlsym()s for the symbol, which works on
Linux where it's found in libgcc_s.so.1, but it doesn't work on mac.)
Commit: 9f009662f3fba1d8955e5e79261c60c2f98d24b6
https://github.com/llvm/llvm-project/commit/9f009662f3fba1d8955e5e79261c60c2f98d24b6
Author: Delaram Talaashrafi <dtalaashrafi at nvidia.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M mlir/include/mlir/Dialect/OpenACC/OpenACCCGAttributes.td
M mlir/include/mlir/Dialect/OpenACC/OpenACCUtilsCG.h
M mlir/lib/Dialect/OpenACC/Transforms/ACCComputeLowering.cpp
M mlir/lib/Dialect/OpenACC/Utils/OpenACCUtilsCG.cpp
M mlir/test/Dialect/OpenACC/acc-compute-lowering-loop.mlir
M mlir/unittests/Dialect/OpenACC/OpenACCUtilsCGTest.cpp
Log Message:
-----------
[mlir][OpenACC] Record gang(static:) chunk size on lowered loops (#227037)
Lower OpenACC `gang(static:)` through compute lowering as
`acc.chunk_size`. A constant size is stored directly; `static:*` and a
non-constant size are recorded as -1. `gang(static:)` also maps to gang
dimension 1.
Commit: bc1a55167c5b0c32a755ce51597bd35a9db85660
https://github.com/llvm/llvm-project/commit/bc1a55167c5b0c32a755ce51597bd35a9db85660
Author: Alex MacLean <amaclean at nvidia.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
M llvm/lib/Target/NVPTX/NVPTXUtilities.h
M llvm/test/CodeGen/NVPTX/call_bitcast_byval.ll
M llvm/test/CodeGen/NVPTX/callchain.ll
M llvm/test/CodeGen/NVPTX/empty-type.ll
A llvm/test/CodeGen/NVPTX/fp-global.ll
M llvm/test/CodeGen/NVPTX/i1-param.ll
M llvm/test/CodeGen/NVPTX/managed.ll
M llvm/test/CodeGen/NVPTX/noreturn.ll
A llvm/test/CodeGen/NVPTX/odd-integer-width.ll
M llvm/test/CodeGen/NVPTX/param-align.ll
A llvm/test/CodeGen/NVPTX/ptr-global.ll
M llvm/test/CodeGen/NVPTX/vector-global.ll
M llvm/test/DebugInfo/NVPTX/debug-info.ll
Log Message:
-----------
[NVPTX] Consolidate AsmPrinter type and global variable printing (#222240)
Commit: 5b3ae0006a69c8a6c3cb8c1dddf3556f413aa037
https://github.com/llvm/llvm-project/commit/5b3ae0006a69c8a6c3cb8c1dddf3556f413aa037
Author: Alex MacLean <amaclean at nvidia.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
Log Message:
-----------
[NVPTX] Consolidate AsmPrinter type and global variable printing (#222240)
Commit: 1637562456ab8561fa2602a438604cac3ddf4bd0
https://github.com/llvm/llvm-project/commit/1637562456ab8561fa2602a438604cac3ddf4bd0
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPShuffleAnalysis.h
Log Message:
-----------
[SLP][NFC]Fix GCC 7 ICE and unused binding warnings, NFC
Reported in https://lab.llvm.org/buildbot/#/builders/116/builds/31627
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/227151
Commit: e59523e9a9dece16edb17341ee14ade7be8753a9
https://github.com/llvm/llvm-project/commit/e59523e9a9dece16edb17341ee14ade7be8753a9
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
Log Message:
-----------
[SLP][NFC]Fix GCC 7 ICE and unused binding warnings, NFC
Reported in https://lab.llvm.org/buildbot/#/builders/116/builds/31627
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/227151
Commit: f85fe6efc523b4f9d2ecb11ccaeefef49ab5e6f3
https://github.com/llvm/llvm-project/commit/f85fe6efc523b4f9d2ecb11ccaeefef49ab5e6f3
Author: Ian Anderson <iana at apple.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M clang/test/Driver/Inputs/MacOSX15.0.sdk/SDKSettings.json
M clang/test/Driver/Inputs/MacOSX15.1.sdk/SDKSettings.json
M clang/test/Driver/modulemap-allow-subdirectory-search.c
M clang/test/InstallAPI/Inputs/MacOSX13.0.sdk/SDKSettings.json
Log Message:
-----------
[NFC][darwin][test] Fix the hand spacing in the SDKSettings files (#227133)
I hand spaced the VersionMap keys in the SDKSettings files to make it
easier to see where the gaps are where a version of Xcode updated one
SDK but not the other. I almost got them all right, but mis-spaced one
in macOS_iOSMac.
Commit: d718391361333d378a5bce643bbdef553f81c203
https://github.com/llvm/llvm-project/commit/d718391361333d378a5bce643bbdef553f81c203
Author: Razvan Lupusoru <razvan.lupusoru at gmail.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M flang/lib/Semantics/check-acc-structure.cpp
M flang/lib/Semantics/check-acc-structure.h
A flang/test/Semantics/OpenACC/acc-routine-loop-nesting.f90
Log Message:
-----------
[flang][acc] Warn when a loop is above its routine parallelism level (#227041)
OpenACC spec allows a routine to parent a loop at its own parallelism
level or below. A higher level is not allowed: gang inside a worker
routine, gang or worker inside a vector routine, gang, worker, or vector
inside a seq routine, and a gang dimension above the routine's gang
dimension. A device-specific routine clause counts the same way.
Flang accepted these loops with no diagnostic. Warn that the clause is
ignored. A loop at the same level or below is left alone, and illegal
nesting of loops remains an error.
Commit: fbac8e1ff3b8b733183e677f49be73ab2210d7df
https://github.com/llvm/llvm-project/commit/fbac8e1ff3b8b733183e677f49be73ab2210d7df
Author: Akhil Goel <akhil.goel at intel.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
M llvm/test/CodeGen/SPIRV/legalization/signed-narrow-int.ll
Log Message:
-----------
[SPIR-V] Sign extend narrow G_SMIN/G_SMAX operands and mask sign sensitive results (#226957)
This PR includes `G_SMIN` and `G_SMAX` to the list of sign sensitive
ops. It also masks the result of the sign sensitive ops to their
original widths with a bitwise AND because the later users assume the
upper bits are zero and without masking they read the wrong value.
Commit: 0ec4a7fe84cde933c044dafdcf5cfd983f7d086c
https://github.com/llvm/llvm-project/commit/0ec4a7fe84cde933c044dafdcf5cfd983f7d086c
Author: Med Ismail Bennani <ismail at bennani.ma>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M lldb/packages/Python/lldbsuite/test/lldbplatformutil.py
Log Message:
-----------
[lldb/test] Normalize appletvos to tvos in getPlatform() (#227138)
Mirror the existing `iphoneos` -> `ios` SDK-name normalization for
`tvOS`. Without it, an `--apple-sdk` value derived from "appletvos" made
`getPlatform()` return "appletvos", which isn't in
`lldbplatform.__name_lookup`, so `platformIsDarwin(`) returned `False`
and `finalize_build_dictionary` KeyError'd before any `remote-tvos` test
could build.
Signed-off-by: Med Ismail Bennani <ismail at bennani.ma>
Commit: c894e63329c144702bd560a8807d17b489e0484b
https://github.com/llvm/llvm-project/commit/c894e63329c144702bd560a8807d17b489e0484b
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M .github/workflows/libc-fullbuild-tests.yml
M .github/workflows/libc-overlay-tests.yml
Log Message:
-----------
[Github] Temporary fix for #226230 (#227147)
We are seeing this issue in the libc++ runner sets and it can presumably
pop up in the libc runner sets as well in the case of an abnormally long
clone operation.
Commit: b1faf8bc3ebbbe70daaac47a5fcd49006be3709e
https://github.com/llvm/llvm-project/commit/b1faf8bc3ebbbe70daaac47a5fcd49006be3709e
Author: Med Ismail Bennani <ismail at bennani.ma>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M lldb/packages/Python/lldbsuite/test/lldbplatform.py
Log Message:
-----------
[lldb/test] Register xros (visionOS) as a Darwin platform (#227142)
`lldbplatform.py` never registered `xros` at all: no enum value, no
`__name_lookup` entry, and it was absent from `__darwin_embedded`/
`darwin_all`. As a result, `platformIsDarwin()` returned `False` for
`xros`, and `finalize_build_dictionary`'s fallback branch, which indexes
`platform_name_to_uname` by the raw platform name, would `KeyError`
before any visionOS test could build.
Add `xros` alongside the other embedded Darwin platforms so it's
recognized the same way `ios`/`tvos`/`watchos`/`bridgeos` already are.
Signed-off-by: Med Ismail Bennani <ismail at bennani.ma>
Commit: 619028d062d90579edb0e80fd2c0a870f83cce84
https://github.com/llvm/llvm-project/commit/619028d062d90579edb0e80fd2c0a870f83cce84
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M llvm/test/lit.cfg.py
M llvm/utils/profcheck-xfail.txt
Log Message:
-----------
[ProfCheck] Exclude DirectX (#227157)
I don't think anyone runs profiling on DirectX, so exclude it for now.
Also move AMDGPU to the normal exclusion list given there are efforts
around PGO for AMDGPU currently.
Commit: 7b5ec23c6053560e306fce71a4332e2b9793dd7e
https://github.com/llvm/llvm-project/commit/7b5ec23c6053560e306fce71a4332e2b9793dd7e
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
R llvm/test/tools/llvm-readobj/ELF/RISCV/eflags-abi.test
A llvm/test/tools/llvm-readobj/ELF/RISCV/eflags.test
Log Message:
-----------
[RISCV][llvm-readobj] Generalize the eflags-abi test to cover all of the eflags. NFC (#227152)
Assisted-by: Claude
Commit: 78f2beb7655e19b3f5a8c55dda3f7b8b20771bed
https://github.com/llvm/llvm-project/commit/78f2beb7655e19b3f5a8c55dda3f7b8b20771bed
Author: Samarth Narang <70980689+snarang181 at users.noreply.github.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M mlir/include/mlir/Dialect/SCF/IR/SCFOps.td
M mlir/lib/Conversion/SCFToControlFlow/SCFToControlFlow.cpp
M mlir/lib/Conversion/SCFToGPU/SCFToGPU.cpp
M mlir/lib/Conversion/SCFToOpenMP/SCFToOpenMP.cpp
M mlir/lib/Dialect/Async/Transforms/AsyncParallelFor.cpp
M mlir/lib/Dialect/SCF/IR/SCF.cpp
M mlir/lib/Dialect/SCF/Transforms/ParallelForToNestedFors.cpp
M mlir/lib/Dialect/SCF/Transforms/ParallelLoopCollapsing.cpp
M mlir/lib/Dialect/SCF/Transforms/ParallelLoopFusion.cpp
M mlir/lib/Dialect/SCF/Transforms/ParallelLoopTiling.cpp
M mlir/test/Conversion/SCFToControlFlow/convert-to-cfg.mlir
M mlir/test/Conversion/SCFToGPU/parallel_loop.mlir
A mlir/test/Conversion/SCFToOpenMP/scf-to-openmp-unsigned.mlir
M mlir/test/Dialect/Async/async-parallel-for-async-dispatch.mlir
M mlir/test/Dialect/SCF/ops.mlir
M mlir/test/Dialect/SCF/parallel-loop-fusion.mlir
M mlir/test/Dialect/SCF/parallel-loop-tiling-inbound-check.mlir
M mlir/test/Dialect/SCF/parallel-to-nested-fors.mlir
A mlir/test/Transforms/parallel-loop-collapsing-unsigned.mlir
Log Message:
-----------
[mlir][scf] Add unsignedCmp to scf.parallel and use it in the tiling in-bound check (#226130)
This change mirrors `scf.for` where `scf.parallel` gets an `unsignedCmp`
unit attribute, and every pass that rebuilds or lowers a `scf.parallel`
has to respect it:
- Propagate where a loop is rebuilt from another, such as parallel loop
tiling, parallel loop fusion (which also refuses to fuse loops of
different signedness), parallel-to-nested-fors and SCF-to-CF lowering.
- Decline where the bound arithmetic assumes signed values, such as
SCF-to-GPU, SCF-to-OpenMP, async-parallel-for and the
parallel-loop-collapsing test pass.
Fixes #223233
Commit: 9a0c255ce1efbd80ef501e8151d123876fa4b5d4
https://github.com/llvm/llvm-project/commit/9a0c255ce1efbd80ef501e8151d123876fa4b5d4
Author: Owen Rodley <orodley at google.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M clang/lib/CodeGen/CodeGenPGO.cpp
M compiler-rt/test/profile/instrprof-thinlto-indirect-call-promotion.cpp
M llvm/include/llvm/ProfileData/InstrProf.h
M llvm/lib/ProfileData/InstrProf.cpp
M llvm/lib/Transforms/IPO/MemProfContextDisambiguation.cpp
M llvm/lib/Transforms/Instrumentation/InstrProfiling.cpp
M llvm/lib/Transforms/Instrumentation/MemProfUse.cpp
M llvm/lib/Transforms/Instrumentation/PGOInstrumentation.cpp
M llvm/lib/Transforms/Scalar/JumpTableToSwitch.cpp
M llvm/test/Instrumentation/cgprofile.ll
M llvm/test/Transforms/JumpTableToSwitch/profile-no-guid-metadata.ll
M llvm/test/Transforms/JumpThreading/thread-prob-1.ll
M llvm/test/Transforms/PGOProfile/Inputs/cspgo_bar_sample.ll
M llvm/test/Transforms/PGOProfile/Inputs/thinlto_cspgo_bar_gen.ll
M llvm/test/Transforms/PGOProfile/Inputs/thinlto_cspgo_bar_use.ll
M llvm/test/Transforms/PGOProfile/icp_invoke.ll
M llvm/test/Transforms/PGOProfile/icp_invoke_nouse.ll
M llvm/test/Transforms/PGOProfile/thinlto_indirect_call_promotion.ll
M llvm/test/tools/gold/X86/Inputs/thinlto_cspgo_bar.ll
A llvm/test/tools/llvm-profdata/Inputs/guid-roundtrip.c
A llvm/test/tools/llvm-profdata/Inputs/guid-roundtrip.proftext
A llvm/test/tools/llvm-profdata/guid-roundtrip.test
M llvm/unittests/ProfileData/InstrProfTest.cpp
Log Message:
-----------
[InstrProf] Replace !PGOFuncName and !PGOName metadata with !guid (#214134)
!PGOFuncName and !PGOName metadata were attached to internal functions
and vtables during profile annotation to record their original
"<file>;<name>" PGO names before ThinLTO promoted and renamed them. In
post-link LTO passes, InstrProfSymtab read that metadata back so profile
records keyed by the original name's hash could still find the renamed
IR object.
Global objects now carry stable !guid metadata assigned before LTO
renaming, which records the MD5 hash of the original PGO name directly.
See: https://discourse.llvm.org/t/rfc-keep-globalvalue-guids-stable/84801
Use !guid instead of maintaining separate PGO name metadata:
- Stop emitting and reading !PGOFuncName and !PGOName in Clang and
PGOInstrumentation, and remove the metadata helper functions
(createPGOFuncNameMetadata, createPGONameMetadata,
getPGOFuncNameMetadata, and the metadata name getters).
- Unify getIRPGOFuncName(const Function &) and
getPGOName(const GlobalVariable &) into
getIRPGOObjectName(const GlobalObject &).
- In InstrProfSymtab::addFuncWithName and addVTableWithName, key each
name by its own hash as before, and also insert the object's assigned
GUID into MD5FuncMap / MD5VTableMap when it differs from the PGO name
hash. This lets lookups find functions and vtables that LTO has
renamed while preserving lookups by current, deprecated, and canonical
names.
- Remove obsolete !PGOFuncName metadata from test inputs, update the
ThinLTO ICP tests to check for !guid, and add symtab unit tests and an
llvm-profdata text/indexed round-trip test.
Assisted-by: Antigravity
Commit: eabb90030e7908fd2f15d77198c8b1e88f5463a4
https://github.com/llvm/llvm-project/commit/eabb90030e7908fd2f15d77198c8b1e88f5463a4
Author: Harrison Hao <57025411+harrisonGPU at users.noreply.github.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
M llvm/test/Transforms/InstCombine/AMDGPU/llvm.amdgcn.sudot.ll
Log Message:
-----------
[AMDGPU] Canonicalize constant operands of sudot intrinsics (#226478)
Move a constant multiplicand and its sign flag to the second operand.
For example:
```
sudot4(true, 1, false, x, acc, clamp)
->
sudot4(false, x, true, 1, acc, clamp)
```
Commit: f896873b4dddca59ec3c18487cf3f1cf6545df1e
https://github.com/llvm/llvm-project/commit/f896873b4dddca59ec3c18487cf3f1cf6545df1e
Author: Hongyu Chen <xxs_chy at outlook.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M clang/lib/Headers/riscv_packed_simd.h
M clang/test/CodeGen/RISCV/rvp-intrinsics.c
M cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoP.td
M llvm/test/CodeGen/RISCV/rvp-simd-32.ll
Log Message:
-----------
[RISCV][P-ext] Support the missing packed pair (#226992)
This patch supports the packed pair for v2i16.
Some are inconsistent with the spec because existing shuffle-lowering
transforms them into equivalent narrowing shifts or zips.
Commit: 31d7b51dbd5a8a5e58631a3c77421209f562ea5c
https://github.com/llvm/llvm-project/commit/31d7b51dbd5a8a5e58631a3c77421209f562ea5c
Author: aokblast <aokblast at FreeBSD.org>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M clang/docs/ReleaseNotes.md
M clang/test/AST/ByteCode/new-delete.cpp
R clang/test/SemaCXX/new-nothrow-by-value.cpp
Log Message:
-----------
[Clang] Add missing release note entry in #226753 (#227078)
As per the feedback from #226753, we add release note for GH-212211.
Also move the test to new-delete.cpp.
Assisted-by: Claude
Commit: 60ac6298c2e70aeeeac1ae388024bbe30f25784a
https://github.com/llvm/llvm-project/commit/60ac6298c2e70aeeeac1ae388024bbe30f25784a
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Scalar/TailRecursionElimination.cpp
A llvm/test/Transforms/TailCallElim/return-value-select-pgo.ll
M llvm/utils/profcheck-xfail.txt
Log Message:
-----------
[TailCallElim] Add profile annotations to return value selects
Tail call elimination in some cases can create selects on possible
return values conditioned on whether or not execution is currently in
what was a recursive call. That is equal to the probability with which
we recurse, which in turn can be computed from the block frequencies of
blocks that recurse and blocks that directly return.
Reviewers: mtrofin
Reviewed By: mtrofin
Pull Request: https://github.com/llvm/llvm-project/pull/202518
Commit: dae88f2450b03f9a123cd681a7f698f67bde9ece
https://github.com/llvm/llvm-project/commit/dae88f2450b03f9a123cd681a7f698f67bde9ece
Author: Aman Maurya <amanmaurya9209 at gmail.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenCoroutine.cpp
M clang/lib/CIR/CodeGen/CIRGenExprAggregate.cpp
A clang/test/CIR/CodeGenCoroutines/coro-agg.cpp
Log Message:
-----------
[CIR] Support aggregate co_await / co_yield in AggExprEmitter (#225412)
Support evaluating `co_await` and `co_yield` expressions whose result is
an aggregate type in `AggExprEmitter`.
Fixes #225317
Commit: 3b0b6d892bdf4eecf4d6fbccf26c6d91fec2d164
https://github.com/llvm/llvm-project/commit/3b0b6d892bdf4eecf4d6fbccf26c6d91fec2d164
Author: theRonShark <ron.lieberman at amd.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M clang/include/clang/CodeGen/CodeGenAction.h
M clang/include/clang/Interpreter/Interpreter.h
M clang/lib/CodeGen/BackendConsumer.h
M clang/lib/CodeGen/CodeGenAction.cpp
M clang/lib/Interpreter/CMakeLists.txt
M clang/lib/Interpreter/DeviceOffload.cpp
M clang/lib/Interpreter/DeviceOffload.h
M clang/lib/Interpreter/Interpreter.cpp
M clang/unittests/Basic/CMakeLists.txt
R clang/unittests/Basic/TargetIDTest.cpp
Log Message:
-----------
Revert "releand "[clang-repl] Implement IncrementalHIPDeviceParser for HIP device compilation"" (#227123)
Reverts llvm/llvm-project#226930
AMD author has an additional step to perform, that is still needed.
in contact with Author.
Commit: ec1b3b10a71c2181b0dfb90f1178e2e739680e02
https://github.com/llvm/llvm-project/commit/ec1b3b10a71c2181b0dfb90f1178e2e739680e02
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M flang/include/flang/Optimizer/Builder/CUDAIntrinsicCall.h
M flang/include/flang/Optimizer/Builder/CUFCommon.h
M flang/include/flang/Optimizer/Dialect/CUF/CUFOps.td
M flang/include/flang/Optimizer/Transforms/Passes.td
M flang/lib/Optimizer/Builder/CUDAIntrinsicCall.cpp
M flang/lib/Optimizer/Builder/CUFCommon.cpp
M flang/lib/Optimizer/Transforms/CMakeLists.txt
R flang/lib/Optimizer/Transforms/CUDA/CUFFunctionRewrite.cpp
M flang/lib/Optimizer/Transforms/CUDA/CUFOpConversion.cpp
M flang/lib/Optimizer/Transforms/CUDA/CUFOpConversionLate.cpp
R flang/test/Fir/CUDA/cuda-function-rewrite.mlir
A flang/test/Fir/CUDA/cuda-on-device.mlir
M flang/test/Fir/cuf.mlir
A flang/test/Lower/CUDA/cuda-on-device.cuf
Log Message:
-----------
[flang][cuda] Add cuf.on_device op and lower to it (#227089)
Replace the CUFFunctionRewrite pass, which matched fir.call names and
folded them to constants, with a cuf.on_device operation emitted when
the intrinsic is lowered. CUFOpConversion folds the operation once the
code is in its host or device context, and leaves the host copy of an
OpenACC routine unfolded so the device clone is not baked to false. Any
operation that remains is folded by the late CUF conversion, and the
rewrite pass is dropped from the pipeline.
Commit: eb3163c52e9fbea9c579c16bdb881655fb6536d5
https://github.com/llvm/llvm-project/commit/eb3163c52e9fbea9c579c16bdb881655fb6536d5
Author: forking-google-bazel-bot[bot] <265904573+forking-google-bazel-bot[bot]@users.noreply.github.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/flang/lib/Optimizer/Builder/BUILD.bazel
Log Message:
-----------
[Bazel] Fixes ec1b3b1 (#227180)
This fixes ec1b3b10a71c2181b0dfb90f1178e2e739680e02 (#227089).
Buildkite error link:
https://buildkite.com/llvm-project/upstream-bazel/builds?commit=ec1b3b10a71c2181b0dfb90f1178e2e739680e02
Co-authored-by: Google Bazel Bot <google-bazel-bot at google.com>
Commit: 2f13592fb1dee32d498c3ec2993d5f109e614abe
https://github.com/llvm/llvm-project/commit/2f13592fb1dee32d498c3ec2993d5f109e614abe
Author: Prajit Rahul <prajitrahul05 at gmail.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M mlir/include/mlir/Dialect/ControlFlow/IR/ControlFlowOps.td
M mlir/lib/Dialect/ControlFlow/IR/ControlFlowOps.cpp
M mlir/test/Dialect/ControlFlow/canonicalize.mlir
M mlir/test/Dialect/ControlFlow/invalid.mlir
M mlir/test/Dialect/ControlFlow/ops.mlir
Log Message:
-----------
[mlir][cf] Fix cf.switch round-trip for case values wider than 64 bits (#221490)
The `cf.switch` parser reads case values into `int64_t`, and its printer
uses `APInt::getLimitedValue()`, preventing values wider than 64 bits
from round-tripping. Printing negative narrow values as unsigned can
also trigger an assertion when reparsing.
Parse case values into `APInt` and print them directly, so wide and
negative values round-trip correctly. Accept signed or unsigned literals
that fit the switch operand’s bit width, and report an error for values
that do not.
Add regression tests for wide and negative values, integer-width
boundaries, out-of-range diagnostics, and case selection after parsing.
Fixes #220609
Assisted-by: Codex
Commit: fddfd6f01e3f203df3fc1d7fc7769bcb9745d0fa
https://github.com/llvm/llvm-project/commit/fddfd6f01e3f203df3fc1d7fc7769bcb9745d0fa
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M clang/lib/AST/ByteCode/Context.cpp
M clang/lib/AST/ByteCode/Context.h
M clang/lib/AST/ByteCode/EvalEmitter.cpp
M clang/lib/AST/ByteCode/EvalEmitter.h
A clang/lib/AST/ByteCode/EvalSettings.h
M clang/lib/AST/ByteCode/InterpState.cpp
M clang/lib/AST/ByteCode/InterpState.h
M clang/lib/AST/ExprConstant.cpp
Log Message:
-----------
[clang][bytecode] Add `EvalSettings` struct and replace parent `State` (#226175)
We currently always construct a full `EvalInfo` when using the bytecode
interpreter, we then pass it to the `evaluate*` function, which only
copies a few values from it.
Introduce a new `EvalSettings` struct that we pass instead of a `State`.
This is cheaper to construct and we only pass what's needed. There is
one `evaluateAsRValue` overload left that takes a parent `State`, that
will be removed in a subsequent patch.
Commit: f4085066128ac709f25c206c9701285f60a0bf83
https://github.com/llvm/llvm-project/commit/f4085066128ac709f25c206c9701285f60a0bf83
Author: Aman Maurya <amanmaurya9209 at gmail.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenExprAggregate.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.cpp
M clang/test/CIR/CodeGen/pack-indexing.cpp
Log Message:
-----------
[CIR] Support PackIndexingExpr for LValue and Aggregates (#227040)
Support `PackIndexingExpr` in `CIRGenFunction::emitLValue` and
`AggExprEmitter` by visiting its selected expression, matching classic
Clang codegen (`CGExpr.cpp` and `CGExprAgg.cpp`) and completing
`PackIndexingExpr` support across all CIR expression emitters.
Fixes #226928
Assisted by Antigravity and Gemini
Commit: 3376b1f4b2f4db8c7f5c94323e6c9a730d974247
https://github.com/llvm/llvm-project/commit/3376b1f4b2f4db8c7f5c94323e6c9a730d974247
Author: Fangrui Song <i at maskray.me>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M lld/test/ELF/pre_init_fini_array.s
M llvm/lib/MC/ELFObjectWriter.cpp
M llvm/test/CodeGen/AMDGPU/lower-ctor-dtor.ll
M llvm/test/MC/AsmParser/section_names.s
M llvm/test/MC/ELF/section.s
Log Message:
-----------
[MC,ELF] Set sh_entsize for SHT_INIT_ARRAY/FINI_ARRAY/PREINIT_ARRAY (#226875)
Match GNU Assembler: set sh_entsize to 4/8, regardless of sh_size. This
is mostly cosmetic: sh_entsize is not a useful member for non-merge
sections.
When clang-produced and GCC-produced objects are linked together, the
mismatch makes lld's output sh_entsize 0.
Commit: c5a5943133d558b7bae36fe3074e7777178e7a6e
https://github.com/llvm/llvm-project/commit/c5a5943133d558b7bae36fe3074e7777178e7a6e
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M llvm/lib/Target/X86/X86InstCombineIntrinsic.cpp
M llvm/test/Transforms/InstCombine/X86/x86-avx512-inseltpoison.ll
M llvm/utils/profcheck-xfail.txt
Log Message:
-----------
[X86][InstCombine] Fix profcheck failures (#227183)
When optimizing some AVX512 masked intrinsics, we would create a select
with a condition derived from the mask. We cannot infer the distribution
of this synthesized condition, so mark it unknown to make profcheck
green.
Commit: 9fe649af67007493c02108b484c8b9259e3d522e
https://github.com/llvm/llvm-project/commit/9fe649af67007493c02108b484c8b9259e3d522e
Author: Vladimir Shiryaev <w at tagolog.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M llvm/lib/CAS/UnifiedOnDiskCache.cpp
A llvm/test/tools/llvm-cas/validate-if-needed.test
Log Message:
-----------
[CAS] Close the stderr temp file of the out-of-process validator (#226844)
Commit: ef45ca75ce721745b997db165f18e4fdf9e93294
https://github.com/llvm/llvm-project/commit/ef45ca75ce721745b997db165f18e4fdf9e93294
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M clang/test/CodeGen/RISCV/rvp-intrinsics.c
Log Message:
-----------
[RISCV] Add common check-prefix to rvp-intrinsics.c. NFC (#227044)
A large number of test cases have the same IR for RV32 and RV64.
Commit: 876ff1506413684af43a3a61fd4ca3b999000aff
https://github.com/llvm/llvm-project/commit/876ff1506413684af43a3a61fd4ca3b999000aff
Author: Abinaya Saravanan <asaravan at qti.qualcomm.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M llvm/lib/Target/Hexagon/HexagonDepInstrInfo.td
A llvm/test/MC/Hexagon/v79-nontemporal.s
Log Message:
-----------
Add v79 scalar non-temporal forms. (#226017)
Also add support for the non-temporal forms of dcfetch and dczeroa.
Fixes https://github.com/llvm/llvm-project/issues/221485
Commit: ba67350bf808d8bef21cc2d59d7bcd0396adc29d
https://github.com/llvm/llvm-project/commit/ba67350bf808d8bef21cc2d59d7bcd0396adc29d
Author: Nico Weber <thakis at chromium.org>
Date: 2026-09-28 (Mon, 28 Sep 2026)
Changed paths:
M clang/lib/Sema/SemaConcept.cpp
M clang/test/CXX/temp/temp.constr/temp.constr.normal/p1.cpp
Log Message:
-----------
[clang] Consistently cache failed constraint normalization (#227086)
Previously, if substituting the parameter mappings of a normalized
constraint failed, Sema::getNormalizedAssociatedConstraints() returned
nullptr, but it stored the partially substituted normal form in
NormalizationCache. So the first lookup for such a declaration failed,
but every later lookup returned the broken normal form, and subsumption
checking and the ambiguous-constraint diagnostics then continued with
it.
I believe this wasn't intentional:
- Before #161671 (e9972debc98c), normalization was a single step, and a
failure was cached as nullptr.
- #161671 added the parameter mapping substitution step. It inserted the
normal form into the cache before substituting, and returned nullptr if
the substitution then failed, leaving the non-null normal form in the
cache.
- #165352 (2984a8db804e) moved the insertion after the substitution to
not use an invalidated iterator, but kept inserting the normal form if
the substitution failed.
To fix this, cache failed substitution as nullptr, like a failed
normalization.
As a consequences we don't emit the diagnostics that were only emitted
because the second lookup continued:
- A second "'type name' declared as a pointer to a reference" error
(with its notes) for the same broken concept. For
template<typename T> concept Foo = True<T*>;
template<typename T> concept Bar = Foo<T&>;
template<typename T> requires Bar<T> struct S { };
template<typename T> requires Bar<T> && true struct S<T> { };
the error got reported once for the partial specialization, and also for
the primary template after. Now, we only have the first report.
- A "similar constraint expressions not considered equivalent" note and
its "similar constraint expression here" note, which we computed from
the broken normal form. The actual problem in that test is the broken
constraint, which is still diagnosed.
This also makes it possible to key the normalization cache by constraint
expression without changing which diagnostics are emitted for failures,
which I want to do in a follow-up.
Commit: 633223d573713822fafbff44a05459e4f27963ba
https://github.com/llvm/llvm-project/commit/633223d573713822fafbff44a05459e4f27963ba
Author: Jiahao Guo <eoonguo at gmail.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
M clang/test/CodeGen/AArch64/neon-intrinsics.c
M clang/test/CodeGen/AArch64/neon/intrinsics.c
Log Message:
-----------
[CIR][AArch64] Lower NEON vshrn* intrinsics (#226382)
## summary
part of : https://github.com/llvm/llvm-project/issues/185382
Lower all intrinsics in :
https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#vector-shift-right-and-narrow
Assisted by : gpt-6-sol
Commit: 992ca79c83b0882465a202883109bd4cd167ec00
https://github.com/llvm/llvm-project/commit/992ca79c83b0882465a202883109bd4cd167ec00
Author: Jack Huang <jackhuang1205 at gmail.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M llvm/include/llvm/IR/IRBuilder.h
M llvm/lib/Transforms/Vectorize/VectorCombine.cpp
M llvm/test/Transforms/VectorCombine/binop-scalarize.ll
A llvm/test/Transforms/VectorCombine/cmp-scalarize.ll
M llvm/test/Transforms/VectorCombine/unary-op-scalarize.ll
Log Message:
-----------
[VectorCombine] Pass flags during IR creation (#193271)
Since commit 777d6b5, VectorCombine has been using InstSimplifyFolder to
simplify vector instructions during IR construction. When creating a new
instruction, InstSimplifyFolder may fold the operation and return an
existing operand instead of emitting a new instruction.
In such cases, copying IR flags to the returned value is incorrect and
may unintentionally propagate flags to pre‑existing instructions,
polluting the original IR. To avoid this, flags should be passed at IR
creation rather than being set after construction. Fix #192607.
Commit: a8d2c44b29e9a5caac37dc400cebca5f997ad6a6
https://github.com/llvm/llvm-project/commit/a8d2c44b29e9a5caac37dc400cebca5f997ad6a6
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
Log Message:
-----------
X86: Mark eflags clobbers dead in va_arg expansion (#227197)
Co-authored-by: Claude Opus 5 <noreply at anthropic.com>
Commit: 8d79b74443de46e78b4f2c90aa65bd42c491e909
https://github.com/llvm/llvm-project/commit/8d79b74443de46e78b4f2c90aa65bd42c491e909
Author: Timur Baidusenov <timurbaidusenov at gmail.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M polly/lib/Transform/ScheduleOptimizer.cpp
A polly/test/ScheduleOptimizer/simplify_deps_bounded_proximity.ll
Log Message:
-----------
[Polly] Keep proximity dependence exact if simplifying it unbounds its distance (#225840)
Before calling the isl scheduler, `runIslScheduleOptimizer` gists the
dependences
with the iteration domains (`-polly-opt-simplify-deps=yes`, the default
since
a26db470834a, 2012). For a statement that reads a value written in one
iteration
of a loop in all later iterations, the gist also drops the upper bound
of that
loop:
{ S[k, i, k] -> S[k, i, j] : k < j <= n - 1 } becomes { S[k, i, k] ->
S[k, i, j] : j > k }
The proximity distance along j is then unbounded. isl's Pluto-like step
needs a
bound `u·n + w` on every proximity distance, finds no row that satisfies
it, and
falls back to carrying dependences one row at a time. For floyd-warshall
this
yields a wavefront over `i + j` below the `k` loop instead of a
permutable band
`(i, j)`. That band is never tiled, and the innermost loop walks the
array
diagonally.
The patch keeps the exact proximity dependence of a statement on itself
when
the gisted dependence has unbounded distances and the exact one has
bounded
distances. Validity dependences, and dependences between different
statements,
are still gisted. The cost of the exact dependences therefore only
applies to
the few maps where the gist removed the bound; heat-3d, where keeping
all
proximity dependences exact makes scheduling take minutes, is
unaffected.
### Measurements
x86-64 (Ryzen 7 9700X), `-O3 -march=native -mllvm -polly`, baseline is
the same
compiler without the change.
| | before | after | |
|---|---|---|---|
| PolyBench 4.2.1 LARGE floyd-warshall (min of 3, pinned) | 26.7 s | 6.8
s | 3.9x |
| llvm-test-suite floyd-warshall (min of 5, pinned) | 60.9 s | 16.4 s |
3.7x |
| compile time floyd-warshall.c (min of 5) | 131 ms | 134 ms | |
| .text floyd-warshall | 4775 | 6298 | |
- Among the 30 PolyBench kernels, only floyd-warshall generates
different code.
- In llvm-test-suite (SingleSource + MultiSource), only floyd-warshall
and two
small regression tests (Regression-C-test_indvars,
GCC-C-execute-20000422-1)
change. All 2137 tests pass in both configurations. The other objects
whose
code differed between the two builds (oggenc, two TSVC programs) differ
by
Polly's pre-existing run-to-run nondeterminism; the patch did not
trigger
there.
- CTMark (`-j1`, pinned, 2 repetitions): identical generated code, total
compile
time within noise.
- With the default 32x32 tiles, floyd-warshall is still 1.2x slower than
plain
-O3 on this machine. That is a tile size effect: with
`-polly-tile-sizes=16,32`
the kernel runs in 1.6 s, 3.5x faster than -O3.
### Test
`polly/test/ScheduleOptimizer/simplify_deps_bounded_proximity.ll`:
floyd-warshall
with a parametric size; checks for the `(k)` band followed by the tiled
`(i, j)`
band. It fails without the patch, which produces the `(i + j)`
wavefront.
Assisted-by: Claude (Anthropic)
Commit: e8c09d19de8212bfb2d5c760c43a21e27729f660
https://github.com/llvm/llvm-project/commit/e8c09d19de8212bfb2d5c760c43a21e27729f660
Author: Nico Weber <thakis at chromium.org>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M clang/docs/InternalsManual.md
M clang/include/clang/Sema/Sema.h
M clang/lib/Sema/SemaConcept.cpp
Log Message:
-----------
[clang] Cache normalized constraints by expression instead of by declaration (#226620)
Sema::NormalizationCache was keyed by the constrained declaration. The
members of a class template specialization are distinct declarations for
every specialization, but they all share the uninstantiated constraint
expressions of the member of the primary template they were instantiated
from. So the constraints of e.g. the constrained constructors of
std::optional, std::span, std::pair or of the members of range adaptors
were normalized from scratch for every single specialization of those
classes that a TU uses. Normalization is expensive: it expands the whole
concept tree below the expression and substitutes the parameter mapping
at every level.
When compiling Chromium, 48%
(chrome/browser/glic/...contents_manager.cc)
to 72% (chrome/browser/ui/views/frame/browser_view.cc) of all
NormalizationCache misses were for expressions that were normalized
before
for a different declaration, and normalization is 4.5% of all compile
time
in a sampling profile.
Instead, key the cache by (expression, pack index). Each associated
constraint is cached separately, and we form the conjunction of a
declaration's associated constraints on every call. That's cheap, and
getNormalizedAssociatedConstraints() is only called on SatisfactionCache
misses and for subsumption checks. Failures are cached as nullptr, like
before.
Build time for 120 random Chromium TUs drawn with probability
proportional to their compile time:
CPU time: 470.0 s => 451.1 s, -4.0%
instructions: 4948.9e9 => 4702.7e9, -5.0%
mean max RSS: 779 MB => 710 MB, -8.9%
(To check noise level, running this with the same binary twice: +-0.04%
CPU time and +-0.01% instructions.)
Recovers some more of the time lost to #161671 and contributes to
improving issue #172266.
No behavior change on the non-error case.
(If several declarations share a constraint expression that fails to
normalize (e.g. the members of different specializations of a class
template), we now diagnose the failure once instead of once per
declaration.)
Commit: 6aeadac52d4f564e5030a1a22013ab381436cce3
https://github.com/llvm/llvm-project/commit/6aeadac52d4f564e5030a1a22013ab381436cce3
Author: David Spickett <david.spickett at arm.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M lldb/examples/python/templates/scripted_process.py
Log Message:
-----------
[lldb] Correct types for ScriptedFrame get_function_name get_display_function_name (#226938)
These claimed to return str but the initial value for self.name is None,
and the C++ side returns optional<string>. So I think optional string is
correct here.
Commit: d7daf1d24be8231f7f422ef2bca1003d4b77ec11
https://github.com/llvm/llvm-project/commit/d7daf1d24be8231f7f422ef2bca1003d4b77ec11
Author: David Spickett <david.spickett at arm.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M llvm/tools/llvm-profgen/PerfReader.cpp
Log Message:
-----------
[llvm][llvm-profgen] Fix printing bogus trace info on 32-bit (#226965)
And as a result, fix
llvm/test/tools/llvm-profgen/AArch64/cs-bogus-trace.test when run on Arm
32-bit:
https://lab.llvm.org/buildbot/#/builders/122/builds/59
Fixes #225569 / 28fec94991905d8dd8a08658e9590e13b7fe1af5.
`x` is for an unsigned integer but the argument given for it is a
uint64_t. This worked on 64-bit (maybe it's passed in a register), but
not on 32-bit where we got strange values printed.
Use format_hex instead, so we don't have to choose a format code.
Commit: b20896c96deab703d7f0e99301b553a8ef4abad7
https://github.com/llvm/llvm-project/commit/b20896c96deab703d7f0e99301b553a8ef4abad7
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M llvm/lib/Target/DirectX/DXILDataScalarization.cpp
M llvm/lib/Target/DirectX/DXILFlattenArrays.cpp
M llvm/lib/Target/DirectX/DXILLegalizePass.cpp
M llvm/lib/Target/DirectX/DXILMemIntrinsics.cpp
M llvm/lib/Target/DirectX/DXILOpLowering.cpp
M llvm/test/CodeGen/DirectX/bugfix_150050_data_scalarize_const_gep.ll
M llvm/test/CodeGen/DirectX/flatten-array.ll
M llvm/test/CodeGen/DirectX/flatten-bug-117273.ll
M llvm/test/CodeGen/DirectX/legalize-i8.ll
M llvm/test/CodeGen/DirectX/llc-vector-load-scalarize.ll
M llvm/test/CodeGen/DirectX/scalar-store.ll
M llvm/test/CodeGen/DirectX/scalarize-static-array-of-float-vectors.ll
M llvm/test/tools/dxil-dis/constantexpr-gep.ll
Log Message:
-----------
[DirectX] Don't use IRBuilder to create GEPs (#227000)
This switches the DirectX backend to directly call
`GetElementPtrInst::Create()` instead of creating GEPs via IRBuilder.
IRBuilder will soon start canonicalizing GEPs to ptradd representation
(with the first change being
https://github.com/llvm/llvm-project/pull/226425, affecting constant
expressions only), while DirectX needs GEPs to have specific form.
The change implemented here is a minimal one to unblock further work. In
the future, it will become impossible to construct such GEPs through any
API. The DirectX backend needs to switch to using an intrinsic to
represent any non-canonical GEPs it needs. This followup work is tracked
in https://github.com/llvm/llvm-project/issues/227005.
Commit: bb9dd27ae02c6b4fb49757085aa13af92cc1ccda
https://github.com/llvm/llvm-project/commit/bb9dd27ae02c6b4fb49757085aa13af92cc1ccda
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M clang/lib/AST/ByteCode/Context.cpp
M clang/lib/AST/ByteCode/Context.h
M clang/lib/AST/ByteCode/EvalEmitter.cpp
M clang/lib/AST/ByteCode/EvalEmitter.h
M clang/lib/AST/ByteCode/InterpState.cpp
M clang/lib/AST/ByteCode/InterpState.h
M clang/lib/AST/ExprConstant.cpp
Log Message:
-----------
[clang][bytecode] Use bytecode interpreter in toplevel `Expr::Evaluate*` functions (#226217)
To avoid all the state setup we otherwise do. This also lets us remove
the `EvalInfo::EnableNewConstInterp` flag, which was previously checked
on every `::EvaluateAsRValue` call.
Commit: c68a4ca2a9202d073b569cbfbfb269f21abf7aec
https://github.com/llvm/llvm-project/commit/c68a4ca2a9202d073b569cbfbfb269f21abf7aec
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M mlir/lib/Target/LLVMIR/Dialect/LLVMIR/LLVMToLLVMIRTranslation.cpp
M mlir/test/Target/LLVMIR/llvmir-invalid.mlir
Log Message:
-----------
[LLVMIR] Directly lower global initializer GEP to constant expression (#226904)
MLIR lowers global initializers in a very unusual way, by using an
IRBuilder without insertion point, and relying on the fact that for a
well-formed initializer, all the instructions will be converted to
constant expressions and no actual instructions that require insertion
will be produced.
This causes issues for https://github.com/llvm/llvm-project/pull/226425,
which requires an insertion point for CreateGEP to determine the data
layout.
To avoid this, make convertGEPOp() directly produce a constant
expression GEP if there is no insertion point, reusing the existing code
path for inrange GEPs.
Commit: 090b123694953beeb55d003e45c24372858b29b8
https://github.com/llvm/llvm-project/commit/090b123694953beeb55d003e45c24372858b29b8
Author: David Spickett <david.spickett at arm.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M lldb/test/API/functionalities/scripted_frame_provider/pass_through_prefix/TestFrameProviderPassThroughPrefix.py
M lldb/test/API/functionalities/scripted_frame_provider/pass_through_prefix/frame_provider.py
Log Message:
-----------
[lldb][test] Handle None function name in frame provider tests (#226936)
Fixes #191859.
On Arm one of the functions has no name, which is a valid state.
```
Num frames: 7
0 frame #0: 0x092a151c a.out`baz at main.c:5:3 --name: baz
1 frame #1: 0x092a1540 a.out`bar at main.c:10:10 --name: bar
2 frame #2: 0x092a1560 a.out`foo at main.c:15:10 --name: foo
3 frame #3: 0x092a158c a.out`main at main.c:20:10 --name: main
4 frame #4: 0xf7ab939a libc.so.6` --name: None
5 frame #5: 0xf7ab943e libc.so.6`__libc_start_main + 94 --name: __libc_start_main
6 frame #6: 0x092a1434 a.out`_start + 40 --name: _start
```
The prefix provider needs to handle that possibility.
Though the Python type annotations on ScriptedFrame say that the name
methods return string, in reality they can return None, which the C++
sides expect. I will fix that in another PR.
Commit: e0bd48983e9d1d0de471a7689573622464c0b332
https://github.com/llvm/llvm-project/commit/e0bd48983e9d1d0de471a7689573622464c0b332
Author: Fangrui Song <i at maskray.me>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M clang/docs/LibASTImporter.md
M clang/docs/UsersManual.md
Log Message:
-----------
[docs] Pass -c when generating a PCH file (#226850)
Without options like -fsyntax-only/-E/-S/-c, the driver runs in link
mode, and a header-only command line produces a PCH only incidentally: a
linker option such as -lm or -Wl,..., including one from a config file,
adds a link job. Use -c in the PCH examples.
Also fix two broken examples: -ignore-pch is a driver option (cc1
rejects -Xclang -ignore-pch), and the relocatable PCH example is
missing -o. In LibASTImporter.md, generate the C++ AST files with
-emit-ast instead of treating .cpp files as headers.
LLM-aided
Commit: 58b102609a9d08fbadb9c3fa1dd88bba2cf7f711
https://github.com/llvm/llvm-project/commit/58b102609a9d08fbadb9c3fa1dd88bba2cf7f711
Author: Pawan Nirpal <pnirpal at qti.qualcomm.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M llvm/lib/Analysis/ScalarEvolution.cpp
A llvm/test/Analysis/ScalarEvolution/trip-count-variable-stride-predicate.ll
A llvm/test/Transforms/LoopVectorize/scev-variable-stride-predicate.ll
Log Message:
-----------
[SCEV] - Add positive-stride predicate for backedge-taken count. (#222261)
When `howManyLessThans` encounters a loop with an unknown stride that
cannot be proven finite (no `mustprogress` or side-effect-free
guarantee), SCEV currently returns `CouldNotCompute` for the
backedge-taken count. This blocks downstream consumers like the loop
vectorizer from optimizing such loops.
This patch relaxes the requirement by allowing a predicated
backedge-taken count when `AllowPredicates` is true. Instead of
requiring `loopIsFiniteByAssumption(L)` unconditionally, we add a
`Compare predicate: stride sgt 0` when finiteness cannot be proven.
A positive stride guarantees forward progress, making the BTC formula
correct. The predicate is emitted as a runtime check by consumers
(e.g., the loop vectorizer generates a guard branch before the vector
loop).
This is the SCEV-level fix for a class of variable-increment loops
common in Fortran-style benchmarks, e.g.:
void f(int n, int *a, int *b, int *c, int inc) {
int i = 0;
L10: if (i >= n) goto L20;
a[i] = a[i] + b[i] * c[i];
i = i + inc; // inc unknown at compile time
goto L10;
L20: ;
}
Addressing : https://github.com/llvm/llvm-project/issues/221915
---------
Co-authored-by: Florian Hahn <flo at fhahn.com>
Commit: ab0582707ef7ea0c4b03dff58ae9c32a9bdfec5c
https://github.com/llvm/llvm-project/commit/ab0582707ef7ea0c4b03dff58ae9c32a9bdfec5c
Author: Ties Stuij <ties.stuij at arm.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M compiler-rt/test/builtins/Unit/arm/aeabi_cmpflags_interwork_test.c
Log Message:
-----------
[compiler-rt][ARM] Make interworking test compatible with BTI (#226154)
In the aeabi_cmpflags_interwork_test.c test wrappers, we should return
through lr instead of r3 so that runs with BTI enabled don't fail. As
returns through lr don't require a landing pad, and returns through r3
do.
Commit: a3a37848d8cac394d067a6c9c5d545753556e4e7
https://github.com/llvm/llvm-project/commit/a3a37848d8cac394d067a6c9c5d545753556e4e7
Author: Henrich Lauko <xlauko at mail.muni.cz>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M mlir/include/mlir/IR/Diagnostics.h
M mlir/lib/IR/Diagnostics.cpp
M mlir/lib/Tools/mlir-opt/MlirOptMain.cpp
A mlir/test/Pass/remark-final-verify-diagnostics.mlir
M mlir/unittests/IR/Diagnostic.cpp
Log Message:
-----------
[mlir] Own the registrations of SourceMgrDiagnosticVerifierHandler (#226258)
`SourceMgrDiagnosticVerifierHandler::registerInContext` registered a
callback capturing `this` and dropped the handler id, so nothing could
erase it. The constructor did the same in its own context. After the
verifier was destroyed, the next diagnostic called into a dead object.
mlir-opt's per-buffer contexts die first, which hid the bug.
Make both registrations owned:
- The constructor installs its callback through `setHandler`, replacing
the base class's printing handler. That handler was unreachable anyway:
the verifier consumes every diagnostic and reports unexpected ones
itself. The base destructor now erases it.
- `registerInContext` returns a scoped registration. Callers destroy it
before the verifier and the context.
Erasing from every registered context in the destructor would not work:
mlir-opt's per-buffer contexts are already gone by then.
mlir-opt's `performActions` finalized the remark policy only after
textual output; on a failing pipeline the remarks deferred by
`--remark-policy=final` were emitted from `~MLIRContext`, after the
handlers were gone. It now finalizes on every exit, so those remarks
reach the verifier, or the printing handler in the non-verify path where
they were dropped before. A lit test pins this.
Assisted-by: Claude Code (Claude Fable 5.1)
Commit: f72d03de7c159efd3c4a4501323d19c86c17d7a8
https://github.com/llvm/llvm-project/commit/f72d03de7c159efd3c4a4501323d19c86c17d7a8
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
M llvm/test/CodeGen/SPIRV/legalization/signed-narrow-int.ll
Log Message:
-----------
[SPIR-V] Sign extend narrow ints feeding sitofp (#222969)
Commit: 197c16add5b16f4bd68c4f4bae115723e74330e2
https://github.com/llvm/llvm-project/commit/197c16add5b16f4bd68c4f4bae115723e74330e2
Author: Luke Lau <luke at igalia.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M .github/workflows/test-suite.yml
Log Message:
-----------
[GitHub] Add ffmpeg to test-suite.yml workflow (#227219)
This provides additional coverage for vector related codegen
Commit: 5e1ed67dbadba1b2bc254411cf78e61db51687d1
https://github.com/llvm/llvm-project/commit/5e1ed67dbadba1b2bc254411cf78e61db51687d1
Author: Momchil Velikov <momchil.velikov at arm.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M llvm/include/llvm/Transforms/Scalar/GVN.h
A llvm/include/llvm/Transforms/Scalar/GVNHoist.h
A llvm/include/llvm/Transforms/Scalar/GVNSink.h
A llvm/include/llvm/Transforms/Scalar/GVNValueTable.h
M llvm/lib/Passes/PassBuilder.cpp
M llvm/lib/Passes/PassBuilderPipelines.cpp
M llvm/lib/Transforms/Scalar/GVN.cpp
M llvm/lib/Transforms/Scalar/GVNHoist.cpp
M llvm/lib/Transforms/Scalar/GVNSink.cpp
Log Message:
-----------
[GVN] Move `ValueTable` out of `GVN.h` (NFC) (#226233)
* Rename `GVNPass::ValueTable` to `GVNValueTable`, and move it out to
the `llvm` namespace and to its own file `GVNValueTable.h`.
* Move `GVNPass::Expression` into `llvm::GVNValueTable`.
* Move `GVNHoistPass` and `GVNSinkPass` to their own headers.
With these changes `GVHoist.cpp` and `GVNSink.cpp` no longer need to
include `GVN.h` or peek into `GVNPass` internals.
Commit: 6286f77214be257eed1cff70d3e2e16f024e3dfb
https://github.com/llvm/llvm-project/commit/6286f77214be257eed1cff70d3e2e16f024e3dfb
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M llvm/include/llvm/Target/CGPassBuilderOption.h
M llvm/lib/CodeGen/TargetPassConfig.cpp
M llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
M llvm/lib/Passes/CodeGenPassBuilder.cpp
M llvm/test/CodeGen/AArch64/O3-pipeline.ll
M llvm/test/CodeGen/AArch64/coalescer-empty-subrange-early-lis.ll
M llvm/test/CodeGen/AArch64/itofp-bf16.ll
M llvm/test/CodeGen/AArch64/pr161420.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-trunc.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/twoaddr-extract-dyn-v7f64.mir
M llvm/test/CodeGen/AMDGPU/a-v-flat-atomic-cmpxchg.ll
M llvm/test/CodeGen/AMDGPU/acc-ldst.ll
M llvm/test/CodeGen/AMDGPU/add_i128.ll
M llvm/test/CodeGen/AMDGPU/add_i64.ll
M llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.160bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.224bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.288bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.32bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.352bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.384bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.448bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.48bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.576bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.640bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.64bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.704bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.768bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-mul24-knownbits.ll
M llvm/test/CodeGen/AMDGPU/and.ll
M llvm/test/CodeGen/AMDGPU/any_extend_vector_inreg.ll
M llvm/test/CodeGen/AMDGPU/anyext.ll
M llvm/test/CodeGen/AMDGPU/asyncmark-gfx12plus.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomicrmw_usub_sat.ll
M llvm/test/CodeGen/AMDGPU/atomics-system-scope.ll
M llvm/test/CodeGen/AMDGPU/av-split-dead-valno-crash.ll
M llvm/test/CodeGen/AMDGPU/bf16.ll
M llvm/test/CodeGen/AMDGPU/bitinsert-bitextract-fp.ll
M llvm/test/CodeGen/AMDGPU/bitinsert-bitextract.ll
M llvm/test/CodeGen/AMDGPU/bitreverse.ll
M llvm/test/CodeGen/AMDGPU/branch-folding-implicit-def-subreg.ll
M llvm/test/CodeGen/AMDGPU/bswap.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointers-memcpy.ll
M llvm/test/CodeGen/AMDGPU/bypass-div.ll
M llvm/test/CodeGen/AMDGPU/clmul.ll
M llvm/test/CodeGen/AMDGPU/consecutive-loads-in-branch.ll
M llvm/test/CodeGen/AMDGPU/copy-illegal-type.ll
M llvm/test/CodeGen/AMDGPU/ctlz.ll
M llvm/test/CodeGen/AMDGPU/ctlz_zero_poison.ll
M llvm/test/CodeGen/AMDGPU/ctpop.ll
M llvm/test/CodeGen/AMDGPU/ctpop16.ll
M llvm/test/CodeGen/AMDGPU/ctpop64.ll
M llvm/test/CodeGen/AMDGPU/cttz.ll
M llvm/test/CodeGen/AMDGPU/cttz_zero_poison.ll
M llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
M llvm/test/CodeGen/AMDGPU/dead-lane.mir
M llvm/test/CodeGen/AMDGPU/div_v2i128.ll
M llvm/test/CodeGen/AMDGPU/ds_gws_align.ll
M llvm/test/CodeGen/AMDGPU/dynamic-vgpr-reserve-stack-for-cwsr.ll
M llvm/test/CodeGen/AMDGPU/fadd.f16.ll
M llvm/test/CodeGen/AMDGPU/fceil64.ll
M llvm/test/CodeGen/AMDGPU/fcmp.f16.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64_noprivate.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system.ll
M llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp-fp8-hw.ll
M llvm/test/CodeGen/AMDGPU/fmax_legacy.f64.ll
M llvm/test/CodeGen/AMDGPU/fmin_legacy.f64.ll
M llvm/test/CodeGen/AMDGPU/fmul.f16.ll
M llvm/test/CodeGen/AMDGPU/fnearbyint.ll
M llvm/test/CodeGen/AMDGPU/fptoi.i128.ll
M llvm/test/CodeGen/AMDGPU/fptrunc.ll
M llvm/test/CodeGen/AMDGPU/freeze.ll
M llvm/test/CodeGen/AMDGPU/frem.ll
M llvm/test/CodeGen/AMDGPU/fshl.ll
M llvm/test/CodeGen/AMDGPU/fsub.f16.ll
M llvm/test/CodeGen/AMDGPU/gfx-callable-return-types.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/global-load-xcnt.ll
M llvm/test/CodeGen/AMDGPU/half.ll
M llvm/test/CodeGen/AMDGPU/hsa-metadata-kernel-code-props.ll
M llvm/test/CodeGen/AMDGPU/identical-subrange-spill-infloop.ll
M llvm/test/CodeGen/AMDGPU/idot2.ll
M llvm/test/CodeGen/AMDGPU/idot4s.ll
M llvm/test/CodeGen/AMDGPU/idot4u.ll
M llvm/test/CodeGen/AMDGPU/idot8u.ll
M llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll
M llvm/test/CodeGen/AMDGPU/indirect-call.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_elt.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll
M llvm/test/CodeGen/AMDGPU/lds-misaligned-bug.ll
M llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll
M llvm/test/CodeGen/AMDGPU/llc-pipeline.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dual_intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.atomic.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.dim.gfx90a.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.dim.gfx90a.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.scale.f32.32x32x64.f8f6f4.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fadd.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fsub.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.set.inactive.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.smfmac.gfx950.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp10.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp10.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp2.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp2.ll
M llvm/test/CodeGen/AMDGPU/llvm.fma.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.log2.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.maxnum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.minimum.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.minnum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.round.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.round.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i16.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i32.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i64.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i8.ll
M llvm/test/CodeGen/AMDGPU/load-global-f32.ll
M llvm/test/CodeGen/AMDGPU/load-global-i16.ll
M llvm/test/CodeGen/AMDGPU/load-global-i32.ll
M llvm/test/CodeGen/AMDGPU/load-global-i8.ll
M llvm/test/CodeGen/AMDGPU/load-local-i16.ll
M llvm/test/CodeGen/AMDGPU/lower-control-flow-live-variables-update.mir
M llvm/test/CodeGen/AMDGPU/machine-sink-temporal-divergence-swdev407790.ll
M llvm/test/CodeGen/AMDGPU/mad-combine.ll
M llvm/test/CodeGen/AMDGPU/mad_uint24.ll
M llvm/test/CodeGen/AMDGPU/max.ll
M llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll
M llvm/test/CodeGen/AMDGPU/merge-stores.ll
M llvm/test/CodeGen/AMDGPU/mfma-cd-select.ll
M llvm/test/CodeGen/AMDGPU/mfma-no-register-aliasing.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-atomicrmw-system.ll
M llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands-non-ptr-intrinsics.ll
M llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands.ll
M llvm/test/CodeGen/AMDGPU/mul.ll
M llvm/test/CodeGen/AMDGPU/mul_uint24-amdgcn.ll
M llvm/test/CodeGen/AMDGPU/no-remat-indirect-mov.mir
M llvm/test/CodeGen/AMDGPU/operand-folding.ll
M llvm/test/CodeGen/AMDGPU/or.ll
M llvm/test/CodeGen/AMDGPU/packed-fp32.ll
M llvm/test/CodeGen/AMDGPU/packed-fp64.ll
M llvm/test/CodeGen/AMDGPU/packed-u64.ll
M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll
M llvm/test/CodeGen/AMDGPU/rewrite-mfma-single-exit-copy.ll
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-reserved-wwm-vgpr.ll
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-spill-joint-dom.ll
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr.ll
M llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll
M llvm/test/CodeGen/AMDGPU/schedule-relaxed-occupancy.ll
M llvm/test/CodeGen/AMDGPU/scratch-simple.ll
M llvm/test/CodeGen/AMDGPU/sdiv.ll
M llvm/test/CodeGen/AMDGPU/select.f16.ll
M llvm/test/CodeGen/AMDGPU/shift-and-i64-ubfe.ll
M llvm/test/CodeGen/AMDGPU/shl.ll
M llvm/test/CodeGen/AMDGPU/shl.v2i64.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll
M llvm/test/CodeGen/AMDGPU/sint_to_fp.i64.ll
M llvm/test/CodeGen/AMDGPU/sminmax.v2i16.ll
M llvm/test/CodeGen/AMDGPU/spill-scavenge-offset.ll
M llvm/test/CodeGen/AMDGPU/spill-vgpr.ll
M llvm/test/CodeGen/AMDGPU/splitkit-getsubrangeformask-phi-extend.ll
M llvm/test/CodeGen/AMDGPU/sra.ll
M llvm/test/CodeGen/AMDGPU/srem.ll
M llvm/test/CodeGen/AMDGPU/srl.ll
M llvm/test/CodeGen/AMDGPU/sub.ll
M llvm/test/CodeGen/AMDGPU/twoaddr-constrain.ll
M llvm/test/CodeGen/AMDGPU/udiv.ll
M llvm/test/CodeGen/AMDGPU/uint_to_fp.i64.ll
M llvm/test/CodeGen/AMDGPU/undef-handling-crash-in-ra.ll
M llvm/test/CodeGen/AMDGPU/undefined-subreg-liverange.ll
M llvm/test/CodeGen/AMDGPU/unspill-vgpr-after-rewrite-vgpr-mfma.ll
M llvm/test/CodeGen/AMDGPU/urem64.ll
M llvm/test/CodeGen/AMDGPU/v_madak_f16.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fmaximum.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fminimum.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-smax.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-smin.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-umax.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-umin.ll
M llvm/test/CodeGen/AMDGPU/vgpr-mark-last-scratch-load.ll
M llvm/test/CodeGen/AMDGPU/vni8-across-blocks.ll
M llvm/test/CodeGen/AMDGPU/vselect.ll
M llvm/test/CodeGen/AMDGPU/waitcnt-loop-ds-prefetch-pattern.ll
M llvm/test/CodeGen/AMDGPU/wave32.ll
M llvm/test/CodeGen/AMDGPU/widen-vselect-and-mask.ll
M llvm/test/CodeGen/AMDGPU/wqm.ll
M llvm/test/CodeGen/AMDGPU/xor.ll
M llvm/test/CodeGen/ARM/O3-pipeline.ll
M llvm/test/CodeGen/ARM/fp-intrinsics-vector.ll
M llvm/test/CodeGen/ARM/inlineasm-operand-implicit-cast.ll
M llvm/test/CodeGen/ARM/llvm.modf.ll
M llvm/test/CodeGen/ARM/llvm.sincos.ll
M llvm/test/CodeGen/ARM/signext-inreg.ll
M llvm/test/CodeGen/ARM/vldlane.ll
M llvm/test/CodeGen/Hexagon/addh.ll
M llvm/test/CodeGen/Hexagon/cttz-elts-widen.ll
M llvm/test/CodeGen/Hexagon/isel-extload-i1.ll
M llvm/test/CodeGen/Hexagon/mulhs.ll
M llvm/test/CodeGen/Hexagon/swp-vect-dotprod.ll
M llvm/test/CodeGen/LoongArch/opt-pipeline.ll
M llvm/test/CodeGen/M68k/pipeline.ll
M llvm/test/CodeGen/PowerPC/O3-pipeline.ll
M llvm/test/CodeGen/PowerPC/dmr-copy.ll
M llvm/test/CodeGen/PowerPC/dmr-enable.ll
M llvm/test/CodeGen/PowerPC/no-rlwimi-trivial-commute.mir
M llvm/test/CodeGen/RISCV/O3-newpm-pipeline.ll
M llvm/test/CodeGen/RISCV/O3-pipeline.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-subvector.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll
M llvm/test/CodeGen/RISCV/rvv/fmaximum-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fminimum-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfmsub-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vwadd.w.ll
M llvm/test/CodeGen/SystemZ/atomicrmw-ops-i128.ll
M llvm/test/CodeGen/SystemZ/atomicrmw-xchg-07.ll
M llvm/test/CodeGen/SystemZ/rot-02.ll
M llvm/test/CodeGen/SystemZ/subregliveness-01.ll
M llvm/test/CodeGen/Thumb/emergency-spill-slot.ll
M llvm/test/CodeGen/Thumb2/mve-clmul.ll
M llvm/test/CodeGen/Thumb2/mve-complex-deinterleaving-f64-add.ll
M llvm/test/CodeGen/Thumb2/mve-complex-deinterleaving-f64-mul.ll
M llvm/test/CodeGen/Thumb2/mve-complex-deinterleaving-mixed-cases.ll
M llvm/test/CodeGen/Thumb2/mve-complex-deinterleaving-uniform-cases.ll
M llvm/test/CodeGen/Thumb2/mve-ctlz.ll
M llvm/test/CodeGen/Thumb2/mve-fmath.ll
M llvm/test/CodeGen/Thumb2/mve-insertshuffleload.ll
M llvm/test/CodeGen/Thumb2/mve-laneinterleaving-cost.ll
M llvm/test/CodeGen/Thumb2/mve-laneinterleaving.ll
M llvm/test/CodeGen/Thumb2/mve-multivec-spill.ll
M llvm/test/CodeGen/Thumb2/mve-pred-shuffle.ll
M llvm/test/CodeGen/Thumb2/mve-saturating-arith.ll
M llvm/test/CodeGen/Thumb2/mve-sext-masked-load.ll
M llvm/test/CodeGen/Thumb2/mve-shuffle-fp16.ll
M llvm/test/CodeGen/Thumb2/mve-shuffle.ll
M llvm/test/CodeGen/Thumb2/mve-shuffleext.ll
M llvm/test/CodeGen/Thumb2/mve-shufflemov.ll
M llvm/test/CodeGen/Thumb2/mve-vabdus.ll
M llvm/test/CodeGen/Thumb2/mve-vcvt16.ll
M llvm/test/CodeGen/Thumb2/mve-vld2.ll
M llvm/test/CodeGen/Thumb2/mve-vld3.ll
M llvm/test/CodeGen/Thumb2/mve-vld4-post.ll
M llvm/test/CodeGen/Thumb2/mve-vld4.ll
M llvm/test/CodeGen/Thumb2/mve-vldst4.ll
M llvm/test/CodeGen/Thumb2/mve-vst2.ll
M llvm/test/CodeGen/Thumb2/mve-vst3.ll
M llvm/test/CodeGen/Thumb2/mve-vst4-post.ll
M llvm/test/CodeGen/Thumb2/mve-vst4.ll
M llvm/test/CodeGen/Thumb2/mve-zext-masked-load.ll
M llvm/test/CodeGen/X86/active_lane_mask.ll
M llvm/test/CodeGen/X86/addcarry.ll
M llvm/test/CodeGen/X86/apx/mul-i1024.ll
M llvm/test/CodeGen/X86/apx/pr191368.ll
M llvm/test/CodeGen/X86/apx/push2-pop2.ll
M llvm/test/CodeGen/X86/bit-manip-i512.ll
M llvm/test/CodeGen/X86/bitselect.ll
M llvm/test/CodeGen/X86/clmul-vector.ll
M llvm/test/CodeGen/X86/combine-bitselect.ll
M llvm/test/CodeGen/X86/combine-or.ll
M llvm/test/CodeGen/X86/combine-rotates.ll
M llvm/test/CodeGen/X86/div-rem-pair-recomposition-unsigned.ll
M llvm/test/CodeGen/X86/fpclamptosat_vec.ll
M llvm/test/CodeGen/X86/ftrunc.ll
M llvm/test/CodeGen/X86/funnel-shift-i512.ll
M llvm/test/CodeGen/X86/half.ll
M llvm/test/CodeGen/X86/i128-udiv.ll
M llvm/test/CodeGen/X86/icmp-abs-C.ll
M llvm/test/CodeGen/X86/inline-asm-A-constraint.ll
M llvm/test/CodeGen/X86/llc-pipeline-npm.ll
M llvm/test/CodeGen/X86/machine-combiner-int-vec.ll
M llvm/test/CodeGen/X86/machine-cse.ll
M llvm/test/CodeGen/X86/masked-urem.ll
M llvm/test/CodeGen/X86/midpoint-int-vec-128.ll
M llvm/test/CodeGen/X86/midpoint-int.ll
M llvm/test/CodeGen/X86/mul-i1024.ll
M llvm/test/CodeGen/X86/mul-i256.ll
M llvm/test/CodeGen/X86/mul-i512.ll
M llvm/test/CodeGen/X86/mul-shift-reassoc.ll
M llvm/test/CodeGen/X86/mul128.ll
M llvm/test/CodeGen/X86/neg-abs.ll
M llvm/test/CodeGen/X86/oddshuffles.ll
M llvm/test/CodeGen/X86/opt-pipeline.ll
M llvm/test/CodeGen/X86/pr46877.ll
M llvm/test/CodeGen/X86/scalar-minmax-simd.ll
M llvm/test/CodeGen/X86/shift-amount-mod.ll
M llvm/test/CodeGen/X86/shift-and.ll
M llvm/test/CodeGen/X86/statepoint-cmp-sunk-past-statepoint.ll
M llvm/test/CodeGen/X86/statepoint-relocate-eh.ll
M llvm/test/CodeGen/X86/statepoint-vreg-unlimited-tied-opnds.ll
M llvm/test/CodeGen/X86/ternlog.ll
M llvm/test/CodeGen/X86/twoaddr-lea-eflags-liveintervals.ll
M llvm/test/CodeGen/X86/ucmp.ll
M llvm/test/CodeGen/X86/unfold-masked-merge-vector-variablemask.ll
M llvm/test/CodeGen/X86/vec_umulo.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-3.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-3.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-3.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-8.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-3.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-8.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-3.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-8.ll
M llvm/test/CodeGen/X86/vector-lzcnt-128.ll
M llvm/test/CodeGen/X86/vector-partial-reduce-sumla.ll
M llvm/test/CodeGen/X86/vector-partial-reduce-umla.ll
M llvm/test/CodeGen/X86/vector-reduce-ctpop.ll
M llvm/test/CodeGen/X86/vector-reduce-smax.ll
M llvm/test/CodeGen/X86/vector-reduce-smin.ll
M llvm/test/CodeGen/X86/vector-reduce-umax.ll
M llvm/test/CodeGen/X86/vector-reduce-umin.ll
M llvm/test/CodeGen/X86/vector-trunc-packus.ll
M llvm/test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll
M llvm/test/CodeGen/X86/widen_arith-2.ll
M llvm/test/CodeGen/X86/widen_bitcnt.ll
M llvm/test/CodeGen/X86/zext-trunc.ll
M llvm/test/DebugInfo/MIR/X86/mlicm-hoist-post-regalloc.mir
M llvm/test/Transforms/SampleProfile/pseudo-probe-twoaddr.ll
Log Message:
-----------
CodeGen: Compute LiveIntervals before TwoAddressInstructions (#225174)
TwoAddressInstructions is the traditional primary use of LiveVariables, but it has
gained a LiveIntervals path. By moving LiveIntervals earlier, the default flips to rely
on it instead of LiveVariables. The overall test churn is mostly neutral, with more net
wins than losses.
This should move before phi elimination. This is a staging move to incrementally
remove the LiveVariables support from TwoAddressInstructions, and because the
move to running LiveIntervals on SSA is a bigger leap.
This obsoletes -early-live-intervals (though, maybe it could be repurposed for
move before SSA).
Co-authored-by: Claude (Claude-Opus-4.8)
Commit: f0f0fe2d928a4c46dbd60b6d6bf6cf6d9f8b2993
https://github.com/llvm/llvm-project/commit/f0f0fe2d928a4c46dbd60b6d6bf6cf6d9f8b2993
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
R libcxx/utils/ci/images/libcxx_next_runners.txt
R libcxx/utils/ci/images/libcxx_release_runners.txt
R libcxx/utils/ci/images/libcxx_runners.txt
Log Message:
-----------
[libcxx] Delete runner set image versions (#227141)
These are no longer needed now that we have removed the old runner sets.
Commit: cdebdbdba13e79bdb09d328e05b417d2b7614a82
https://github.com/llvm/llvm-project/commit/cdebdbdba13e79bdb09d328e05b417d2b7614a82
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
M llvm/lib/Transforms/Vectorize/VPlanUtils.h
M llvm/test/Transforms/LoopVectorize/VPlan/execution-frequencies-match-bfi.ll
M llvm/test/Transforms/LoopVectorize/VPlan/record-execution-frequencies.ll
M llvm/test/Transforms/LoopVectorize/VPlan/vplan-based-stride-mv.ll
M llvm/test/Transforms/LoopVectorize/VPlan/vplan-printing-branch-weights.ll
Log Message:
-----------
[VPlan] Use BlockFrequencyInfo's full mass for execution frequencies. (#227006)
Use BlockFrequencyInfo's full mass instead of custom 2^63 for "always
execute".
This updates VPlan's block frequencies to match BFI.
PR: https://github.com/llvm/llvm-project/pull/227006
Commit: f69661de1c6fd034afabc2acf79a888cf7b58c5c
https://github.com/llvm/llvm-project/commit/f69661de1c6fd034afabc2acf79a888cf7b58c5c
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M llvm/lib/Analysis/BlockFrequencyInfoImpl.cpp
A llvm/test/Analysis/BlockFrequencyInfo/many-successors-order.ll
Log Message:
-----------
[BFI] Use MapVector in combineWeightsByHashing. (#227027)
combineWeightsByHashing iterated over a DenseMap, which depends on the
hash. Use MapVector to get consistent results, independent of index
type/values.
This is mainly to ensure consistency between users that use different
index numbers, i.e. used for IR BFI and VPlan's use.
PR: https://github.com/llvm/llvm-project/pull/227027
Commit: 724557a9bd1389446ba52d270ad31d78a6071497
https://github.com/llvm/llvm-project/commit/724557a9bd1389446ba52d270ad31d78a6071497
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M llvm/test/CodeGen/X86/two-address-subreg-to-reg-kill.mir
Log Message:
-----------
X86: Fix missing ... separator between functions in mir test (#227228)
The update_mir_test_checks output is incomplete so the later functions
here were really manually checked.
Commit: fa3d17075284bf746f4030ad3371fe5c05b06653
https://github.com/llvm/llvm-project/commit/fa3d17075284bf746f4030ad3371fe5c05b06653
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M llvm/lib/Transforms/IPO/FunctionAttrs.cpp
M llvm/test/Transforms/FunctionAttrs/noalias.ll
Log Message:
-----------
[FunctionAttrs] Infer noalias through a null check. (#226956)
Only comparing against null does not captures provenance and should not
impact whether a pointer is noalias or not.
This enables noalias inference in a number of cases for malloc-like
functions:
https://github.com/dtcxzyw/llvm-opt-benchmark-nightly/pull/1459.
PR: https://github.com/llvm/llvm-project/pull/226956
Commit: 6ccc4917217c650428fd36360690dad4a3f69d20
https://github.com/llvm/llvm-project/commit/6ccc4917217c650428fd36360690dad4a3f69d20
Author: Utkarsh Saxena <usx at google.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M clang/lib/Analysis/LifetimeSafety/FactsGenerator.cpp
M clang/test/Sema/LifetimeSafety/safety.cpp
Log Message:
-----------
[LifetimeSafety] Fix off-by-one crash in `lifetime_capture_by` argument indexing (#227231)
Fixes an off-by-one crash in the lifetime_capture_by attribute handling.
The CapturingArgIdx is already an index into the full Args array, but
the code was incorrectly creating a CallArgs array (dropping the first
argument for instance methods) and then indexing into it with
CapturingArgIdx, causing incorrect argument access and potential
out-of-bounds crashes.
Currently crashes at head: https://godbolt.org/z/7rYczK1z6
Commit: 74c86a79968b3f23eb3b292d318429364709f6b2
https://github.com/llvm/llvm-project/commit/74c86a79968b3f23eb3b292d318429364709f6b2
Author: Jay Foad <jay.foad at amd.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPULaneMaskUtils.h
M llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.h
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
M llvm/test/CodeGen/AMDGPU/anyext.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
M llvm/test/CodeGen/AMDGPU/bf16-conversions.ll
M llvm/test/CodeGen/AMDGPU/copy-to-reg-scc-clobber.ll
M llvm/test/CodeGen/AMDGPU/extract-subvector-16bit.ll
M llvm/test/CodeGen/AMDGPU/fcmp.f16.ll
M llvm/test/CodeGen/AMDGPU/fcopysign.bf16.ll
A llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-scc-cmp-wave32.mir
A llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-scc-cmp.mir
M llvm/test/CodeGen/AMDGPU/fneg-combines.new.ll
M llvm/test/CodeGen/AMDGPU/fneg-modifier-casting.ll
M llvm/test/CodeGen/AMDGPU/fp-classify.ll
M llvm/test/CodeGen/AMDGPU/fp_to_sint.ll
M llvm/test/CodeGen/AMDGPU/fp_to_uint.ll
M llvm/test/CodeGen/AMDGPU/fpow.ll
M llvm/test/CodeGen/AMDGPU/fptosi-sat-scalar.ll
M llvm/test/CodeGen/AMDGPU/fptosi.f16.ll
M llvm/test/CodeGen/AMDGPU/fptoui.f16.ll
M llvm/test/CodeGen/AMDGPU/frem.ll
M llvm/test/CodeGen/AMDGPU/fsqrt.f64.ll
M llvm/test/CodeGen/AMDGPU/literal64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.class.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp2.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.ll
M llvm/test/CodeGen/AMDGPU/llvm.log.ll
M llvm/test/CodeGen/AMDGPU/llvm.log10.ll
M llvm/test/CodeGen/AMDGPU/llvm.log2.ll
M llvm/test/CodeGen/AMDGPU/max.ll
M llvm/test/CodeGen/AMDGPU/min.ll
M llvm/test/CodeGen/AMDGPU/mixed-vmem-types.ll
M llvm/test/CodeGen/AMDGPU/or.ll
M llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.ll
M llvm/test/CodeGen/AMDGPU/rsq.f64.ll
M llvm/test/CodeGen/AMDGPU/saddo.ll
M llvm/test/CodeGen/AMDGPU/scmp.ll
M llvm/test/CodeGen/AMDGPU/setcc-f64-hi32mask.ll
M llvm/test/CodeGen/AMDGPU/ssubo.ll
M llvm/test/CodeGen/AMDGPU/ucmp.ll
M llvm/test/CodeGen/AMDGPU/umin-sub-to-usubo-select-combine.ll
M llvm/test/CodeGen/AMDGPU/wave32.ll
Log Message:
-----------
[AMDGPU] Use S_CMP to lower a copy of a lane mask to SCC (#221445)
SIFixSGPRCopies lowers a copy of a lane mask to SCC as an AND with EXEC,
whose destination register is created by the pass and is always dead.
The AND with EXEC is only needed because SCC has to be "any active lane
is set". When the lane mask already has 0 in the bits of all inactive
lanes, that is just "the mask is non-zero", which S_CMP computes without
needing a destination register. In some cases the S_CMP can be optimized
away later by SIInstrInfo::optimizeCompareInstr.
Co-authored-by: Claude Opus 5 (1M context) <noreply at anthropic.com>
Commit: 7cf8ecb2ef8acc2bca15f2223a3635f5863a81a7
https://github.com/llvm/llvm-project/commit/7cf8ecb2ef8acc2bca15f2223a3635f5863a81a7
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M llvm/lib/Target/Mips/MipsFastISel.cpp
A llvm/test/CodeGen/Mips/Fast-ISel/mul-dead-hilo.ll
Log Message:
-----------
Mips: Mark MUL's existing HI0/LO0 defs dead in FastISel (#227230)
Commit: 5a245737377fec09c871c802cc730189a61df459
https://github.com/llvm/llvm-project/commit/5a245737377fec09c871c802cc730189a61df459
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M llvm/lib/Target/Mips/MipsCallLowering.cpp
M llvm/test/CodeGen/Mips/GlobalISel/irtranslator/aggregate_struct_return.ll
M llvm/test/CodeGen/Mips/GlobalISel/irtranslator/call.ll
M llvm/test/CodeGen/Mips/GlobalISel/irtranslator/extend_args.ll
M llvm/test/CodeGen/Mips/GlobalISel/irtranslator/float_args.ll
M llvm/test/CodeGen/Mips/GlobalISel/irtranslator/global_address.ll
M llvm/test/CodeGen/Mips/GlobalISel/irtranslator/global_address_pic.ll
M llvm/test/CodeGen/Mips/GlobalISel/irtranslator/sret_pointer.ll
M llvm/test/CodeGen/Mips/GlobalISel/irtranslator/stack_args.ll
M llvm/test/CodeGen/Mips/GlobalISel/irtranslator/var_arg.ll
M llvm/test/CodeGen/Mips/GlobalISel/legalizer/ceil_and_floor.mir
M llvm/test/CodeGen/Mips/GlobalISel/legalizer/dyn_stackalloc.mir
M llvm/test/CodeGen/Mips/GlobalISel/legalizer/fptosi_and_fptoui.mir
M llvm/test/CodeGen/Mips/GlobalISel/legalizer/rem_and_div.mir
M llvm/test/CodeGen/Mips/GlobalISel/legalizer/sitofp_and_uitofp.mir
Log Message:
-----------
Mips/GlobalISel: Mark call's implicit RA def dead (#227233)
Co-authored-by: Claude Opus 5 <noreply at anthropic.com>
Commit: a4b0944bde4640586dd902d3ad401a6270c8a1fe
https://github.com/llvm/llvm-project/commit/a4b0944bde4640586dd902d3ad401a6270c8a1fe
Author: Gaëtan Bossu <gaetan.bossu at arm.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.h
M llvm/test/CodeGen/AArch64/named-vector-shuffle-reverse-sve.ll
Log Message:
-----------
[AArch64] ISel support for nxv1i1 vector_reverse (#226939)
This ensures llvm.vector.reverse can be selected for nxv1i1 types. These intrinsics can be generated by LoopVectorizer for `VF = vscale x 1` and loops iterating in reverse order.
Commit: d5f6c302fff1aeed8fb6a247c21a694b156778bc
https://github.com/llvm/llvm-project/commit/d5f6c302fff1aeed8fb6a247c21a694b156778bc
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M libcxx/docs/Hardening.rst
M libcxx/include/__configuration/attributes.h
Log Message:
-----------
[libc++] Encode the standard version in the ABI tag (#218527)
This prevents ODR mismatch issues from biting us across standard
versions. The order of elements in the ABI tag is now: libc++ version,
hardening mode, assertion semantic, exceptions, standard version.
Fixes #218524
Commit: 5c170b01350198b7f1f830fb53253652015077b3
https://github.com/llvm/llvm-project/commit/5c170b01350198b7f1f830fb53253652015077b3
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M llvm/lib/Target/Mips/MipsOptimizePICCall.cpp
A llvm/test/CodeGen/Mips/optimize-pic-call-dead-gp.ll
Log Message:
-----------
Mips: Mark the $gp setup copy dead when erasing the call's $gp use (#227216)
MipsOptimizePICCall drops the implicit $gp operand from a call when the
lazy binding stub for the callee has already run. The copy that set $gp
up for that call then has no reader left, but nothing flagged it, so the
MIR carried a live def until a later liveness recomputation cleaned it
up.
The pass already walks each block in order, so track the reaching
definition of $gp as it goes and mark it dead when the use is erased.
Co-authored-by: Claude Opus 5 <noreply at anthropic.com>
Commit: e0c49c0739807c8c75d38148babfa338d1e07f6a
https://github.com/llvm/llvm-project/commit/e0c49c0739807c8c75d38148babfa338d1e07f6a
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
A llvm/test/CodeGen/AArch64/GlobalISel/select-tls-macho.ll
Log Message:
-----------
AArch64/GlobalISel: Mark the LR def of the Mach-O TLS call dead (#227234)
The ordinary call path already does this, and the SelectionDAG emitter
marks unused implicit physreg defs dead for free. Without it the dead
flag needs to be reinferred later.
Co-authored-by: Claude Opus 5 <noreply at anthropic.com>
Commit: 5aa04826046edad5122d959688c0b8e9950f261f
https://github.com/llvm/llvm-project/commit/5aa04826046edad5122d959688c0b8e9950f261f
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCTargetDesc.cpp
A llvm/test/CodeGen/LoongArch/null-streamer.ll
Log Message:
-----------
LoongArch: Register a null target streamer (#226497)
Emitting a TLS variable's debug location calls into the target streamer,
which was only registered for asm and object output. -filetype=null
therefore null dereferenced.
Co-authored-by: Claude Opus 5 <noreply at anthropic.com>
Commit: 80cd6102a79c02763034fbf1b6a1473930b1d4ab
https://github.com/llvm/llvm-project/commit/80cd6102a79c02763034fbf1b6a1473930b1d4ab
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M llvm/lib/Target/LoongArch/LoongArchAsmPrinter.cpp
M llvm/lib/Target/LoongArch/LoongArchAsmPrinter.h
A llvm/test/CodeGen/LoongArch/module-target-abi.ll
Log Message:
-----------
LoongArch: Respect the target-abi module flag in the ELF header (#226498)
The target streamer read the ABI from MCTargetOptions when constructed,
so the e_flags recorded the command line -target-abi and ignored the
module flag.
Co-authored-by: Claude Opus 5 <noreply at anthropic.com>
Commit: b7bd84ff2a30e08e7f1bd2b36db5f8ec9ba300ee
https://github.com/llvm/llvm-project/commit/b7bd84ff2a30e08e7f1bd2b36db5f8ec9ba300ee
Author: Luke Lau <luke at igalia.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/conditional-scalar-assignment-fold-tail.ll
M llvm/test/Transforms/LoopVectorize/AArch64/conditional-scalar-assignment.ll
M llvm/test/Transforms/LoopVectorize/AArch64/findlast-epilogue-loop.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-select-cmp.ll
M llvm/test/Transforms/LoopVectorize/RISCV/conditional-scalar-assignment-fold-tail.ll
M llvm/test/Transforms/LoopVectorize/RISCV/conditional-scalar-assignment.ll
M llvm/test/Transforms/LoopVectorize/RISCV/iv-select-cmp.ll
M llvm/test/Transforms/LoopVectorize/RISCV/select-cmp-reduction.ll
M llvm/test/Transforms/LoopVectorize/VPlan/conditional-scalar-assignment-vplan.ll
M llvm/test/Transforms/LoopVectorize/VPlan/interleave-conditional-scalar-assignment-vplan.ll
M llvm/test/Transforms/LoopVectorize/X86/conditional-scalar-assignment.ll
M llvm/test/Transforms/LoopVectorize/alias-mask.ll
M llvm/test/Transforms/LoopVectorize/conditional-scalar-assignment-interleave-only.ll
M llvm/test/Transforms/LoopVectorize/find-last-iv-sinkable-expr-tail-folding.ll
M llvm/test/Transforms/LoopVectorize/find-last-iv-sinkable-expr.ll
M llvm/test/Transforms/LoopVectorize/find-last-iv-sinkable-load.ll
M llvm/test/Transforms/LoopVectorize/find-last-ptr-induction.ll
M llvm/test/Transforms/LoopVectorize/find-last.ll
M llvm/test/Transforms/LoopVectorize/iv-select-cmp-fold-tail.ll
M llvm/test/Transforms/LoopVectorize/iv-select-cmp-non-const-iv-start.ll
M llvm/test/Transforms/LoopVectorize/iv-select-cmp-trunc.ll
M llvm/test/Transforms/LoopVectorize/iv-select-cmp.ll
M llvm/test/Transforms/LoopVectorize/select-cmp.ll
Log Message:
-----------
[VPlan] Fix find last reductions not using frozen condition in select (#223962)
A find last reduction is something like:
(select c[n], x[n], (select c[n-1], x[n-1], (select ...)))
So even if previous iterations had poison for c[x], the top-level select
blocks it.
MaskSelect uses the non-frozen Cond, and that in turn is fed into
VPInstruction::ExtractLastActive, which in turn gets expanded to
vector.reduce.umax, which returns poison if any of the lanes were
poison.
So in the case e.g. c[n] = 1, c[n-1] = poison and VF=2, the scalar loop
returns x[n] whilst vector loop returns poison.
We're also introducing multiple uses of Cond which isn't sound for
undef, so for these reasons we need to use the frozen Cond.
Commit: bd9d96ce12d083a8de6e06c5dffd1b79a5cbef47
https://github.com/llvm/llvm-project/commit/bd9d96ce12d083a8de6e06c5dffd1b79a5cbef47
Author: Dharuni R Acharya <125176188+DharuniRAcharya at users.noreply.github.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M clang/include/clang/Basic/BuiltinsNVPTX.td
M clang/lib/CodeGen/TargetBuiltins/NVPTX.cpp
M clang/test/CodeGen/builtins-nvptx.c
M llvm/include/llvm/IR/IntrinsicsNVVM.td
M llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
M llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
A llvm/test/CodeGen/NVPTX/convert-fp4-pzo.ll
M mlir/lib/Dialect/LLVMIR/IR/NVVMDialect.cpp
M mlir/test/Target/LLVMIR/nvvm/convert_fp4x2.mlir
Log Message:
-----------
[clang][NVPTX] Add support for pzo in f32/f16x2/bf16x2 to FP4 conversions (#225318)
This patch adds support for `pzo` variants and `rz` rounding mode to
existing `f32/f16x2/bf16x2` to `FP4` (`e2m1x2`) conversion intrinsics.
Also adds `clang builtins` for the new variants.
Tests have been verified through `ptxas-13.4`.
PTX ISA Reference:
https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-cvt
---------
Signed-off-by: DharuniRAcharya <dharunira at nvidia.com>
Commit: 5da194580292bc90f6577f3959dda3a9bb6d5366
https://github.com/llvm/llvm-project/commit/5da194580292bc90f6577f3959dda3a9bb6d5366
Author: Anand Mistry (MSFT) <anandmistry at microsoft.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
M llvm/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp
M llvm/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.h
A llvm/test/MC/Mips/eva/set-eva-directive.s
A llvm/test/MC/Mips/eva/set-noeva-directive.s
Log Message:
-----------
[Mips] Add set directive support for EVA instructions (#225888)
Add assembler directives to enable/disable access to EVA instructions,
such as `cachee/lbe/sbe/tlbinv/etc`, with `.set eva/noeva`.
Commit: 5748da9e6a2e6eecfae8c35cc0a78073cde76c63
https://github.com/llvm/llvm-project/commit/5748da9e6a2e6eecfae8c35cc0a78073cde76c63
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-09-29 (Tue, 29 Sep 2026)
Changed paths:
M .github/workflows/libc-fullbuild-tests.yml
M .github/workflows/libc-overlay-tests.yml
M .github/workflows/libcxx-pr-benchmark.yml
M .github/workflows/libcxx-pr-test-tools.yml
M .github/workflows/test-suite.yml
M clang/docs/InternalsManual.md
M clang/docs/LibASTImporter.md
M clang/docs/ReleaseNotes.md
M clang/docs/UsersManual.md
M clang/include/clang/Basic/BuiltinsNVPTX.td
M clang/include/clang/CodeGen/CodeGenAction.h
M clang/include/clang/Interpreter/Interpreter.h
M clang/include/clang/Sema/Sema.h
M clang/lib/AST/ByteCode/Context.cpp
M clang/lib/AST/ByteCode/Context.h
M clang/lib/AST/ByteCode/EvalEmitter.cpp
M clang/lib/AST/ByteCode/EvalEmitter.h
A clang/lib/AST/ByteCode/EvalSettings.h
M clang/lib/AST/ByteCode/InterpState.cpp
M clang/lib/AST/ByteCode/InterpState.h
M clang/lib/AST/ExprConstant.cpp
M clang/lib/Analysis/LifetimeSafety/FactsGenerator.cpp
M clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
M clang/lib/CIR/CodeGen/CIRGenCoroutine.cpp
M clang/lib/CIR/CodeGen/CIRGenExprAggregate.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.cpp
M clang/lib/CodeGen/BackendConsumer.h
M clang/lib/CodeGen/CGExprScalar.cpp
M clang/lib/CodeGen/CGObjCRuntime.cpp
M clang/lib/CodeGen/CodeGenAction.cpp
M clang/lib/CodeGen/CodeGenPGO.cpp
M clang/lib/CodeGen/TargetBuiltins/NVPTX.cpp
M clang/lib/Headers/riscv_packed_simd.h
M clang/lib/Interpreter/CMakeLists.txt
M clang/lib/Interpreter/DeviceOffload.cpp
M clang/lib/Interpreter/DeviceOffload.h
M clang/lib/Interpreter/Interpreter.cpp
M clang/lib/Sema/SemaConcept.cpp
M clang/test/AST/ByteCode/new-delete.cpp
M clang/test/CIR/CodeGen/pack-indexing.cpp
A clang/test/CIR/CodeGenCoroutines/coro-agg.cpp
M clang/test/CXX/temp/temp.constr/temp.constr.normal/p1.cpp
M clang/test/CodeGen/AArch64/neon-intrinsics.c
M clang/test/CodeGen/AArch64/neon/intrinsics.c
M clang/test/CodeGen/RISCV/rvp-intrinsics.c
M clang/test/CodeGen/X86/sse41-builtins-constrained.c
M clang/test/CodeGen/X86/sse41-builtins.c
M clang/test/CodeGen/builtins-nvptx.c
M clang/test/CodeGenHLSL/BasicFeatures/MatrixElementTypeCast.hlsl
M clang/test/CodeGenHLSL/BasicFeatures/VectorElementwiseCast.hlsl
A clang/test/CodeGenObjC/exceptions-seh.m
M clang/test/Driver/Inputs/MacOSX15.0.sdk/SDKSettings.json
M clang/test/Driver/Inputs/MacOSX15.1.sdk/SDKSettings.json
M clang/test/Driver/modulemap-allow-subdirectory-search.c
M clang/test/InstallAPI/Inputs/MacOSX13.0.sdk/SDKSettings.json
M clang/test/Sema/LifetimeSafety/safety.cpp
R clang/test/SemaCXX/new-nothrow-by-value.cpp
M clang/unittests/Basic/CMakeLists.txt
R clang/unittests/Basic/TargetIDTest.cpp
M compiler-rt/test/builtins/Unit/arm/aeabi_cmpflags_interwork_test.c
M compiler-rt/test/profile/instrprof-thinlto-indirect-call-promotion.cpp
M cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c
M flang/include/flang/Optimizer/Builder/CUDAIntrinsicCall.h
M flang/include/flang/Optimizer/Builder/CUFCommon.h
M flang/include/flang/Optimizer/Dialect/CUF/CUFOps.td
M flang/include/flang/Optimizer/Transforms/Passes.td
M flang/include/flang/Support/Fortran-features.h
M flang/lib/Optimizer/Builder/CUDAIntrinsicCall.cpp
M flang/lib/Optimizer/Builder/CUFCommon.cpp
M flang/lib/Optimizer/Transforms/CMakeLists.txt
R flang/lib/Optimizer/Transforms/CUDA/CUFFunctionRewrite.cpp
M flang/lib/Optimizer/Transforms/CUDA/CUFOpConversion.cpp
M flang/lib/Optimizer/Transforms/CUDA/CUFOpConversionLate.cpp
M flang/lib/Semantics/check-acc-structure.cpp
M flang/lib/Semantics/check-acc-structure.h
M flang/lib/Semantics/check-declarations.cpp
R flang/test/Fir/CUDA/cuda-function-rewrite.mlir
A flang/test/Fir/CUDA/cuda-on-device.mlir
M flang/test/Fir/cuf.mlir
A flang/test/Lower/CUDA/cuda-on-device.cuf
A flang/test/Semantics/OpenACC/acc-routine-loop-nesting.f90
A flang/test/Semantics/bind-c20.f90
A flang/test/Semantics/bind-c21.f90
M libcxx/docs/Hardening.rst
M libcxx/include/__configuration/attributes.h
R libcxx/utils/ci/images/libcxx_next_runners.txt
R libcxx/utils/ci/images/libcxx_release_runners.txt
R libcxx/utils/ci/images/libcxx_runners.txt
M libcxxabi/src/cxa_personality.cpp
M libunwind/include/unwind_wasm.h
M libunwind/src/Unwind-wasm.c
M lld/test/ELF/pre_init_fini_array.s
M lld/test/wasm/check-arch-32-in-64.test
M lld/test/wasm/check-arch-64-in-32.test
M lld/wasm/InputFiles.cpp
M lldb/examples/python/templates/scripted_process.py
M lldb/packages/Python/lldbsuite/test/lldbplatform.py
M lldb/packages/Python/lldbsuite/test/lldbplatformutil.py
M lldb/test/API/functionalities/scripted_frame_provider/pass_through_prefix/TestFrameProviderPassThroughPrefix.py
M lldb/test/API/functionalities/scripted_frame_provider/pass_through_prefix/frame_provider.py
M llvm/include/llvm/IR/IRBuilder.h
M llvm/include/llvm/IR/IntrinsicsNVVM.td
M llvm/include/llvm/IR/RuntimeLibcalls.td
M llvm/include/llvm/ProfileData/InstrProf.h
M llvm/include/llvm/Target/CGPassBuilderOption.h
M llvm/include/llvm/Transforms/Scalar/GVN.h
A llvm/include/llvm/Transforms/Scalar/GVNHoist.h
A llvm/include/llvm/Transforms/Scalar/GVNSink.h
A llvm/include/llvm/Transforms/Scalar/GVNValueTable.h
M llvm/lib/Analysis/BlockFrequencyInfoImpl.cpp
M llvm/lib/Analysis/ScalarEvolution.cpp
M llvm/lib/CAS/UnifiedOnDiskCache.cpp
M llvm/lib/CodeGen/TargetPassConfig.cpp
M llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
M llvm/lib/CodeGen/WasmEHPrepare.cpp
M llvm/lib/MC/ELFObjectWriter.cpp
M llvm/lib/Passes/CodeGenPassBuilder.cpp
M llvm/lib/Passes/PassBuilder.cpp
M llvm/lib/Passes/PassBuilderPipelines.cpp
M llvm/lib/ProfileData/InstrProf.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.h
M llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
M llvm/lib/Target/AMDGPU/AMDGPULaneMaskUtils.h
M llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.h
M llvm/lib/Target/DirectX/DXILDataScalarization.cpp
M llvm/lib/Target/DirectX/DXILFlattenArrays.cpp
M llvm/lib/Target/DirectX/DXILLegalizePass.cpp
M llvm/lib/Target/DirectX/DXILMemIntrinsics.cpp
M llvm/lib/Target/DirectX/DXILOpLowering.cpp
M llvm/lib/Target/Hexagon/HexagonDepInstrInfo.td
M llvm/lib/Target/LoongArch/LoongArchAsmPrinter.cpp
M llvm/lib/Target/LoongArch/LoongArchAsmPrinter.h
M llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCTargetDesc.cpp
M llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
M llvm/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp
M llvm/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.h
M llvm/lib/Target/Mips/MipsCallLowering.cpp
M llvm/lib/Target/Mips/MipsFastISel.cpp
M llvm/lib/Target/Mips/MipsOptimizePICCall.cpp
M llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
M llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
M llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
M llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.h
M llvm/lib/Target/NVPTX/NVPTXUtilities.h
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoP.td
M llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86InstCombineIntrinsic.cpp
M llvm/lib/Transforms/IPO/FunctionAttrs.cpp
M llvm/lib/Transforms/IPO/MemProfContextDisambiguation.cpp
M llvm/lib/Transforms/Instrumentation/InstrProfiling.cpp
M llvm/lib/Transforms/Instrumentation/MemProfUse.cpp
M llvm/lib/Transforms/Instrumentation/PGOInstrumentation.cpp
M llvm/lib/Transforms/Scalar/GVN.cpp
M llvm/lib/Transforms/Scalar/GVNHoist.cpp
M llvm/lib/Transforms/Scalar/GVNSink.cpp
M llvm/lib/Transforms/Scalar/InferAddressSpaces.cpp
M llvm/lib/Transforms/Scalar/JumpTableToSwitch.cpp
M llvm/lib/Transforms/Scalar/TailRecursionElimination.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPMemoryUtils.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPShuffleAnalysis.h
M llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
M llvm/lib/Transforms/Vectorize/VPlanUtils.h
M llvm/lib/Transforms/Vectorize/VectorCombine.cpp
A llvm/test/Analysis/BlockFrequencyInfo/many-successors-order.ll
A llvm/test/Analysis/ScalarEvolution/trip-count-variable-stride-predicate.ll
A llvm/test/CodeGen/AArch64/GlobalISel/select-tls-macho.ll
M llvm/test/CodeGen/AArch64/O3-pipeline.ll
M llvm/test/CodeGen/AArch64/coalescer-empty-subrange-early-lis.ll
M llvm/test/CodeGen/AArch64/itofp-bf16.ll
M llvm/test/CodeGen/AArch64/named-vector-shuffle-reverse-sve.ll
M llvm/test/CodeGen/AArch64/pr161420.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-trunc.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/twoaddr-extract-dyn-v7f64.mir
M llvm/test/CodeGen/AMDGPU/a-v-flat-atomic-cmpxchg.ll
M llvm/test/CodeGen/AMDGPU/acc-ldst.ll
M llvm/test/CodeGen/AMDGPU/add_i128.ll
M llvm/test/CodeGen/AMDGPU/add_i64.ll
M llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.160bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.224bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.288bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.32bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.352bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.384bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.448bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.48bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.576bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.640bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.64bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.704bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.768bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-mul24-knownbits.ll
M llvm/test/CodeGen/AMDGPU/and.ll
M llvm/test/CodeGen/AMDGPU/any_extend_vector_inreg.ll
M llvm/test/CodeGen/AMDGPU/anyext.ll
M llvm/test/CodeGen/AMDGPU/asyncmark-gfx12plus.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomicrmw_usub_sat.ll
M llvm/test/CodeGen/AMDGPU/atomics-system-scope.ll
M llvm/test/CodeGen/AMDGPU/av-split-dead-valno-crash.ll
M llvm/test/CodeGen/AMDGPU/bf16-conversions.ll
M llvm/test/CodeGen/AMDGPU/bf16.ll
M llvm/test/CodeGen/AMDGPU/bitinsert-bitextract-fp.ll
M llvm/test/CodeGen/AMDGPU/bitinsert-bitextract.ll
M llvm/test/CodeGen/AMDGPU/bitreverse.ll
M llvm/test/CodeGen/AMDGPU/branch-folding-implicit-def-subreg.ll
M llvm/test/CodeGen/AMDGPU/bswap.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointers-memcpy.ll
M llvm/test/CodeGen/AMDGPU/bypass-div.ll
M llvm/test/CodeGen/AMDGPU/clmul.ll
M llvm/test/CodeGen/AMDGPU/consecutive-loads-in-branch.ll
M llvm/test/CodeGen/AMDGPU/copy-illegal-type.ll
M llvm/test/CodeGen/AMDGPU/copy-to-reg-scc-clobber.ll
M llvm/test/CodeGen/AMDGPU/ctlz.ll
M llvm/test/CodeGen/AMDGPU/ctlz_zero_poison.ll
M llvm/test/CodeGen/AMDGPU/ctpop.ll
M llvm/test/CodeGen/AMDGPU/ctpop16.ll
M llvm/test/CodeGen/AMDGPU/ctpop64.ll
M llvm/test/CodeGen/AMDGPU/cttz.ll
M llvm/test/CodeGen/AMDGPU/cttz_zero_poison.ll
M llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
M llvm/test/CodeGen/AMDGPU/dead-lane.mir
M llvm/test/CodeGen/AMDGPU/div_v2i128.ll
M llvm/test/CodeGen/AMDGPU/ds_gws_align.ll
M llvm/test/CodeGen/AMDGPU/dynamic-vgpr-reserve-stack-for-cwsr.ll
M llvm/test/CodeGen/AMDGPU/extract-subvector-16bit.ll
M llvm/test/CodeGen/AMDGPU/fadd.f16.ll
M llvm/test/CodeGen/AMDGPU/fceil64.ll
M llvm/test/CodeGen/AMDGPU/fcmp.f16.ll
M llvm/test/CodeGen/AMDGPU/fcopysign.bf16.ll
A llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-scc-cmp-wave32.mir
A llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-scc-cmp.mir
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64_noprivate.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system.ll
M llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp-fp8-hw.ll
M llvm/test/CodeGen/AMDGPU/fmax_legacy.f64.ll
M llvm/test/CodeGen/AMDGPU/fmin_legacy.f64.ll
M llvm/test/CodeGen/AMDGPU/fmul.f16.ll
M llvm/test/CodeGen/AMDGPU/fnearbyint.ll
M llvm/test/CodeGen/AMDGPU/fneg-combines.new.ll
M llvm/test/CodeGen/AMDGPU/fneg-modifier-casting.ll
M llvm/test/CodeGen/AMDGPU/fp-classify.ll
M llvm/test/CodeGen/AMDGPU/fp_to_sint.ll
M llvm/test/CodeGen/AMDGPU/fp_to_uint.ll
M llvm/test/CodeGen/AMDGPU/fpow.ll
M llvm/test/CodeGen/AMDGPU/fptoi.i128.ll
M llvm/test/CodeGen/AMDGPU/fptosi-sat-scalar.ll
M llvm/test/CodeGen/AMDGPU/fptosi.f16.ll
M llvm/test/CodeGen/AMDGPU/fptoui.f16.ll
M llvm/test/CodeGen/AMDGPU/fptrunc.ll
M llvm/test/CodeGen/AMDGPU/freeze.ll
M llvm/test/CodeGen/AMDGPU/frem.ll
M llvm/test/CodeGen/AMDGPU/fshl.ll
M llvm/test/CodeGen/AMDGPU/fsqrt.f64.ll
M llvm/test/CodeGen/AMDGPU/fsub.f16.ll
M llvm/test/CodeGen/AMDGPU/gfx-callable-return-types.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/global-load-xcnt.ll
M llvm/test/CodeGen/AMDGPU/half.ll
M llvm/test/CodeGen/AMDGPU/hsa-metadata-kernel-code-props.ll
M llvm/test/CodeGen/AMDGPU/identical-subrange-spill-infloop.ll
M llvm/test/CodeGen/AMDGPU/idot2.ll
M llvm/test/CodeGen/AMDGPU/idot4s.ll
M llvm/test/CodeGen/AMDGPU/idot4u.ll
M llvm/test/CodeGen/AMDGPU/idot8u.ll
M llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll
M llvm/test/CodeGen/AMDGPU/indirect-call.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_elt.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll
M llvm/test/CodeGen/AMDGPU/lds-misaligned-bug.ll
M llvm/test/CodeGen/AMDGPU/literal64.ll
M llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll
M llvm/test/CodeGen/AMDGPU/llc-pipeline.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.class.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dual_intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.atomic.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.dim.gfx90a.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.dim.gfx90a.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.scale.f32.32x32x64.f8f6f4.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fadd.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fsub.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.set.inactive.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.smfmac.gfx950.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp10.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp10.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp2.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp2.ll
M llvm/test/CodeGen/AMDGPU/llvm.fma.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.ll
M llvm/test/CodeGen/AMDGPU/llvm.log.ll
M llvm/test/CodeGen/AMDGPU/llvm.log10.ll
M llvm/test/CodeGen/AMDGPU/llvm.log2.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.maxnum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.minimum.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.minnum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.round.f64.ll
M llvm/test/CodeGen/AMDGPU/llvm.round.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i16.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i32.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i64.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i8.ll
M llvm/test/CodeGen/AMDGPU/load-global-f32.ll
M llvm/test/CodeGen/AMDGPU/load-global-i16.ll
M llvm/test/CodeGen/AMDGPU/load-global-i32.ll
M llvm/test/CodeGen/AMDGPU/load-global-i8.ll
M llvm/test/CodeGen/AMDGPU/load-local-i16.ll
M llvm/test/CodeGen/AMDGPU/lower-control-flow-live-variables-update.mir
M llvm/test/CodeGen/AMDGPU/lower-ctor-dtor.ll
M llvm/test/CodeGen/AMDGPU/machine-sink-temporal-divergence-swdev407790.ll
M llvm/test/CodeGen/AMDGPU/mad-combine.ll
M llvm/test/CodeGen/AMDGPU/mad_uint24.ll
M llvm/test/CodeGen/AMDGPU/max.ll
M llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll
M llvm/test/CodeGen/AMDGPU/merge-stores.ll
M llvm/test/CodeGen/AMDGPU/mfma-cd-select.ll
M llvm/test/CodeGen/AMDGPU/mfma-no-register-aliasing.ll
M llvm/test/CodeGen/AMDGPU/min.ll
M llvm/test/CodeGen/AMDGPU/mixed-vmem-types.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-atomicrmw-system.ll
M llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands-non-ptr-intrinsics.ll
M llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands.ll
M llvm/test/CodeGen/AMDGPU/mul.ll
M llvm/test/CodeGen/AMDGPU/mul_uint24-amdgcn.ll
M llvm/test/CodeGen/AMDGPU/no-remat-indirect-mov.mir
M llvm/test/CodeGen/AMDGPU/operand-folding.ll
M llvm/test/CodeGen/AMDGPU/or.ll
M llvm/test/CodeGen/AMDGPU/packed-fp32.ll
M llvm/test/CodeGen/AMDGPU/packed-fp64.ll
M llvm/test/CodeGen/AMDGPU/packed-u64.ll
M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll
M llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.ll
M llvm/test/CodeGen/AMDGPU/rewrite-mfma-single-exit-copy.ll
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-reserved-wwm-vgpr.ll
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-spill-joint-dom.ll
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr.ll
M llvm/test/CodeGen/AMDGPU/rsq.f64.ll
M llvm/test/CodeGen/AMDGPU/saddo.ll
M llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll
M llvm/test/CodeGen/AMDGPU/schedule-relaxed-occupancy.ll
M llvm/test/CodeGen/AMDGPU/scmp.ll
M llvm/test/CodeGen/AMDGPU/scratch-simple.ll
M llvm/test/CodeGen/AMDGPU/sdiv.ll
M llvm/test/CodeGen/AMDGPU/select.f16.ll
M llvm/test/CodeGen/AMDGPU/setcc-f64-hi32mask.ll
M llvm/test/CodeGen/AMDGPU/shift-and-i64-ubfe.ll
M llvm/test/CodeGen/AMDGPU/shl.ll
M llvm/test/CodeGen/AMDGPU/shl.v2i64.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll
M llvm/test/CodeGen/AMDGPU/sint_to_fp.i64.ll
M llvm/test/CodeGen/AMDGPU/sminmax.v2i16.ll
M llvm/test/CodeGen/AMDGPU/spill-scavenge-offset.ll
M llvm/test/CodeGen/AMDGPU/spill-vgpr.ll
M llvm/test/CodeGen/AMDGPU/splitkit-getsubrangeformask-phi-extend.ll
M llvm/test/CodeGen/AMDGPU/sra.ll
M llvm/test/CodeGen/AMDGPU/srem.ll
M llvm/test/CodeGen/AMDGPU/srl.ll
M llvm/test/CodeGen/AMDGPU/ssubo.ll
M llvm/test/CodeGen/AMDGPU/sub.ll
M llvm/test/CodeGen/AMDGPU/twoaddr-constrain.ll
M llvm/test/CodeGen/AMDGPU/ucmp.ll
M llvm/test/CodeGen/AMDGPU/udiv.ll
M llvm/test/CodeGen/AMDGPU/uint_to_fp.i64.ll
M llvm/test/CodeGen/AMDGPU/umin-sub-to-usubo-select-combine.ll
M llvm/test/CodeGen/AMDGPU/undef-handling-crash-in-ra.ll
M llvm/test/CodeGen/AMDGPU/undefined-subreg-liverange.ll
M llvm/test/CodeGen/AMDGPU/unspill-vgpr-after-rewrite-vgpr-mfma.ll
M llvm/test/CodeGen/AMDGPU/urem64.ll
M llvm/test/CodeGen/AMDGPU/v_madak_f16.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fmaximum.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fminimum.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-smax.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-smin.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-umax.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-umin.ll
M llvm/test/CodeGen/AMDGPU/vgpr-mark-last-scratch-load.ll
M llvm/test/CodeGen/AMDGPU/vni8-across-blocks.ll
M llvm/test/CodeGen/AMDGPU/vselect.ll
M llvm/test/CodeGen/AMDGPU/waitcnt-loop-ds-prefetch-pattern.ll
M llvm/test/CodeGen/AMDGPU/wave32.ll
M llvm/test/CodeGen/AMDGPU/widen-vselect-and-mask.ll
M llvm/test/CodeGen/AMDGPU/wqm.ll
M llvm/test/CodeGen/AMDGPU/xor.ll
M llvm/test/CodeGen/ARM/O3-pipeline.ll
M llvm/test/CodeGen/ARM/fp-intrinsics-vector.ll
M llvm/test/CodeGen/ARM/inlineasm-operand-implicit-cast.ll
M llvm/test/CodeGen/ARM/llvm.modf.ll
M llvm/test/CodeGen/ARM/llvm.sincos.ll
M llvm/test/CodeGen/ARM/signext-inreg.ll
M llvm/test/CodeGen/ARM/vldlane.ll
M llvm/test/CodeGen/DirectX/bugfix_150050_data_scalarize_const_gep.ll
M llvm/test/CodeGen/DirectX/flatten-array.ll
M llvm/test/CodeGen/DirectX/flatten-bug-117273.ll
M llvm/test/CodeGen/DirectX/legalize-i8.ll
M llvm/test/CodeGen/DirectX/llc-vector-load-scalarize.ll
M llvm/test/CodeGen/DirectX/scalar-store.ll
M llvm/test/CodeGen/DirectX/scalarize-static-array-of-float-vectors.ll
M llvm/test/CodeGen/Hexagon/addh.ll
M llvm/test/CodeGen/Hexagon/cttz-elts-widen.ll
M llvm/test/CodeGen/Hexagon/isel-extload-i1.ll
M llvm/test/CodeGen/Hexagon/mulhs.ll
M llvm/test/CodeGen/Hexagon/swp-vect-dotprod.ll
A llvm/test/CodeGen/LoongArch/module-target-abi.ll
A llvm/test/CodeGen/LoongArch/null-streamer.ll
M llvm/test/CodeGen/LoongArch/opt-pipeline.ll
M llvm/test/CodeGen/M68k/pipeline.ll
A llvm/test/CodeGen/Mips/Fast-ISel/mul-dead-hilo.ll
M llvm/test/CodeGen/Mips/GlobalISel/irtranslator/aggregate_struct_return.ll
M llvm/test/CodeGen/Mips/GlobalISel/irtranslator/call.ll
M llvm/test/CodeGen/Mips/GlobalISel/irtranslator/extend_args.ll
M llvm/test/CodeGen/Mips/GlobalISel/irtranslator/float_args.ll
M llvm/test/CodeGen/Mips/GlobalISel/irtranslator/global_address.ll
M llvm/test/CodeGen/Mips/GlobalISel/irtranslator/global_address_pic.ll
M llvm/test/CodeGen/Mips/GlobalISel/irtranslator/sret_pointer.ll
M llvm/test/CodeGen/Mips/GlobalISel/irtranslator/stack_args.ll
M llvm/test/CodeGen/Mips/GlobalISel/irtranslator/var_arg.ll
M llvm/test/CodeGen/Mips/GlobalISel/legalizer/ceil_and_floor.mir
M llvm/test/CodeGen/Mips/GlobalISel/legalizer/dyn_stackalloc.mir
M llvm/test/CodeGen/Mips/GlobalISel/legalizer/fptosi_and_fptoui.mir
M llvm/test/CodeGen/Mips/GlobalISel/legalizer/rem_and_div.mir
M llvm/test/CodeGen/Mips/GlobalISel/legalizer/sitofp_and_uitofp.mir
A llvm/test/CodeGen/Mips/optimize-pic-call-dead-gp.ll
M llvm/test/CodeGen/NVPTX/call_bitcast_byval.ll
M llvm/test/CodeGen/NVPTX/callchain.ll
A llvm/test/CodeGen/NVPTX/convert-fp4-pzo.ll
M llvm/test/CodeGen/NVPTX/empty-type.ll
M llvm/test/CodeGen/NVPTX/forward-ld-param.ll
A llvm/test/CodeGen/NVPTX/fp-global.ll
M llvm/test/CodeGen/NVPTX/i1-param.ll
A llvm/test/CodeGen/NVPTX/infer-volatile-address-spaces.ll
M llvm/test/CodeGen/NVPTX/local-stack-frame.ll
M llvm/test/CodeGen/NVPTX/lower-byval-args.ll
M llvm/test/CodeGen/NVPTX/managed.ll
M llvm/test/CodeGen/NVPTX/noreturn.ll
A llvm/test/CodeGen/NVPTX/odd-integer-width.ll
M llvm/test/CodeGen/NVPTX/param-align.ll
A llvm/test/CodeGen/NVPTX/ptr-global.ll
M llvm/test/CodeGen/NVPTX/vector-global.ll
M llvm/test/CodeGen/PowerPC/O3-pipeline.ll
M llvm/test/CodeGen/PowerPC/dmr-copy.ll
M llvm/test/CodeGen/PowerPC/dmr-enable.ll
M llvm/test/CodeGen/PowerPC/no-rlwimi-trivial-commute.mir
M llvm/test/CodeGen/RISCV/O3-newpm-pipeline.ll
M llvm/test/CodeGen/RISCV/O3-pipeline.ll
M llvm/test/CodeGen/RISCV/rvp-simd-32.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-subvector.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll
M llvm/test/CodeGen/RISCV/rvv/fmaximum-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fminimum-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vfmsub-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vwadd.w.ll
M llvm/test/CodeGen/SPIRV/legalization/signed-narrow-int.ll
M llvm/test/CodeGen/SystemZ/atomicrmw-ops-i128.ll
M llvm/test/CodeGen/SystemZ/atomicrmw-xchg-07.ll
M llvm/test/CodeGen/SystemZ/rot-02.ll
M llvm/test/CodeGen/SystemZ/subregliveness-01.ll
M llvm/test/CodeGen/Thumb/emergency-spill-slot.ll
M llvm/test/CodeGen/Thumb2/mve-clmul.ll
M llvm/test/CodeGen/Thumb2/mve-complex-deinterleaving-f64-add.ll
M llvm/test/CodeGen/Thumb2/mve-complex-deinterleaving-f64-mul.ll
M llvm/test/CodeGen/Thumb2/mve-complex-deinterleaving-mixed-cases.ll
M llvm/test/CodeGen/Thumb2/mve-complex-deinterleaving-uniform-cases.ll
M llvm/test/CodeGen/Thumb2/mve-ctlz.ll
M llvm/test/CodeGen/Thumb2/mve-fmath.ll
M llvm/test/CodeGen/Thumb2/mve-insertshuffleload.ll
M llvm/test/CodeGen/Thumb2/mve-laneinterleaving-cost.ll
M llvm/test/CodeGen/Thumb2/mve-laneinterleaving.ll
M llvm/test/CodeGen/Thumb2/mve-multivec-spill.ll
M llvm/test/CodeGen/Thumb2/mve-pred-shuffle.ll
M llvm/test/CodeGen/Thumb2/mve-saturating-arith.ll
M llvm/test/CodeGen/Thumb2/mve-sext-masked-load.ll
M llvm/test/CodeGen/Thumb2/mve-shuffle-fp16.ll
M llvm/test/CodeGen/Thumb2/mve-shuffle.ll
M llvm/test/CodeGen/Thumb2/mve-shuffleext.ll
M llvm/test/CodeGen/Thumb2/mve-shufflemov.ll
M llvm/test/CodeGen/Thumb2/mve-vabdus.ll
M llvm/test/CodeGen/Thumb2/mve-vcvt16.ll
M llvm/test/CodeGen/Thumb2/mve-vld2.ll
M llvm/test/CodeGen/Thumb2/mve-vld3.ll
M llvm/test/CodeGen/Thumb2/mve-vld4-post.ll
M llvm/test/CodeGen/Thumb2/mve-vld4.ll
M llvm/test/CodeGen/Thumb2/mve-vldst4.ll
M llvm/test/CodeGen/Thumb2/mve-vst2.ll
M llvm/test/CodeGen/Thumb2/mve-vst3.ll
M llvm/test/CodeGen/Thumb2/mve-vst4-post.ll
M llvm/test/CodeGen/Thumb2/mve-vst4.ll
M llvm/test/CodeGen/Thumb2/mve-zext-masked-load.ll
M llvm/test/CodeGen/WebAssembly/eh-lsda.ll
M llvm/test/CodeGen/WebAssembly/exception-legacy.ll
M llvm/test/CodeGen/WebAssembly/exception.ll
M llvm/test/CodeGen/WebAssembly/wasm-eh-prepare.ll
M llvm/test/CodeGen/X86/active_lane_mask.ll
M llvm/test/CodeGen/X86/addcarry.ll
M llvm/test/CodeGen/X86/apx/mul-i1024.ll
M llvm/test/CodeGen/X86/apx/pr191368.ll
M llvm/test/CodeGen/X86/apx/push2-pop2.ll
M llvm/test/CodeGen/X86/bit-manip-i512.ll
M llvm/test/CodeGen/X86/bitselect.ll
M llvm/test/CodeGen/X86/clmul-vector.ll
M llvm/test/CodeGen/X86/combine-bitselect.ll
M llvm/test/CodeGen/X86/combine-or.ll
M llvm/test/CodeGen/X86/combine-rotates.ll
M llvm/test/CodeGen/X86/div-rem-pair-recomposition-unsigned.ll
M llvm/test/CodeGen/X86/fpclamptosat_vec.ll
M llvm/test/CodeGen/X86/ftrunc.ll
M llvm/test/CodeGen/X86/funnel-shift-i512.ll
M llvm/test/CodeGen/X86/half.ll
M llvm/test/CodeGen/X86/i128-udiv.ll
M llvm/test/CodeGen/X86/icmp-abs-C.ll
M llvm/test/CodeGen/X86/inline-asm-A-constraint.ll
M llvm/test/CodeGen/X86/llc-pipeline-npm.ll
M llvm/test/CodeGen/X86/machine-combiner-int-vec.ll
M llvm/test/CodeGen/X86/machine-cse.ll
M llvm/test/CodeGen/X86/masked-urem.ll
M llvm/test/CodeGen/X86/midpoint-int-vec-128.ll
M llvm/test/CodeGen/X86/midpoint-int.ll
M llvm/test/CodeGen/X86/mul-i1024.ll
M llvm/test/CodeGen/X86/mul-i256.ll
M llvm/test/CodeGen/X86/mul-i512.ll
M llvm/test/CodeGen/X86/mul-shift-reassoc.ll
M llvm/test/CodeGen/X86/mul128.ll
M llvm/test/CodeGen/X86/neg-abs.ll
M llvm/test/CodeGen/X86/oddshuffles.ll
M llvm/test/CodeGen/X86/opt-pipeline.ll
M llvm/test/CodeGen/X86/pr46877.ll
M llvm/test/CodeGen/X86/scalar-minmax-simd.ll
M llvm/test/CodeGen/X86/shift-amount-mod.ll
M llvm/test/CodeGen/X86/shift-and.ll
M llvm/test/CodeGen/X86/statepoint-cmp-sunk-past-statepoint.ll
M llvm/test/CodeGen/X86/statepoint-relocate-eh.ll
M llvm/test/CodeGen/X86/statepoint-vreg-unlimited-tied-opnds.ll
M llvm/test/CodeGen/X86/ternlog.ll
M llvm/test/CodeGen/X86/two-address-subreg-to-reg-kill.mir
M llvm/test/CodeGen/X86/twoaddr-lea-eflags-liveintervals.ll
M llvm/test/CodeGen/X86/ucmp.ll
M llvm/test/CodeGen/X86/unfold-masked-merge-vector-variablemask.ll
M llvm/test/CodeGen/X86/vec_umulo.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-3.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-3.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-3.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-8.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-3.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-8.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-3.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-8.ll
M llvm/test/CodeGen/X86/vector-lzcnt-128.ll
M llvm/test/CodeGen/X86/vector-partial-reduce-sumla.ll
M llvm/test/CodeGen/X86/vector-partial-reduce-umla.ll
M llvm/test/CodeGen/X86/vector-reduce-ctpop.ll
M llvm/test/CodeGen/X86/vector-reduce-smax.ll
M llvm/test/CodeGen/X86/vector-reduce-smin.ll
M llvm/test/CodeGen/X86/vector-reduce-umax.ll
M llvm/test/CodeGen/X86/vector-reduce-umin.ll
M llvm/test/CodeGen/X86/vector-trunc-packus.ll
M llvm/test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll
M llvm/test/CodeGen/X86/widen_arith-2.ll
M llvm/test/CodeGen/X86/widen_bitcnt.ll
M llvm/test/CodeGen/X86/zext-trunc.ll
M llvm/test/DebugInfo/MIR/X86/mlicm-hoist-post-regalloc.mir
M llvm/test/DebugInfo/NVPTX/debug-info.ll
M llvm/test/Instrumentation/cgprofile.ll
M llvm/test/MC/AsmParser/section_names.s
M llvm/test/MC/ELF/section.s
A llvm/test/MC/Hexagon/v79-nontemporal.s
A llvm/test/MC/Mips/eva/set-eva-directive.s
A llvm/test/MC/Mips/eva/set-noeva-directive.s
M llvm/test/Transforms/FunctionAttrs/noalias.ll
A llvm/test/Transforms/InferAddressSpaces/NVPTX/volatile.ll
M llvm/test/Transforms/InstCombine/AMDGPU/llvm.amdgcn.sudot.ll
M llvm/test/Transforms/InstCombine/X86/x86-avx512-inseltpoison.ll
M llvm/test/Transforms/JumpTableToSwitch/profile-no-guid-metadata.ll
M llvm/test/Transforms/JumpThreading/thread-prob-1.ll
M llvm/test/Transforms/LoopVectorize/AArch64/conditional-scalar-assignment-fold-tail.ll
M llvm/test/Transforms/LoopVectorize/AArch64/conditional-scalar-assignment.ll
M llvm/test/Transforms/LoopVectorize/AArch64/findlast-epilogue-loop.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-select-cmp.ll
M llvm/test/Transforms/LoopVectorize/RISCV/conditional-scalar-assignment-fold-tail.ll
M llvm/test/Transforms/LoopVectorize/RISCV/conditional-scalar-assignment.ll
M llvm/test/Transforms/LoopVectorize/RISCV/iv-select-cmp.ll
M llvm/test/Transforms/LoopVectorize/RISCV/select-cmp-reduction.ll
M llvm/test/Transforms/LoopVectorize/VPlan/conditional-scalar-assignment-vplan.ll
M llvm/test/Transforms/LoopVectorize/VPlan/execution-frequencies-match-bfi.ll
M llvm/test/Transforms/LoopVectorize/VPlan/interleave-conditional-scalar-assignment-vplan.ll
M llvm/test/Transforms/LoopVectorize/VPlan/record-execution-frequencies.ll
M llvm/test/Transforms/LoopVectorize/VPlan/vplan-based-stride-mv.ll
M llvm/test/Transforms/LoopVectorize/VPlan/vplan-printing-branch-weights.ll
M llvm/test/Transforms/LoopVectorize/X86/conditional-scalar-assignment.ll
M llvm/test/Transforms/LoopVectorize/alias-mask.ll
M llvm/test/Transforms/LoopVectorize/conditional-scalar-assignment-interleave-only.ll
M llvm/test/Transforms/LoopVectorize/find-last-iv-sinkable-expr-tail-folding.ll
M llvm/test/Transforms/LoopVectorize/find-last-iv-sinkable-expr.ll
M llvm/test/Transforms/LoopVectorize/find-last-iv-sinkable-load.ll
M llvm/test/Transforms/LoopVectorize/find-last-ptr-induction.ll
M llvm/test/Transforms/LoopVectorize/find-last.ll
M llvm/test/Transforms/LoopVectorize/iv-select-cmp-fold-tail.ll
M llvm/test/Transforms/LoopVectorize/iv-select-cmp-non-const-iv-start.ll
M llvm/test/Transforms/LoopVectorize/iv-select-cmp-trunc.ll
M llvm/test/Transforms/LoopVectorize/iv-select-cmp.ll
A llvm/test/Transforms/LoopVectorize/scev-variable-stride-predicate.ll
M llvm/test/Transforms/LoopVectorize/select-cmp.ll
M llvm/test/Transforms/PGOProfile/Inputs/cspgo_bar_sample.ll
M llvm/test/Transforms/PGOProfile/Inputs/thinlto_cspgo_bar_gen.ll
M llvm/test/Transforms/PGOProfile/Inputs/thinlto_cspgo_bar_use.ll
M llvm/test/Transforms/PGOProfile/icp_invoke.ll
M llvm/test/Transforms/PGOProfile/icp_invoke_nouse.ll
M llvm/test/Transforms/PGOProfile/thinlto_indirect_call_promotion.ll
M llvm/test/Transforms/SampleProfile/pseudo-probe-twoaddr.ll
A llvm/test/Transforms/TailCallElim/return-value-select-pgo.ll
M llvm/test/Transforms/VectorCombine/binop-scalarize.ll
A llvm/test/Transforms/VectorCombine/cmp-scalarize.ll
M llvm/test/Transforms/VectorCombine/unary-op-scalarize.ll
M llvm/test/lit.cfg.py
M llvm/test/tools/dxil-dis/constantexpr-gep.ll
M llvm/test/tools/gold/X86/Inputs/thinlto_cspgo_bar.ll
A llvm/test/tools/llvm-cas/validate-if-needed.test
A llvm/test/tools/llvm-profdata/Inputs/guid-roundtrip.c
A llvm/test/tools/llvm-profdata/Inputs/guid-roundtrip.proftext
A llvm/test/tools/llvm-profdata/guid-roundtrip.test
R llvm/test/tools/llvm-readobj/ELF/RISCV/eflags-abi.test
A llvm/test/tools/llvm-readobj/ELF/RISCV/eflags.test
M llvm/tools/llvm-profgen/PerfReader.cpp
M llvm/unittests/ProfileData/InstrProfTest.cpp
M llvm/utils/gn/build/BUILD.gn
M llvm/utils/gn/build/BUILDCONFIG.gn
M llvm/utils/gn/build/mac_sdk.gni
M llvm/utils/gn/secondary/clang/include/clang/Config/BUILD.gn
M llvm/utils/gn/secondary/clang/tools/clang-repl/BUILD.gn
M llvm/utils/gn/secondary/clang/unittests/Interpreter/BUILD.gn
M llvm/utils/gn/secondary/llvm/tools/llc/BUILD.gn
M llvm/utils/gn/secondary/llvm/tools/lli/BUILD.gn
M llvm/utils/gn/secondary/llvm/tools/llvm-jitlink/BUILD.gn
M llvm/utils/gn/secondary/llvm/tools/opt/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/Analysis/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/CodeGen/CGPluginTest/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/ExecutionEngine/Orc/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/Passes/Plugins/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/Support/DynamicLibrary/BUILD.gn
M llvm/utils/gn/secondary/third-party/unittest/unittest.gni
M llvm/utils/profcheck-xfail.txt
M mlir/include/mlir/Dialect/ControlFlow/IR/ControlFlowOps.td
M mlir/include/mlir/Dialect/OpenACC/OpenACCCGAttributes.td
M mlir/include/mlir/Dialect/OpenACC/OpenACCUtilsCG.h
M mlir/include/mlir/Dialect/SCF/IR/SCFOps.td
M mlir/include/mlir/IR/Diagnostics.h
M mlir/include/mlir/Target/Cpp/CppEmitter.h
M mlir/lib/Conversion/SCFToControlFlow/SCFToControlFlow.cpp
M mlir/lib/Conversion/SCFToGPU/SCFToGPU.cpp
M mlir/lib/Conversion/SCFToOpenMP/SCFToOpenMP.cpp
M mlir/lib/Dialect/Async/Transforms/AsyncParallelFor.cpp
M mlir/lib/Dialect/ControlFlow/IR/ControlFlowOps.cpp
M mlir/lib/Dialect/LLVMIR/IR/NVVMDialect.cpp
M mlir/lib/Dialect/OpenACC/Transforms/ACCComputeLowering.cpp
M mlir/lib/Dialect/OpenACC/Utils/OpenACCUtilsCG.cpp
M mlir/lib/Dialect/SCF/IR/SCF.cpp
M mlir/lib/Dialect/SCF/Transforms/ParallelForToNestedFors.cpp
M mlir/lib/Dialect/SCF/Transforms/ParallelLoopCollapsing.cpp
M mlir/lib/Dialect/SCF/Transforms/ParallelLoopFusion.cpp
M mlir/lib/Dialect/SCF/Transforms/ParallelLoopTiling.cpp
M mlir/lib/IR/Diagnostics.cpp
M mlir/lib/Target/LLVMIR/Dialect/LLVMIR/LLVMToLLVMIRTranslation.cpp
M mlir/lib/Tools/mlir-opt/MlirOptMain.cpp
M mlir/test/Conversion/SCFToControlFlow/convert-to-cfg.mlir
M mlir/test/Conversion/SCFToGPU/parallel_loop.mlir
A mlir/test/Conversion/SCFToOpenMP/scf-to-openmp-unsigned.mlir
M mlir/test/Dialect/Async/async-parallel-for-async-dispatch.mlir
M mlir/test/Dialect/ControlFlow/canonicalize.mlir
M mlir/test/Dialect/ControlFlow/invalid.mlir
M mlir/test/Dialect/ControlFlow/ops.mlir
M mlir/test/Dialect/OpenACC/acc-compute-lowering-loop.mlir
M mlir/test/Dialect/SCF/ops.mlir
M mlir/test/Dialect/SCF/parallel-loop-fusion.mlir
M mlir/test/Dialect/SCF/parallel-loop-tiling-inbound-check.mlir
M mlir/test/Dialect/SCF/parallel-to-nested-fors.mlir
A mlir/test/Pass/remark-final-verify-diagnostics.mlir
M mlir/test/Target/LLVMIR/llvmir-invalid.mlir
M mlir/test/Target/LLVMIR/nvvm/convert_fp4x2.mlir
A mlir/test/Transforms/parallel-loop-collapsing-unsigned.mlir
M mlir/unittests/Dialect/OpenACC/OpenACCUtilsCGTest.cpp
M mlir/unittests/IR/Diagnostic.cpp
M polly/lib/Transform/ScheduleOptimizer.cpp
A polly/test/ScheduleOptimizer/simplify_deps_bounded_proximity.ll
M utils/bazel/llvm-project-overlay/flang/lib/Optimizer/Builder/BUILD.bazel
Log Message:
-----------
Rebase
Created using spr 1.3.7
Compare: https://github.com/llvm/llvm-project/compare/650a674314dd...5748da9e6a2e
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