[all-commits] [llvm/llvm-project] 74c86a: [AMDGPU] Use S_CMP to lower a copy of a lane mask ...

[Jay Foad via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 74c86a79968b3f23eb3b292d318429364709f6b2
      https://github.com/llvm/llvm-project/commit/74c86a79968b3f23eb3b292d318429364709f6b2
  Author: Jay Foad <jay.foad at amd.com>
  Date:   2026-09-29 (Tue, 29 Sep 2026)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPULaneMaskUtils.h
    M llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
    M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
    M llvm/lib/Target/AMDGPU/SIInstrInfo.h
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
    M llvm/test/CodeGen/AMDGPU/anyext.ll
    M llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
    M llvm/test/CodeGen/AMDGPU/bf16-conversions.ll
    M llvm/test/CodeGen/AMDGPU/copy-to-reg-scc-clobber.ll
    M llvm/test/CodeGen/AMDGPU/extract-subvector-16bit.ll
    M llvm/test/CodeGen/AMDGPU/fcmp.f16.ll
    M llvm/test/CodeGen/AMDGPU/fcopysign.bf16.ll
    A llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-scc-cmp-wave32.mir
    A llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-scc-cmp.mir
    M llvm/test/CodeGen/AMDGPU/fneg-combines.new.ll
    M llvm/test/CodeGen/AMDGPU/fneg-modifier-casting.ll
    M llvm/test/CodeGen/AMDGPU/fp-classify.ll
    M llvm/test/CodeGen/AMDGPU/fp_to_sint.ll
    M llvm/test/CodeGen/AMDGPU/fp_to_uint.ll
    M llvm/test/CodeGen/AMDGPU/fpow.ll
    M llvm/test/CodeGen/AMDGPU/fptosi-sat-scalar.ll
    M llvm/test/CodeGen/AMDGPU/fptosi.f16.ll
    M llvm/test/CodeGen/AMDGPU/fptoui.f16.ll
    M llvm/test/CodeGen/AMDGPU/frem.ll
    M llvm/test/CodeGen/AMDGPU/fsqrt.f64.ll
    M llvm/test/CodeGen/AMDGPU/literal64.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.class.f16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.exp2.ll
    M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.ll
    M llvm/test/CodeGen/AMDGPU/llvm.log.ll
    M llvm/test/CodeGen/AMDGPU/llvm.log10.ll
    M llvm/test/CodeGen/AMDGPU/llvm.log2.ll
    M llvm/test/CodeGen/AMDGPU/max.ll
    M llvm/test/CodeGen/AMDGPU/min.ll
    M llvm/test/CodeGen/AMDGPU/mixed-vmem-types.ll
    M llvm/test/CodeGen/AMDGPU/or.ll
    M llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.ll
    M llvm/test/CodeGen/AMDGPU/rsq.f64.ll
    M llvm/test/CodeGen/AMDGPU/saddo.ll
    M llvm/test/CodeGen/AMDGPU/scmp.ll
    M llvm/test/CodeGen/AMDGPU/setcc-f64-hi32mask.ll
    M llvm/test/CodeGen/AMDGPU/ssubo.ll
    M llvm/test/CodeGen/AMDGPU/ucmp.ll
    M llvm/test/CodeGen/AMDGPU/umin-sub-to-usubo-select-combine.ll
    M llvm/test/CodeGen/AMDGPU/wave32.ll

  Log Message:
  -----------
  [AMDGPU] Use S_CMP to lower a copy of a lane mask to SCC (#221445)

SIFixSGPRCopies lowers a copy of a lane mask to SCC as an AND with EXEC,
whose destination register is created by the pass and is always dead.
The AND with EXEC is only needed because SCC has to be "any active lane
is set". When the lane mask already has 0 in the bits of all inactive
lanes, that is just "the mask is non-zero", which S_CMP computes without
needing a destination register. In some cases the S_CMP can be optimized
away later by SIInstrInfo::optimizeCompareInstr.

Co-authored-by: Claude Opus 5 (1M context) <noreply at anthropic.com>



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