[all-commits] [llvm/llvm-project] 46dc3d: Legalize sgpr16 in sdag

Guo Chen via All-commits all-commits at lists.llvm.org
Mon Sep 28 13:25:37 PDT 2026 

  Branch: refs/heads/users/guochen2/amdgpu/true16-fix-isel-sdag
  Home:   https://github.com/llvm/llvm-project
  Commit: 46dc3dff31d0a4a11ebe9ae45e37278c5e145b60
      https://github.com/llvm/llvm-project/commit/46dc3dff31d0a4a11ebe9ae45e37278c5e145b60
  Author: guochen2 <guochen2 at amd.com>
  Date:   2026-09-25 (Fri, 25 Sep 2026)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
    M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h
    M llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
    M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
    M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
    M llvm/lib/Target/AMDGPU/VOP1Instructions.td
    M llvm/test/CodeGen/AMDGPU/GlobalISel/bswap.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.16bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.32bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.48bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.576bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.640bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.64bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.704bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.768bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll
    M llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
    M llvm/test/CodeGen/AMDGPU/atomicrmw_usub_sat.ll
    M llvm/test/CodeGen/AMDGPU/bf16-conversions.ll
    M llvm/test/CodeGen/AMDGPU/bf16-math.ll
    M llvm/test/CodeGen/AMDGPU/bf16.ll
    M llvm/test/CodeGen/AMDGPU/bfe-i8-i16.ll
    M llvm/test/CodeGen/AMDGPU/br_cc.f16.ll
    M llvm/test/CodeGen/AMDGPU/bswap.ll
    M llvm/test/CodeGen/AMDGPU/call-args-inreg-bfloat.ll
    M llvm/test/CodeGen/AMDGPU/call-args-inreg.ll
    M llvm/test/CodeGen/AMDGPU/call-argument-types.ll
    M llvm/test/CodeGen/AMDGPU/calling-conventions.ll
    M llvm/test/CodeGen/AMDGPU/extract_vector_elt-f16.ll
    M llvm/test/CodeGen/AMDGPU/fabs.bf16.ll
    M llvm/test/CodeGen/AMDGPU/fabs.f16.ll
    M llvm/test/CodeGen/AMDGPU/fcmp.f16.ll
    M llvm/test/CodeGen/AMDGPU/fcopysign.bf16.ll
    M llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll
    M llvm/test/CodeGen/AMDGPU/fcopysign.f32.ll
    M llvm/test/CodeGen/AMDGPU/fcopysign.f64.ll
    M llvm/test/CodeGen/AMDGPU/fcopysign.gfx11plus.ll
    M llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-f16-gfx12-true16.mir
    M llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-f16-true16.mir
    M llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-f16.mir
    M llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-sgpr32-to-vgpr16.ll
    M llvm/test/CodeGen/AMDGPU/flat_atomics.ll
    M llvm/test/CodeGen/AMDGPU/float-sopc-vopc.ll
    M llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp-fp8-f16-hw.ll
    M llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp-widen.ll
    M llvm/test/CodeGen/AMDGPU/fma-mix.gfx11plus.ll
    M llvm/test/CodeGen/AMDGPU/fma.f16.gfx11plus.ll
    M llvm/test/CodeGen/AMDGPU/fmax3-maximumnum.ll
    M llvm/test/CodeGen/AMDGPU/fmaximum.ll
    M llvm/test/CodeGen/AMDGPU/fmaximum3.ll
    M llvm/test/CodeGen/AMDGPU/fmaxnum.ll
    M llvm/test/CodeGen/AMDGPU/fmed3.bf16.ll
    M llvm/test/CodeGen/AMDGPU/fmin3-minimumnum.ll
    M llvm/test/CodeGen/AMDGPU/fminimum.ll
    M llvm/test/CodeGen/AMDGPU/fminimum3.ll
    M llvm/test/CodeGen/AMDGPU/fminnum.ll
    M llvm/test/CodeGen/AMDGPU/fmul-2-combine-multi-use.ll
    M llvm/test/CodeGen/AMDGPU/fneg-fabs.bf16.ll
    M llvm/test/CodeGen/AMDGPU/fneg-fabs.f16.ll
    M llvm/test/CodeGen/AMDGPU/fneg.bf16.ll
    M llvm/test/CodeGen/AMDGPU/fneg.f16.ll
    M llvm/test/CodeGen/AMDGPU/fpext.f16.ll
    M llvm/test/CodeGen/AMDGPU/fptosi-sat-scalar.ll
    M llvm/test/CodeGen/AMDGPU/fptosi-sat-vector.ll
    M llvm/test/CodeGen/AMDGPU/fptoui-sat-scalar.ll
    M llvm/test/CodeGen/AMDGPU/fptoui-sat-vector.ll
    M llvm/test/CodeGen/AMDGPU/frem.ll
    M llvm/test/CodeGen/AMDGPU/function-args-inreg.ll
    M llvm/test/CodeGen/AMDGPU/function-returns.ll
    M llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll
    M llvm/test/CodeGen/AMDGPU/global_atomics.ll
    M llvm/test/CodeGen/AMDGPU/half.ll
    M llvm/test/CodeGen/AMDGPU/idiv-licm.ll
    M llvm/test/CodeGen/AMDGPU/insert-delay-alu-bug.ll
    M llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2bf16.ll
    M llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll
    M llvm/test/CodeGen/AMDGPU/integer-canonicalizing-src-modifiers.ll
    M llvm/test/CodeGen/AMDGPU/isel-amdgpu-cs-chain-cc.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.alignbyte.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.bitop3.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.bf16.bf16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.make.buffer.rsrc.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.tbuffer.load.d16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.tbuffer.store.d16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.load.d16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.store.d16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fadd.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmax.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmin.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fsub.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.tbuffer.load.d16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.tbuffer.store.d16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.load.d16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.store.d16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.exp2.bf16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.fptrunc.round.ll
    M llvm/test/CodeGen/AMDGPU/llvm.maximum.f16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.minimum.f16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.rint.f16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.round.ll
    M llvm/test/CodeGen/AMDGPU/llvm.sqrt.f16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.trunc.f16.ll
    M llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
    M llvm/test/CodeGen/AMDGPU/load-constant-i16.ll
    M llvm/test/CodeGen/AMDGPU/load-constant-i8.ll
    M llvm/test/CodeGen/AMDGPU/mad.u16.ll
    M llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll
    M llvm/test/CodeGen/AMDGPU/minimummaximum.ll
    M llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll
    M llvm/test/CodeGen/AMDGPU/minmax.ll
    M llvm/test/CodeGen/AMDGPU/move-to-valu-pseudo-scalar-trans-f16-true16.ll
    M llvm/test/CodeGen/AMDGPU/promote-alloca-vector-dynamic-idx-bitcasts-llc.ll
    M llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.ll
    M llvm/test/CodeGen/AMDGPU/scalar-float-sop1.ll
    M llvm/test/CodeGen/AMDGPU/scalar-float-sop2.ll
    M llvm/test/CodeGen/AMDGPU/scalar_to_vector.gfx11plus.ll
    M llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll
    M llvm/test/CodeGen/AMDGPU/select.f16.ll
    M llvm/test/CodeGen/AMDGPU/strict_fadd.f16.ll
    M llvm/test/CodeGen/AMDGPU/strict_fmul.f16.ll
    M llvm/test/CodeGen/AMDGPU/strict_fsub.f16.ll
    M llvm/test/CodeGen/AMDGPU/ucmp.ll
    M llvm/test/CodeGen/AMDGPU/umin-sub-to-usubo-select-combine.ll
    M llvm/test/CodeGen/AMDGPU/usubsat.ll

  Log Message:
  -----------
  Legalize sgpr16 in sdag


  Commit: b65dbd14ba63e3561253337d2cee4f454977a450
      https://github.com/llvm/llvm-project/commit/b65dbd14ba63e3561253337d2cee4f454977a450
  Author: guochen2 <guochen2 at amd.com>
  Date:   2026-09-25 (Fri, 25 Sep 2026)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
    M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h
    M llvm/lib/Target/AMDGPU/VOP1Instructions.td
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.16bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.48bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.64bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll
    M llvm/test/CodeGen/AMDGPU/bf16-math.ll
    M llvm/test/CodeGen/AMDGPU/bfe-i8-i16.ll
    M llvm/test/CodeGen/AMDGPU/call-args-inreg-bfloat.ll
    M llvm/test/CodeGen/AMDGPU/calling-conventions.ll
    M llvm/test/CodeGen/AMDGPU/extract-hi16-true16.ll
    M llvm/test/CodeGen/AMDGPU/fabs.bf16.ll
    M llvm/test/CodeGen/AMDGPU/fcopysign.bf16.ll
    M llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll
    M llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp-widen.ll
    M llvm/test/CodeGen/AMDGPU/fmac.sdwa.ll
    M llvm/test/CodeGen/AMDGPU/fmax3-maximumnum.ll
    M llvm/test/CodeGen/AMDGPU/fmaxnum.ll
    M llvm/test/CodeGen/AMDGPU/fmed3.bf16.ll
    M llvm/test/CodeGen/AMDGPU/fmin3-minimumnum.ll
    M llvm/test/CodeGen/AMDGPU/fminnum.ll
    M llvm/test/CodeGen/AMDGPU/fptosi-sat-vector.ll
    M llvm/test/CodeGen/AMDGPU/fptoui-sat-vector.ll
    M llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll
    M llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2bf16.ll
    M llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll
    M llvm/test/CodeGen/AMDGPU/integer-canonicalizing-src-modifiers.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.intersect_ray.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.make.buffer.rsrc.ll
    M llvm/test/CodeGen/AMDGPU/llvm.exp2.bf16.ll
    M llvm/test/CodeGen/AMDGPU/mad.u16.ll
    M llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll
    M llvm/test/CodeGen/AMDGPU/maximumnum.ll
    M llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll
    M llvm/test/CodeGen/AMDGPU/minimumnum.ll
    M llvm/test/CodeGen/AMDGPU/scalar-float-sop1.ll
    M llvm/test/CodeGen/AMDGPU/scalar_to_vector.gfx11plus.ll
    M llvm/test/CodeGen/AMDGPU/schedule-amdgpu-trackers.ll
    M llvm/test/CodeGen/AMDGPU/ucmp.ll
    M llvm/test/CodeGen/AMDGPU/umin-sub-to-usubo-select-combine.ll
    M llvm/test/CodeGen/AMDGPU/usubsat.ll

  Log Message:
  -----------
  address comment, add sgpr32 reg_seq optimization and hi16 fix


  Commit: 007bf426765277eeef3d8f0e17dfc1f115d70a54
      https://github.com/llvm/llvm-project/commit/007bf426765277eeef3d8f0e17dfc1f115d70a54
  Author: guochen2 <guochen2 at amd.com>
  Date:   2026-09-25 (Fri, 25 Sep 2026)

  Changed paths:
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.48bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.64bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll
    M llvm/test/CodeGen/AMDGPU/fabs.bf16.ll
    M llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll
    M llvm/test/CodeGen/AMDGPU/idiv-licm.ll

  Log Message:
  -----------
  rebase and update test


  Commit: a3738feae6bfa8c0e08616d292e30f4b2eff0ae1
      https://github.com/llvm/llvm-project/commit/a3738feae6bfa8c0e08616d292e30f4b2eff0ae1
  Author: guochen2 <guochen2 at amd.com>
  Date:   2026-09-25 (Fri, 25 Sep 2026)

  Changed paths:
    M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
    M llvm/test/CodeGen/AMDGPU/bf16.ll
    M llvm/test/CodeGen/AMDGPU/extract-hi16-true16.ll
    M llvm/test/CodeGen/AMDGPU/fmaximum3.ll
    M llvm/test/CodeGen/AMDGPU/fminimum3.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.alignbyte.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.bitop3.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.bf16.bf16.ll
    M llvm/test/CodeGen/AMDGPU/minmax.ll
    M llvm/test/CodeGen/AMDGPU/select.f16.ll

  Log Message:
  -----------
  split legalizeOpWithMove


  Commit: 3c5f2acac4224da4caf1d6432a48b5194e2f838f
      https://github.com/llvm/llvm-project/commit/3c5f2acac4224da4caf1d6432a48b5194e2f838f
  Author: guochen2 <guochen2 at amd.com>
  Date:   2026-09-28 (Mon, 28 Sep 2026)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.16bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.48bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.64bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll
    M llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
    M llvm/test/CodeGen/AMDGPU/bf16-conversions.ll
    M llvm/test/CodeGen/AMDGPU/bfe-i8-i16.ll
    M llvm/test/CodeGen/AMDGPU/bswap.ll
    M llvm/test/CodeGen/AMDGPU/call-args-inreg-bfloat.ll
    M llvm/test/CodeGen/AMDGPU/call-args-inreg.ll
    M llvm/test/CodeGen/AMDGPU/calling-conventions.ll
    M llvm/test/CodeGen/AMDGPU/fcopysign.bf16.ll
    M llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll
    M llvm/test/CodeGen/AMDGPU/fptosi-sat-vector.ll
    M llvm/test/CodeGen/AMDGPU/fptoui-sat-vector.ll
    M llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll
    M llvm/test/CodeGen/AMDGPU/immv216.ll
    M llvm/test/CodeGen/AMDGPU/insert-delay-alu-bug.ll
    M llvm/test/CodeGen/AMDGPU/integer-canonicalizing-src-modifiers.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.intersect_ray.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.make.buffer.rsrc.ll
    M llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
    M llvm/test/CodeGen/AMDGPU/mad.u16.ll
    M llvm/test/CodeGen/AMDGPU/scalar-float-sop1.ll
    M llvm/test/CodeGen/AMDGPU/scalar_to_vector_v2bf16.ll
    M llvm/test/CodeGen/AMDGPU/ucmp.ll
    M llvm/test/CodeGen/AMDGPU/umin-sub-to-usubo-select-combine.ll
    M llvm/test/CodeGen/AMDGPU/usubsat.ll

  Log Message:
  -----------
  improve optimization, added missing testlines, and address comment


Compare: https://github.com/llvm/llvm-project/compare/316807054717...3c5f2acac422

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