[all-commits] [llvm/llvm-project] f9d25d: [lldb][FreeBSD] Adopt file_t for closeFile() (#226...
Chinmay Deshpande via All-commits
all-commits at lists.llvm.org
Sun Sep 27 11:12:54 PDT 2026
Branch: refs/heads/users/chinmaydd/lld-elf-vfs
Home: https://github.com/llvm/llvm-project
Commit: f9d25d67d4f7a5b9c37047306a700b234fd6c2c8
https://github.com/llvm/llvm-project/commit/f9d25d67d4f7a5b9c37047306a700b234fd6c2c8
Author: Minsoo Choo <minsoo at minsoo.io>
Date: 2026-09-24 (Thu, 24 Sep 2026)
Changed paths:
M lldb/source/Plugins/Process/FreeBSD/NativeProcessFreeBSD.cpp
Log Message:
-----------
[lldb][FreeBSD] Adopt file_t for closeFile() (#226290)
Fixes: ae82b85123a2271df24ceb28c09a2a0c467c16d5
Commit: 4010c1ac00e25464ecc7e20950cba84edd0e3880
https://github.com/llvm/llvm-project/commit/4010c1ac00e25464ecc7e20950cba84edd0e3880
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2026-09-24 (Thu, 24 Sep 2026)
Changed paths:
M mlir/include/mlir/IR/OpImplementation.h
M mlir/lib/IR/AsmPrinter.cpp
M mlir/test/mlir-tblgen/op-decl-and-defs.td
M mlir/test/mlir-tblgen/op-format.td
M mlir/tools/mlir-tblgen/OpDefinitionsGen.cpp
M mlir/tools/mlir-tblgen/OpFormatGen.cpp
Log Message:
-----------
[MLIR] Reduce generated assembly printer compile time (NFC) (#225740)
Use fixed arrays for statically elided attributes and combine leading
spaces with literals. Move common operand printing out of generated call
sites and emit sliced operand getters to reduce optimizer work in large
printers.
For omp.target, optimized print IR drops from 3,893 to 2,667
instructions.
Assisted-by: Codex
Commit: a858e5ebb33c3988ac593cefe4593040029169b4
https://github.com/llvm/llvm-project/commit/a858e5ebb33c3988ac593cefe4593040029169b4
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-09-24 (Thu, 24 Sep 2026)
Changed paths:
M llvm/test/Transforms/LoopVectorize/induction-wrapflags.ll
Log Message:
-----------
[LV] Add tests showing incorrect flags for sub inductions (NFC). (#226301)
Add tests showing incorrect NUW/NSW flags preserved on wide induction
where the induction step uses sub.
Tests for https://github.com/llvm/llvm-project/issues/224024.
Commit: 5e7f66672867f3ccf23baa6156d16ec4541de29b
https://github.com/llvm/llvm-project/commit/5e7f66672867f3ccf23baa6156d16ec4541de29b
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2026-09-24 (Thu, 24 Sep 2026)
Changed paths:
M mlir/include/mlir/IR/OperationSupport.h
M mlir/lib/IR/OperationSupport.cpp
M mlir/test/mlir-tblgen/op-decl-and-defs.td
M mlir/tools/mlir-tblgen/OpDefinitionsGen.cpp
Log Message:
-----------
[mlir][ODS] Share generated legacy property splitting (NFC) (#226085)
Route generated legacy builder attributes through an out-of-line helper
that partitions inherent and discardable attributes before converting
properties. This avoids compiling the same loop and error path for every
operation.
Assisted-by: Codex
Commit: 45ea3b957284d8940b109b6b6706f451e9719ef9
https://github.com/llvm/llvm-project/commit/45ea3b957284d8940b109b6b6706f451e9719ef9
Author: Joshua Batista <jbatista at microsoft.com>
Date: 2026-09-24 (Thu, 24 Sep 2026)
Changed paths:
M clang/include/clang/Basic/Builtins.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/lib/CodeGen/CGHLSLBuiltins.cpp
M clang/lib/Sema/HLSLBuiltinTypeDeclBuilder.cpp
M clang/lib/Sema/HLSLExternalSemaSource.cpp
M clang/lib/Sema/SemaHLSL.cpp
M clang/test/CodeGenHLSL/builtins/InterlockedExchange.hlsl
M clang/test/CodeGenHLSL/builtins/RWByteAddressBuffer-InterlockedExchange.hlsl
M clang/test/CodeGenHLSL/builtins/RWTexture-Interlocked.hlsl
A clang/test/SemaHLSL/BuiltIns/ByteAddressBuffer-InterlockedExchangeFloat-sm60.hlsl
M clang/test/SemaHLSL/BuiltIns/InterlockedExchange-errors.hlsl
M llvm/lib/Target/DirectX/DXILLegalizePass.cpp
M llvm/lib/Target/DirectX/DXILResourceAccess.cpp
A llvm/test/CodeGen/DirectX/LegalizeAtomicExchangeFloat-unsupported-width.ll
A llvm/test/CodeGen/DirectX/LegalizeAtomicExchangeFloat.ll
M llvm/test/CodeGen/DirectX/ResourceAtomicBinOp-texture-nonscalar.ll
A llvm/test/CodeGen/DirectX/ResourceAtomicExchangeFloat.ll
Log Message:
-----------
[HLSL] Add float overload for `InterlockedExchange` (#222163)
This PR adds the float overload of `InterlockedExchange`, and the
`InterlockedExchangeFloat` method on `RWByteAddressBuffer` and
`RasterizerOrderedByteAddressBuffer`.
The HLSL interlocked builtins are declared with a variadic type in
`Builtins.td`, so Clang applies the default argument promotions to their
arguments. That promotion turns a `float` argument into a `double`
before Sema
sees it. The Sema check then rejects the call and names the type as
`'double'`
in the diagnostic, which does not match what the user wrote.
`CustomTypeChecking` suppresses that promotion, so the argument keeps
its
`float` type and the diagnostic names it correctly.
Only the builtins that can see a float argument need the attribute. This
PR
sets it on `__builtin_hlsl_interlocked_exchange` alone. The later float
builtins in this stack set it as they are added. The integer-only
builtins do
not set it, because they never see a float and the promotion cannot
affect
them.
Fixes: https://github.com/llvm/llvm-project/issues/99129
Assisted by: Github Copilot
Commit: 3a4d4104528d44e1bae74464f8a104d7ee86a7ac
https://github.com/llvm/llvm-project/commit/3a4d4104528d44e1bae74464f8a104d7ee86a7ac
Author: Ivan R. Ivanov <iivanov at nvidia.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M offload/include/OpenMP/OMPT/Callback.h
M offload/include/OpenMP/OMPT/Interface.h
M offload/include/device.h
M offload/liboffload/src/OffloadImpl.cpp
M offload/libompaccsupport/PluginManager.cpp
M offload/libompaccsupport/device.cpp
M offload/libomptarget/OffloadRTL.cpp
M offload/libomptarget/OpenMP/OMPT/Callback.cpp
M offload/plugins-nextgen/amdgpu/src/rtl.cpp
M offload/plugins-nextgen/common/include/PluginInterface.h
M offload/plugins-nextgen/common/src/PluginInterface.cpp
M offload/plugins-nextgen/cuda/src/rtl.cpp
M offload/plugins-nextgen/host/src/rtl.cpp
Log Message:
-----------
[offload] Extract OMPT out of PluginInterface (#221726)
Some of the OMPT callbacks, namely the device lifetime and image related
ones, lived in the generic PluginInterface even though they are OpenMP
specific. This patch extracts them out to the PluginManager, and removes
some device ID tracking functionality which was only necessary for
OpenMP from PluginInterface. The OpenMP device ID mapping should live
only in libomptarget.
Commit: 16cbe80f1d294451026cc79d25754e98172d4d1f
https://github.com/llvm/llvm-project/commit/16cbe80f1d294451026cc79d25754e98172d4d1f
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUGlobalISelDivergenceLowering.cpp
M llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-phis-no-lane-mask-merging.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-phis-no-lane-mask-merging.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-used-outside-loop.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-used-outside-loop.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-structurizer.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-structurizer.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-i1.mir
M llvm/test/CodeGen/AMDGPU/i1-divergent-phi-fix-sgpr-copies-assert.mir
M llvm/test/CodeGen/AMDGPU/lower-i1-copies-clear-kills.mir
M llvm/test/CodeGen/AMDGPU/lower-i1-copies-implicit-def-unstructured-loop.mir
M llvm/test/CodeGen/AMDGPU/mmra.ll
M llvm/test/CodeGen/AMDGPU/si-annotate-nested-control-flows.ll
M llvm/test/CodeGen/AMDGPU/si-lower-i1-copies-order-of-phi-incomings.mir
M llvm/test/CodeGen/AMDGPU/si-lower-i1-copies.mir
Log Message:
-----------
AMDGPU: Mark the SCC def dead when merging lane masks (#226282)
The scalar and/or/xor used to merge a lane mask with EXEC clobber SCC,
but nothing reads the result. Avoid depending on later dead flag inference.
Co-authored-by: Claude Opus 5 <noreply at anthropic.com>
Commit: 25ba11d9dd3053d82af538e8b2cd7d449dcc867c
https://github.com/llvm/llvm-project/commit/25ba11d9dd3053d82af538e8b2cd7d449dcc867c
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2026-09-24 (Thu, 24 Sep 2026)
Changed paths:
M mlir/include/mlir/IR/OpDefinition.h
Log Message:
-----------
[mlir] Constant-initialize registered operation hook tables (NFC) (#226320)
Make the generic operation hook accessors constexpr so registered
operation hook tables can be constant-initialized. Keep the table
declared static const to support non-constexpr downstream overrides.
In OpenMPDialect.cpp this removes 72 initialization guards and 10,368
bytes of object text, and saves about 0.56B compiler instructions.
Assisted-by: Codex
Commit: ec32f94a2d5f871624fce2e0c51c4902ee02ec15
https://github.com/llvm/llvm-project/commit/ec32f94a2d5f871624fce2e0c51c4902ee02ec15
Author: Lang Hames <lhames at gmail.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/tools/llvm-jitlink/llvm-jitlink.cpp
Log Message:
-----------
[llvm-jitlink] Add -show-jit-result option (#226149)
Add a -show-jit-result option that prints the int result of the JIT'd
main / entry function to stdout as:
JIT result: <return value>
This makes the result of the JIT'd main / entry function FileCheck-able,
and distinguishable from an llvm-jitlink failure.
This will be used in upcoming ORC runtime tests.
Since we don't currently run code under llvm-jitlink in LLVM regression
tests, this commit does not include an LLVM-side test.
Commit: 0d049f14804d436b12d81846de00c45516541f0b
https://github.com/llvm/llvm-project/commit/0d049f14804d436b12d81846de00c45516541f0b
Author: Syadus Sefat <42645939+mssefat at users.noreply.github.com>
Date: 2026-09-24 (Thu, 24 Sep 2026)
Changed paths:
M llvm/include/llvm/CodeGen/MachineRegisterInfo.h
M llvm/include/llvm/CodeGen/TargetRegisterInfo.h
M llvm/lib/CodeGen/AllocationOrder.cpp
M llvm/lib/CodeGen/AllocationOrder.h
M llvm/lib/CodeGen/MachineRegisterInfo.cpp
M llvm/lib/CodeGen/RegAllocGreedy.cpp
M llvm/lib/CodeGen/TargetRegisterInfo.cpp
M llvm/unittests/CodeGen/AllocationOrderTest.cpp
Log Message:
-----------
[RegAlloc] Add register allocation anti-hints infrastructure (#218071)
This PR adds a RA anti-hint mechanism. MachineRegisterInfo is extended
to track anti-hints
between vregs to try avoiding to be allocated on the same physical
register. AllocationOrder can
queries these and also allows the target reorder the allocation order
through the new
TargetRegisterInfo::applyRegAllocationAntiHints hook. The default
implementation moves
the anti-hinted registers to the end of the order, so they are only used
as a last option.
## Stack
PR **1/4**. Next: MIR serialization #218073.
Commit: 25485b3c4964ab704e7d4961b67ab2501fedbdbe
https://github.com/llvm/llvm-project/commit/25485b3c4964ab704e7d4961b67ab2501fedbdbe
Author: Ryan Buchner <rbuchner at qti.qualcomm.com>
Date: 2026-09-24 (Thu, 24 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPTypeUtils.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPTypeUtils.h
M llvm/test/Transforms/SLPVectorizer/RISCV/wide-load-reduction.ll
Log Message:
-----------
[SLP] Use getRegUsageForType() rather than getNumberOfParts() when determining reduction width (#226277)
`getRegUsageForType()` is more appropriate for comparison to total
number of registers. `getNumberOfParts()` is legalization cost based,
but in this situation, we are looking to make sure we don't create
vectors that are widen than the register file can handle.
Commit: 9d90850fe6b01d877a7d7559a097fd4e785b4f5a
https://github.com/llvm/llvm-project/commit/9d90850fe6b01d877a7d7559a097fd4e785b4f5a
Author: Zachary Yedidia <zyedidia at gmail.com>
Date: 2026-09-24 (Thu, 24 Sep 2026)
Changed paths:
M llvm/docs/LFI.md
M llvm/lib/Target/X86/CMakeLists.txt
M llvm/lib/Target/X86/MCTargetDesc/X86MCLFIRewriter.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86MCLFIRewriter.h
M llvm/lib/Target/X86/X86.h
M llvm/lib/Target/X86/X86CodeGenPassBuilder.cpp
A llvm/lib/Target/X86/X86LFIRewritePass.cpp
M llvm/lib/Target/X86/X86PassRegistry.def
M llvm/lib/Target/X86/X86TargetMachine.cpp
A llvm/test/CodeGen/X86/lfi-align.ll
A llvm/test/MC/X86/LFI/control-flow-errors.s
A llvm/test/MC/X86/LFI/control-flow.s
Log Message:
-----------
[LFI][X86] Add control-flow rewrites (#210913)
This adds LFI rewrites for control-flow operations. All jumps and
calls are rewritten so that their target is both guaranteed to be within
the sandbox, and at an address that is a multiple of the bundle size.
When combined with bundling, this restricts control-flow to the sandbox
region.
With Intel MPK support, this can provide a complete sandbox. A future
patch will also introduce software-based memory sandboxing so that MPK
is not required for memory isolation.
Commit: 2428c10786f12f8e4e7bffa63b0393c137b031bb
https://github.com/llvm/llvm-project/commit/2428c10786f12f8e4e7bffa63b0393c137b031bb
Author: Greg Clayton <gclayton at fb.com>
Date: 2026-09-24 (Thu, 24 Sep 2026)
Changed paths:
M llvm/include/llvm/DebugInfo/GSYM/GsymCreator.h
M llvm/lib/DebugInfo/GSYM/GsymCreator.cpp
A llvm/test/tools/llvm-gsymutil/X86/macho-last-symbol-section-end.yaml
M llvm/tools/llvm-gsymutil/llvm-gsymutil.cpp
Log Message:
-----------
Improve llvm-gsymutil to set the end address correctly. (#225593)
When converting DWARF in llvm-gsymutil, if the last function info had no
size, it would set it to the end of the valid text ranges. This meant a
symbol could get a larger than necessary size in mach-o files. This
patch will set the address to the minimum of the last TextRanges or the
end of the section that contains the symbol.
Commit: 56e0b9a7d7acb82a2cc4499808277c388b1e4332
https://github.com/llvm/llvm-project/commit/56e0b9a7d7acb82a2cc4499808277c388b1e4332
Author: Walter Lee <49250218+googlewalt at users.noreply.github.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M mlir/lib/Dialect/Tosa/Transforms/TosaProfileCompliance.cpp
Log Message:
-----------
[mlir][tosa] Use optnone for compliance initialization under HWAsan (#226310)
Similar to #223586, compiling the file is very slow when we enable
HWAsan internally. Mark the constructor with optnone under
LLVM_HWADDRESS_SANITIZER_BUILD to skip expensive optimization and
register allocation passes, bringing compilation time from 10+m to ~30s.
Commit: 73aa0db9662ca7e38337761076a622e8095011af
https://github.com/llvm/llvm-project/commit/73aa0db9662ca7e38337761076a622e8095011af
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-09-24 (Thu, 24 Sep 2026)
Changed paths:
A llvm/test/tools/llvm-readobj/ELF/RISCV/eflags-abi.test
M llvm/tools/llvm-readobj/ELFDumper.cpp
Log Message:
-----------
[RISCV][llvm-readobj] Treat RISC-V float ABI e_flags field as an enum (#226313)
EF_RISCV_FLOAT_ABI is a 2-bit field, not independent flag bits, so
printFlags needs to be told about the mask. Previously a quad-float ABI
object printed "single-float ABI, double-float ABI, quad-float ABI"
instead of just "quad-float ABI".
Co-Authored-By: Claude Sonnet 5 <noreply at anthropic.com>
Commit: eaddb12b0463d9baa048da856c21f50fa9bfc1cf
https://github.com/llvm/llvm-project/commit/eaddb12b0463d9baa048da856c21f50fa9bfc1cf
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-09-24 (Thu, 24 Sep 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
Log Message:
-----------
[RISCV] Make the getJumpTableIndex search more structured. NFC (#226266)
Instead of recursively searching through instructions with certain
opcodes, look for the specific patterns we use for jump tables.
I've added a few TODOs for Zilx and SHXADD_UW.
Commit: 2c6ac60714745ffc338e1b9664d10ec46212185b
https://github.com/llvm/llvm-project/commit/2c6ac60714745ffc338e1b9664d10ec46212185b
Author: Ziliang Zhang <zzl.coding at gmail.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M mlir/lib/Dialect/Bufferization/Transforms/OneShotAnalysis.cpp
M mlir/test/Dialect/Tensor/one-shot-bufferize.mlir
M mlir/test/Dialect/Vector/one-shot-bufferize.mlir
Log Message:
-----------
[mlir][bufferization] Handle disjoint subsets in One-Shot Analysis (#224184)
Teach One-Shot Analysis to ignore RaW conflicts between provably
disjoint subset reads and writes. Trace aliasing reads back to subset
extraction ops to handle alias-only operations such as
tensor.extract_slice.
Add tensor and vector tests for disjoint, overlapping, and unknown
subsets.
Commit: 10e12674cb9c52611d1f3c3c4c92ce43b586b7fe
https://github.com/llvm/llvm-project/commit/10e12674cb9c52611d1f3c3c4c92ce43b586b7fe
Author: Ziliang Zhang <zzl.coding at gmail.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M mlir/lib/Dialect/Linalg/Transforms/BufferizableOpInterfaceImpl.cpp
M mlir/test/Dialect/Linalg/one-shot-bufferize-analysis.mlir
M mlir/test/Dialect/Linalg/one-shot-bufferize.mlir
Log Message:
-----------
[mlir][bufferization] Support matching permutation maps in Linalg analysis (#226079)
Generalize `LinalgOpInterface::bufferizesToElementwiseAccess` to
recognize participating tensor operands with identical permutation
indexing maps, instead of requiring identity maps.
This enables in-place bufferization after loop interchange. Projected
and mismatching maps, reduction iterators, and sparse operands remain
conservatively rejected.
The tests cover the analysis decision as well as end-to-end
bufferization without an allocation or copy.
Commit: dd3534fd5af15575d0d8dea116740b2abb8f3328
https://github.com/llvm/llvm-project/commit/dd3534fd5af15575d0d8dea116740b2abb8f3328
Author: Cyndy Ishida <cyndy_ishida at apple.com>
Date: 2026-09-24 (Thu, 24 Sep 2026)
Changed paths:
M clang/lib/DependencyScanning/DependencyScanningWorker.cpp
R clang/test/ClangScanDeps/build-session-validation-relocated-modules.c
M clang/test/ClangScanDeps/modules-relocated-mm-macro.c
Log Message:
-----------
[clang][DepScan] Disable relocation checks (#225563)
This internally broke an incremental build. Disable while it gets
investigated.
This is partial revert of cf8597bd3b87
resolves: rdar://188026923
Commit: 051daff864822f9edcb05acb8ccb30852753dfc5
https://github.com/llvm/llvm-project/commit/051daff864822f9edcb05acb8ccb30852753dfc5
Author: geoffreygaren <ggaren at apple.com>
Date: 2026-09-24 (Thu, 24 Sep 2026)
Changed paths:
M clang/docs/analyzer/checkers.md
M clang/include/clang/StaticAnalyzer/Checkers/Checkers.td
M clang/lib/StaticAnalyzer/Checkers/WebKit/RawPtrRefLambdaCapturesChecker.cpp
M clang/lib/StaticAnalyzer/Checkers/WebKit/RawPtrRefSafetyModel.cpp
M clang/test/Analysis/Checkers/WebKit/mock-canborrow.h
A clang/test/Analysis/Checkers/WebKit/unborrowed-lambda-captures.cpp
Log Message:
-----------
[WebKit Checkers] Add alpha.webkit.UnborrowedLambdaCapturesChecker (#226288)
Like alpha.webkit.UnborrowedLocalVarsChecker, but for lambda captures.
This checker is pretty restrictive because, unlike a refcounted object,
a lifetime-dependent pointer/reference/view cannot be captured in an
escaping closure at all. Still, we permit capturing in a NOESCAPE
closure.
Commit: 6e687f8dea8825c52fc6f31459dabb0ee0c1d4bd
https://github.com/llvm/llvm-project/commit/6e687f8dea8825c52fc6f31459dabb0ee0c1d4bd
Author: Syadus Sefat <42645939+mssefat at users.noreply.github.com>
Date: 2026-09-24 (Thu, 24 Sep 2026)
Changed paths:
M llvm/include/llvm/CodeGen/MIRParser/MIParser.h
M llvm/include/llvm/CodeGen/MIRYamlMapping.h
M llvm/lib/CodeGen/MIRParser/MIRParser.cpp
M llvm/lib/CodeGen/MIRPrinter.cpp
A llvm/test/CodeGen/MIR/AMDGPU/register-allocation-antihints-mir-print-parse.mir
Log Message:
-----------
[MIR][AMDGPU] Serialize register allocation anti-hints (#218073)
This PR adds MIR print and parse support for the register allocation
anti-hints through
a per vreg anti-hints: [ .. ] field in the registers: section. The
printer only emits
the anti-hint registers only when the it is non-empty to keep existing
tests unchanged.
## Stack
PR **2/4**. Depends on #218071. Next: Apply Occupancy-Aware allocation
anti-hints #218074.
Commit: 7ee53ccefc851c05f3183b1d2cc5bf811cdb62df
https://github.com/llvm/llvm-project/commit/7ee53ccefc851c05f3183b1d2cc5bf811cdb62df
Author: Helena Kotas <hekotas at microsoft.com>
Date: 2026-09-24 (Thu, 24 Sep 2026)
Changed paths:
A clang/docs/HLSL/DynamicResources.md
M clang/docs/HLSL/HLSLDocs.md
M clang/include/clang/Basic/Builtins.td
M clang/include/clang/Sema/HLSLExternalSemaSource.h
M clang/lib/CodeGen/CGHLSLBuiltins.cpp
M clang/lib/CodeGen/CGHLSLRuntime.h
M clang/lib/Headers/CMakeLists.txt
M clang/lib/Headers/hlsl.h
M clang/lib/Headers/hlsl/hlsl_detail.h
A clang/lib/Headers/hlsl/hlsl_resources.h
M clang/lib/Sema/HLSLBuiltinTypeDeclBuilder.cpp
M clang/lib/Sema/HLSLBuiltinTypeDeclBuilder.h
M clang/lib/Sema/HLSLExternalSemaSource.cpp
M clang/lib/Sema/SemaHLSL.cpp
M clang/test/AST/HLSL/ByteAddressBuffers-AST.hlsl
A clang/test/AST/HLSL/DynamicResources-AST.hlsl
M clang/test/AST/HLSL/StructuredBuffers-AST.hlsl
M clang/test/AST/HLSL/TypedBuffers-AST.hlsl
M clang/test/AST/HLSL/matrix-alias.hlsl
A clang/test/CodeGenHLSL/resources/dynamic-resources.hlsl
M clang/test/SemaHLSL/Language/InitLists.hlsl
M clang/test/SemaHLSL/Resources/Textures-SampleCmpLevelZero.hlsl
A clang/test/SemaHLSL/Resources/dynamic-resources-availability.hlsl
A clang/test/SemaHLSL/Resources/dynamic-resources.hlsl
M llvm/utils/gn/secondary/clang/lib/Headers/BUILD.gn
Log Message:
-----------
[HLSL] Add support for dynamic resources (#221103)
Adds support for dynamic resources, also known as bindless or directly
indexed resources. The design is described in
https://github.com/llvm/wg-hlsl/issues/204.
The change adds:
- The `ResourceDescriptorHeap` and `SamplerDescriptorHeap` global
symbols, which expose the Shader Model 6.6 descriptor heaps.
- Internal `hlsl::__detail::heap_resource_info` and
`hlsl::__detail::heap_sampler_info` types, which are produced by
indexing the corresponding descriptor heap. HLSL resource and sampler
types can be implicitly constructed from these values.
- Constructors that accept the corresponding internal heap info type for
all currently implemented resource classes.
- Clang builtins `__builtin_hlsl_resource_handlefromheap` and
`__builtin_hlsl_resource_counterhandlefromheap` for creating resource
and counter handles from descriptor heap indices.
- Sema validation and return-type handling for the new builtins.
For DXIL, the built-in function is lowered to
`llvm.dx.resource.handlefromheap`. For SPIR-V, the built-ins are lowered
to `llvm.spv.resource.handlefromheap` and
`llvm.spv.resource.counterhandlefromheap`.
Fixes #133831
Assisted by GPT 5.6 Sol and Claude Opus 4.8.
Commit: 35f073eb07f641713513fefb1ae4f4a5eb0bc604
https://github.com/llvm/llvm-project/commit/35f073eb07f641713513fefb1ae4f4a5eb0bc604
Author: Harrison Hao <57025411+harrisonGPU at users.noreply.github.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
M llvm/test/Transforms/InstCombine/AMDGPU/llvm.amdgcn.sudot.ll
Log Message:
-----------
[AMDGPU] Fold a constant add/sub into the sudot4/sudot8 accumulator (#225322)
Fold a constant add into the accumulator operand of sudot4 and sudot8
when
clamping is disabled:
```
sudot(a, b, C1, false) + C2 -> sudot(a, b, C1 + C2, false)
```
Subtraction by a constant is canonicalized to addition of its negation.
Commit: 3243453c7b919c155a16e4e70e50d5f8417839d9
https://github.com/llvm/llvm-project/commit/3243453c7b919c155a16e4e70e50d5f8417839d9
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2026-09-24 (Thu, 24 Sep 2026)
Changed paths:
M .github/workflows/libcxx-pr-benchmark.yml
M libcxx/utils/ci/lnt/machines.json
M libcxx/utils/ci/lnt/run-benchmarks
M libcxx/utils/test-at-commit
Log Message:
-----------
[libc++] Take the benchmark testing configuration from the test suite (#226267)
Previously, we'd use the testing configuration (the .cfg.in file) from
the checked out test suite for the PR benchmarking, but we'd use the one
from `main` for the historical benchmarking. Since the config file is
logically part of the test suite (just like the rest of the Lit setup),
it makes more sense to take it from the checked-out test suite version.
Commit: 4880e16f73dfc25762a857b9c08ad2bd5c14c8e0
https://github.com/llvm/llvm-project/commit/4880e16f73dfc25762a857b9c08ad2bd5c14c8e0
Author: Zeyi Xu <zeyi2 at nekoarch.cc>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M clang/docs/ReleaseNotes.md
M llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
R llvm/test/CodeGen/RISCV/sifive-interrupt-attr-err.ll
M llvm/test/CodeGen/RISCV/sifive-interrupt-attr.ll
M llvm/test/CodeGen/RISCV/sifive-interrupt-frame-flags.ll
A llvm/test/CodeGen/RISCV/sifive-interrupt-frame-pointer.ll
Log Message:
-----------
[RISCV] Support frame pointers in SiFive CLIC preemptible handlers (#221318)
This commit adds frame-pointer support for SiFive CLIC preemptible
handlers by using t0 to save mcause and mepc to dedicated stack slots in
both cases.
Commit: 8c237a2c9f979a7b8716ef1073d3a5a0558d1415
https://github.com/llvm/llvm-project/commit/8c237a2c9f979a7b8716ef1073d3a5a0558d1415
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2026-09-24 (Thu, 24 Sep 2026)
Changed paths:
M .github/workflows/libcxx-benchmark-commit.yml
M .github/workflows/libcxx-pr-benchmark.yml
M .github/workflows/libcxx/build-at-commit/action.yml
Log Message:
-----------
[libc++] Run the PR benchmarking tooling from main (#226278)
Previously, we'd use the workflow file and machines.json from the main
branch, but the rest of the tools (e.g. build-at-commit) would be taken
from the PR head. This patch switches to using the tools from main and
only using the PR head's content for the actual code and benchmarks.
This should make it easier to evolve the tools and the workflow files
without breaking PR benchmarking for people who submit PRs from slightly
outdated bases.
Commit: f119c93418ebd6aa3a95b7346fe3f6c86fba57f7
https://github.com/llvm/llvm-project/commit/f119c93418ebd6aa3a95b7346fe3f6c86fba57f7
Author: Med Ismail Bennani <ismail at bennani.ma>
Date: 2026-09-24 (Thu, 24 Sep 2026)
Changed paths:
M lldb/source/Interpreter/CommandInterpreter.cpp
A lldb/test/Shell/ScriptInterpreter/Python/nested_command_selected_target.test
Log Message:
-----------
[lldb] Use the selected target when the override context is the dummy (#226332)
Commit: f91a3b1bcd7bb69634bc40da1f599daab2aea67c
https://github.com/llvm/llvm-project/commit/f91a3b1bcd7bb69634bc40da1f599daab2aea67c
Author: Fangrui Song <i at maskray.me>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M bolt/test/X86/dwarf5-debug-names-skip-forward-decl.s
Log Message:
-----------
[BOLT,test] Add missing pipe in dwarf5-debug-names-skip-forward-decl.s (#226338)
With cl::Grouping, --check-prefix=POSTCHECK parses as -c -h..., so
llvm-dwarfdump prints --help and exits 0, and the checks never run.
Commit: b9123f788eb3e62c5cf18fd7d7b093dd3206b60d
https://github.com/llvm/llvm-project/commit/b9123f788eb3e62c5cf18fd7d7b093dd3206b60d
Author: Fangrui Song <i at maskray.me>
Date: 2026-09-24 (Thu, 24 Sep 2026)
Changed paths:
M llvm/docs/CommandLine.md
M llvm/include/llvm/Support/CommandLine.h
M llvm/lib/Support/CommandLine.cpp
M llvm/unittests/Support/CommandLineTest.cpp
Log Message:
-----------
[Support] Remove cl::Grouping (#224958)
This feature emulates POSIX's grouped short options in a non-perfect
way. https://reviews.llvm.org/D61270 made every single-character
cl::option implicitly group, leading to weird error message for `opt
-foo=bar`: `opt: for the -o option: may not occur within a group!`
Every tool (primarily binutils-style tools) has since migrated to
OptTable,
with llvm-cov gcov the last (#224955).
Delete this feature, which would block TableGen based representation.
LLM-aided
Commit: e9c56af6e91289a9be5604c74309638d685999be
https://github.com/llvm/llvm-project/commit/e9c56af6e91289a9be5604c74309638d685999be
Author: Alex MacLean <amaclean at nvidia.com>
Date: 2026-09-24 (Thu, 24 Sep 2026)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
M llvm/unittests/CodeGen/GlobalISel/LegalizerHelperTest.cpp
Log Message:
-----------
[GlobalISel] Fix segment size when narrowing G_INSERT (#226275)
When an inserted value starts inside a destination piece, bound the
overlap by the size of the inserted value. Including the offset from the
start of the piece can produce an extract wider than its source.
---------
Co-authored-by: Hongyu Chen <hongchen at nvidia.com>
Commit: 178caae5c39dbf9a03f52f9a3d7edc11d3b02405
https://github.com/llvm/llvm-project/commit/178caae5c39dbf9a03f52f9a3d7edc11d3b02405
Author: Syadus Sefat <42645939+mssefat at users.noreply.github.com>
Date: 2026-09-24 (Thu, 24 Sep 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
M llvm/lib/Target/AMDGPU/SIRegisterInfo.h
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.anti-hints.mir
Log Message:
-----------
[AMDGPU] Apply occupancy-aware register allocation anti-hints (#218074)
This PR overrides applyRegAllocationAntiHints in the SIRegisterInfo so
anti-hints
try to protect against occupancy regression. Changing of the allocation
order is
confined to the vgpr budget of the current occupancy. Reordering is
skipped when
the allocation is near the budget (80% of the target-occupancy vgpr
limit or 95%
of the current occupancy vgpr limit). Below this, the anti-hinted
registers are
moved behind the non-anti-hinted ones within the budget.
## Stack
PR **3/4**. Depends on #218073. Next: Add anti-hints in
GCNPreRAOptimizatioins #218075.
Commit: 007551bacb899a409218574908d96b0633d52018
https://github.com/llvm/llvm-project/commit/007551bacb899a409218574908d96b0633d52018
Author: Sudharsan Veeravalli <svs at qti.qualcomm.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfo.h
Log Message:
-----------
[RISCV] Remove getInstSizeVerifyMode override (#226241)
Now that we generate the correct instruction sizes for the compressed
instructions we can remove this function override.
Commit: 3489ea3b567c719f497bfcf83348e27cfd79cdb7
https://github.com/llvm/llvm-project/commit/3489ea3b567c719f497bfcf83348e27cfd79cdb7
Author: Himadhith <hima130602 at gmail.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M libcxx/include/__locale_dir/locale_base_api.h
M libcxx/include/__locale_dir/locale_base_api/bsd_locale_fallbacks.h
M libcxx/include/__locale_dir/num.h
M libcxx/include/__locale_dir/support/aix.h
M libcxx/include/__locale_dir/support/bsd_like.h
M libcxx/include/__locale_dir/support/fuchsia.h
M libcxx/include/__locale_dir/support/linux.h
M libcxx/include/__locale_dir/support/newlib.h
M libcxx/include/__locale_dir/support/no_locale/strtonum.h
M libcxx/include/__locale_dir/support/openbsd.h
M libcxx/include/__locale_dir/support/windows.h
M libcxx/src/support/win32/locale_win32.cpp
Log Message:
-----------
[libcxx][locale] Refactor strtonum functions using __str_to_float_c_locale<FloatT> (#222081)
Replace the 3 separate functions `__strtof`, `__strtod` and `__strtold`
with a single template `__str_to_float_c_locale<FloatT>` across
locale_base_api and all platform support headers. Since
`__str_to_float_c_locale<FloatT>` now does not need `__get_c_locale`
argument we can directly call it instead of `__do_strtod`.
This removes `__setAndRestore` from `aix.h` entirely as `__locale_guard`
is now used directly in the template specialisations to switch locales.
`num.h` is updated to call `__locale::__str_to_float_c_locale<T>`
uniformly across the 3 separate `__do_strtod` specialisation calls.
Additionally,
- linux.h, bsd_like.h, newlib.h delegate to the platform's native
`strtof_l`/`strtod_l`/`strtold_l`.
- openbsd.h, no_locale/strtonum.h call bare `strtof`, `strtod` and
`strtold` (no locale needed).
- windows.h, locale_win32.cpp's MSVCRT path inlines the 3 functions and
the non-MSVCRT path exports explicit specialisations from the library.
- Changes `__locale_guard` to take `__locale_t` by value now by removing
`&`.
- Forward declared the `__get_c_locale()` function as it's being used
well before the include.
---------
Co-authored-by: himadhith <himadhith.v at ibm.com>
Commit: 585df631037b5cf8d822b9d6de5abb74cf79d1f4
https://github.com/llvm/llvm-project/commit/585df631037b5cf8d822b9d6de5abb74cf79d1f4
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2026-09-24 (Thu, 24 Sep 2026)
Changed paths:
M lldb/source/Plugins/ObjectFile/wasm/ObjectFileWasm.cpp
A lldb/test/Shell/ObjectFile/wasm/data-segment-names.yaml
Log Message:
-----------
[lldb] Index Wasm data segment names by their entry's index (#226302)
ParseNames bounds-checked each data segment name entry's index but wrote
the name to the slot of the loop counter. A name subsection with more
entries than segments wrote past the end of the segment vector, and
entries listed out of order named the wrong segment.
rdar://186890690
Commit: 8e7254831f7793abbad795c203d4f1bbc47929b1
https://github.com/llvm/llvm-project/commit/8e7254831f7793abbad795c203d4f1bbc47929b1
Author: Lang Hames <lhames at gmail.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M orc-rt/include/orc-rt/bedrock/SocketConnector.h
M orc-rt/lib/bedrock/sys/posix/SocketConnector.cpp
M orc-rt/test/unit/CMakeLists.txt
A orc-rt/test/unit/bedrock/SocketConnectorTest.cpp
Log Message:
-----------
[orc-rt] Reject non-socket descriptors in socket:adopt (#226354)
The socket connector now checks with getsockopt(SO_TYPE) that the
descriptor named by a socket:adopt spec is a socket before wrapping it
in a SocketHandle. Non-sockets (pipes, files, etc.) are rejected with an
error and left open. Sockets are claimed after verification so that they
can be closed on error paths (e.g. if GetAttachInfo fails).
Adds SocketConnectorTest.
Commit: 7a732b1ccfbf9694aad53817ebd47d29335590bc
https://github.com/llvm/llvm-project/commit/7a732b1ccfbf9694aad53817ebd47d29335590bc
Author: Lang Hames <lhames at gmail.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M orc-rt/cmake/OrcRTTesting.cmake
A orc-rt/test/regression/README.md
R orc-rt/test/regression/check-rt-process-info.test
R orc-rt/test/regression/darwin/lit.local.cfg
R orc-rt/test/regression/init.test
A orc-rt/test/regression/jit-free-foundations/check-rt-process-info.test
A orc-rt/test/regression/jit-free-foundations/lit.local.cfg
A orc-rt/test/regression/jit-free-foundations/logging/lit.local.cfg
A orc-rt/test/regression/jit-free-foundations/logging/os_log/delivery.test
A orc-rt/test/regression/jit-free-foundations/logging/os_log/lit.local.cfg
A orc-rt/test/regression/jit-free-foundations/logging/os_log/no-printf-output.test
A orc-rt/test/regression/jit-free-foundations/logging/printf-backend/bad-level.test
A orc-rt/test/regression/jit-free-foundations/logging/printf-backend/debug-compiled-out.test
A orc-rt/test/regression/jit-free-foundations/logging/printf-backend/debug-level.test
A orc-rt/test/regression/jit-free-foundations/logging/printf-backend/format.test
A orc-rt/test/regression/jit-free-foundations/logging/printf-backend/level-off.test
A orc-rt/test/regression/jit-free-foundations/logging/printf-backend/lit.local.cfg
A orc-rt/test/regression/jit-free-foundations/logging/printf-backend/output-redirect.test
A orc-rt/test/regression/jit-free-foundations/logging/printf-backend/runtime-level.test
A orc-rt/test/regression/jit-free-foundations/ogre-help.test
A orc-rt/test/regression/jit-free-foundations/smoke-check.test
A orc-rt/test/regression/languages/c/lit.local.cfg
A orc-rt/test/regression/languages/c/return-zero.c
R orc-rt/test/regression/linux/lit.local.cfg
M orc-rt/test/regression/lit.cfg.py
R orc-rt/test/regression/logging/lit.local.cfg
R orc-rt/test/regression/logging/os_log/delivery.test
R orc-rt/test/regression/logging/os_log/lit.local.cfg
R orc-rt/test/regression/logging/os_log/no-printf-output.test
R orc-rt/test/regression/logging/printf-backend/bad-level.test
R orc-rt/test/regression/logging/printf-backend/debug-compiled-out.test
R orc-rt/test/regression/logging/printf-backend/debug-level.test
R orc-rt/test/regression/logging/printf-backend/format.test
R orc-rt/test/regression/logging/printf-backend/level-off.test
R orc-rt/test/regression/logging/printf-backend/lit.local.cfg
R orc-rt/test/regression/logging/printf-backend/output-redirect.test
R orc-rt/test/regression/logging/printf-backend/runtime-level.test
A orc-rt/test/regression/object-formats/lit.local.cfg
A orc-rt/test/regression/object-formats/mach-o/arm64/lit.local.cfg
A orc-rt/test/regression/object-formats/mach-o/arm64/return-zero.s
A orc-rt/test/regression/object-formats/mach-o/lit.local.cfg
R orc-rt/test/regression/smoke-check.test
Log Message:
-----------
[orc-rt] Reorganize regression tests, add JIT'd code support (#226356)
Reorganize orc-rt/test/regression so that tests are placed by the
question they ask, rather than by the kind of input they use:
jit-free-foundations/ Tests of runtime facilities that can be
exercised without JIT'd code: ogre's command
line, process info, logging, and (in future)
connection lifecycle.
languages/<language>/ Tests that source-language constructs behave
correctly when JIT'd under the ORC runtime.
object-formats/<format>/<arch>/
Tests that object format features (e.g.
relocations, sections, and directives) are
handled correctly, written in assembly.
A README.md describes where tests should go, and the conventions for
writing them. Existing tests move into jit-free-foundations/, and
init.test is renamed to ogre-help.test to describe what it tests. The
darwin/ and linux/ directories are removed: they contained no tests, and
gated on the host rather than the runtime's target. Tests should gate on
features instead.
Add lit support for compiling and running JIT'd code:
%{jit} Runs its inputs under ogre, with llvm-jitlink as the
controller.
%{ogre} The path to ogre.
%{cc} Compiles C for the runtime's target.
%{cxx} Compiles C++ for the runtime's target.
%{mc} Assembles its input for the runtime's target, using
llvm-mc.
%{cc} and %{cxx} default to clang and clang++ from the LLVM tools
directory, and can be overridden with --param orc-rt-cc=<cc> and --param
orc-rt-cxx=<cxx> to test the runtime against output from other
compilers. %{mc} can't be overridden, so that object format tests always
check the runtime against the same assembler.
Tests that use these substitutions are gated on the llvm-jitlink,
llvm-mc, orc-rt-cc, and orc-rt-cxx features, so they are reported as
unsupported (rather than failing) when the tools aren't available.
clang, llvm-jitlink, and llvm-mc are added to the test dependencies if
they're being built alongside the runtime. Object format tests are also
gated on new target-arch=<arch> and target-object-format=<format>
features, derived from the runtime's target triple.
jit-free-foundations/ removes the %{cc}, %{cxx}, %{mc}, and %{jit}
substitutions, so that tests there can't accidentally depend on JIT'd
code.
Add languages/c/return-zero.c and object-formats/mach-o/arm64/
return-zero.s as the first tests that run JIT'd code, establishing the
pattern for each kind of test. They use llvm-jitlink's -show-jit-result
option to check that the JIT'd main actually ran and returned zero.
Commit: 79443248bd4a8bdb8ecfb0de94fa1e7bfb1b16f6
https://github.com/llvm/llvm-project/commit/79443248bd4a8bdb8ecfb0de94fa1e7bfb1b16f6
Author: Nico Weber <thakis at chromium.org>
Date: 2026-09-24 (Thu, 24 Sep 2026)
Changed paths:
M llvm/utils/gn/secondary/clang/unittests/offload-arch/BUILD.gn
Log Message:
-----------
[gn] port 6bef34a7ebbef (#226362)
Commit: 1777581615ec7a7278b87c0a11445c05e34db066
https://github.com/llvm/llvm-project/commit/1777581615ec7a7278b87c0a11445c05e34db066
Author: Vaisman <vasili.svirski at gmail.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M mlir/test/Dialect/NVGPU/invalid.mlir
Log Message:
-----------
[mlir][nvgpu] Add negative tests for invalid FP8 warpgroup MMA types (#208047)
Add negative tests for invalid FP8 type combinations in
nvgpu.warpgroup.mma.
FP8 inputs are supported for f16/f32 accumulators, but the verifier
should still reject unsupported combinations such as FP8 accumulators
and mixed FP8/non-FP8 input element types.
Tested:
llvm-lit mlir/test/Dialect/NVGPU/invalid.mlir
Commit: d9635c615c4d7b00c26d7281036bc5cf210d85fb
https://github.com/llvm/llvm-project/commit/d9635c615c4d7b00c26d7281036bc5cf210d85fb
Author: Nico Weber <thakis at chromium.org>
Date: 2026-09-24 (Thu, 24 Sep 2026)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/TargetParser/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/TargetParser/BUILD.gn
Log Message:
-----------
[gn build] Port 6bef34a7ebbe (#226366)
Commit: 0ce55c6cfa837dcad4561ca7d5740e7c7cdc5154
https://github.com/llvm/llvm-project/commit/0ce55c6cfa837dcad4561ca7d5740e7c7cdc5154
Author: Nico Weber <thakis at chromium.org>
Date: 2026-09-24 (Thu, 24 Sep 2026)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/Target/X86/BUILD.gn
Log Message:
-----------
[gn build] Port 9d90850fe6b0 (#226367)
Commit: 045cefb54385763d1159782ea97b95bb34ff2f2b
https://github.com/llvm/llvm-project/commit/045cefb54385763d1159782ea97b95bb34ff2f2b
Author: Nico Weber <thakis at chromium.org>
Date: 2026-09-24 (Thu, 24 Sep 2026)
Changed paths:
M llvm/utils/gn/secondary/lldb/source/Target/BUILD.gn
Log Message:
-----------
[gn build] Port d0c787e447e1 (#226368)
Commit: a1c9df8e73402eac4c0b3a467e7876f3c387e408
https://github.com/llvm/llvm-project/commit/a1c9df8e73402eac4c0b3a467e7876f3c387e408
Author: Nico Weber <thakis at chromium.org>
Date: 2026-09-24 (Thu, 24 Sep 2026)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/ABI/BUILD.gn
Log Message:
-----------
[gn build] Port f6e450004591 (#226369)
Commit: 5035ea5e1b16ba89eba76994ef50bdf0ff439840
https://github.com/llvm/llvm-project/commit/5035ea5e1b16ba89eba76994ef50bdf0ff439840
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/include/llvm/ExecutionEngine/Orc/JITTargetMachineBuilder.h
Log Message:
-----------
Orc: Compute the JIT DataLayout from the triple and ABI (#226316)
getDefaultDataLayoutForTarget was constructing a throwaway TargetMachine
purely to read back its cached DataLayout. Directly compute it from
the triple and ABI name instead.
Co-Authored-By: Claude Opus 5 <noreply at anthropic.com>
Commit: b15daae148e77f1ad2e20990094ddbeb8cc598ac
https://github.com/llvm/llvm-project/commit/b15daae148e77f1ad2e20990094ddbeb8cc598ac
Author: Changpeng Fang <changpeng.fang at amd.com>
Date: 2026-09-24 (Thu, 24 Sep 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInstructions.td
A llvm/test/CodeGen/AMDGPU/scalar_to_vector_v2bf16.ll
Log Message:
-----------
[AMDGPU] Add scalar_to_vector pattern for v2bf16 (#225303)
A target DAGCombine rewrites `v2bf16 = scalar_to_vector` into bitcast(any_extend),
but it only runs at -O1 and above, so at -O0 the node reaches ISel and fails to select.
Add the missing pattern, mirroring the v2f16 one, for both fake-true16 and real-true16.
Fixes: ROCM-31415
Commit: 28cbb0f0a0c4cbf5e732fa74a362e451a648d26b
https://github.com/llvm/llvm-project/commit/28cbb0f0a0c4cbf5e732fa74a362e451a648d26b
Author: Sven van Haastregt <sven.vanhaastregt at arm.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M clang/include/clang/AST/OpenMPClause.h
Log Message:
-----------
[AST] Avoid deprecated implicit `this` capture for C++20; NFC (#226142)
`OpenMPClause.h` contains a lambda with an implicit `this` capture,
which triggers the C++20 deprecation warning in many compilation units
that (transitively) include this header.
Commit: 6f44f333c3572d3ee54cdfdcba9124424b6ad1df
https://github.com/llvm/llvm-project/commit/6f44f333c3572d3ee54cdfdcba9124424b6ad1df
Author: Mian Miftah <mmiftah.duna at gmail.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/Analysis/TypeBasedAliasAnalysis.cpp
A llvm/test/Analysis/TypeBasedAliasAnalysis/merge-immutable.ll
Log Message:
-----------
[TBAA] Only keep the immutable flag if both merged tags have it (#225907)
getMostGenericTBAA() can return one of the two tags unchanged, as it
does when both have the same base type and offset. If only that tag has
the immutable flag, the merged access claims that the memory is constant
on both paths. For example, after SimplifyCFG hoists two such loads, GVN
can forward a load across a store to the same location.
Keep the immutable flag only if both tags have it. Otherwise drop just
the flag and keep the rest of the tag.
Commit: cfc320ace31d7a62bfbcdbcb08191d89e8e529cf
https://github.com/llvm/llvm-project/commit/cfc320ace31d7a62bfbcdbcb08191d89e8e529cf
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-non-kernel-declaration.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-dynamic-indirect-access-asan.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-dynamic-indirect-access.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-indirect-access-asan.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-indirect-access-lower-all.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-indirect-access-nested-asan.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-indirect-access-nested.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-indirect-access-no-kernel-lds-id.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-indirect-access.ll
A llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/placeholder_escape.ll
A llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/placeholder_escape.ll.expected
A llvm/test/tools/UpdateTestChecks/update_test_checks/placeholder_escape.test
M llvm/utils/UpdateTestChecks/common.py
Log Message:
-----------
[UpdateTestChecks] Escape special characters more consistently (#226203)
The `{{` and `[[` character sequences have special meaning in FileCheck.
Escape these when generating check lines.
We were already doing this for `{{` in analyze tests, where this pattern
occurs e.g. for nested SCEV addrecs. Extend this to `[[`, which occurs
in IR tests due to nested array initializers for globals.
We now need to do this escaping much earlier: `[[...]]` is introduced by
the check line generalization. But even before that, `{{...}}` can be
introduced either via `--replace-value-regex` or via asm scrubbing. So
we perform this escaping right at the start now.
This also updates some AMDGPU LDS tests, which were the motivation for
this change. I've had to manually fix up those check lines one too many
times now...
Commit: 4a63d32442818fd311739ec60c0a31a8e60fe64d
https://github.com/llvm/llvm-project/commit/4a63d32442818fd311739ec60c0a31a8e60fe64d
Author: Fangrui Song <i at maskray.me>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/include/llvm/Support/CommandLine.h
M llvm/lib/Support/CommandLine.cpp
M llvm/unittests/Support/CommandLineTest.cpp
Log Message:
-----------
[Support] Remove LongOptionsUseDoubleDash from cl::ParseCommandLineOptions (#226347)
The mode (https://reviews.llvm.org/D61294), in which `-` introduces only
single-character options and `--` long ones, was added for the
binutils-style tools, which have since moved to OptTable. Its last
users, yaml2obj, obj2yaml and split-file, parse with OptTable now.
LLM-aided
Commit: 210e8f1c567bbaa1b2ac8e3fcb11b106e7b4c520
https://github.com/llvm/llvm-project/commit/210e8f1c567bbaa1b2ac8e3fcb11b106e7b4c520
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.buffer.load.format.f16.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.buffer.load.format.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.buffer.store.format.f16.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.buffer.store.format.f32.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.buffer.load.format.f16.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.buffer.load.format.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.buffer.store.format.f16.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.buffer.store.format.f32.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.tbuffer.load.f16.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.tbuffer.load.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.tbuffer.store.f16.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.tbuffer.store.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.tbuffer.load.f16.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.tbuffer.load.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.tbuffer.store.f16.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.tbuffer.store.ll
M llvm/test/CodeGen/AMDGPU/legalize-soffset-mbuf.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-vimage-vsample.ll
M llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands.mir
Log Message:
-----------
AMDGPU: Mark the SCC def dead in the waterfall loop expansion (#226300)
Commit: 6c6c968398f25c2a56705004f2eb68d21d5de900
https://github.com/llvm/llvm-project/commit/6c6c968398f25c2a56705004f2eb68d21d5de900
Author: Timur Baidusenov <timurbaidusenov at gmail.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/Transforms/AggressiveInstCombine/TruncInstCombine.cpp
M llvm/test/Transforms/AggressiveInstCombine/trunc_unreachable_bb.ll
Log Message:
-----------
[AggressiveInstCombine] Bail out on graph nodes in unreachable blocks (#226383)
TruncInstCombine::run() already skips truncs in unreachable blocks, but
the expression graph of reachable trunc can still be extended into an
unreachable block through a phi incoming value. Dead code may contain an
instruction that is its own operand, and buildTruncExpressionGraph only
breaks cycles at phi nodes, so such a cycle leaves the graph unorderable
and ReduceExpressionGraph asks for the reduced value of a node it has
not built yet.
Solution: Bail out as soon as a graph node is found in an unreachable
block, which extends the existing rule from the trunc itself to the
whole graph.
Fixes #58008.
Commit: 67f685af1b364056fd59fc42841d7f428d46ee1a
https://github.com/llvm/llvm-project/commit/67f685af1b364056fd59fc42841d7f428d46ee1a
Author: Mariya Podchishchaeva <Mariya.Podchishchaeva at amd.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/lib/CIR/CodeGen/CIRGenAtomic.cpp
M clang/lib/CIR/CodeGen/CIRGenBuilder.h
M clang/lib/CIR/CodeGen/CIRGenBuiltin.cpp
M clang/lib/CIR/CodeGen/CIRGenExprAggregate.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
M clang/test/CIR/CodeGen/assign-operator.cpp
M clang/test/CIR/CodeGen/atomic.c
A clang/test/CIR/CodeGen/builtin-memcpy.c
M clang/test/CIR/CodeGen/libc.c
M clang/test/CIR/CodeGen/union-copy-move-assignment.cpp
M clang/test/CIR/CodeGenBuiltins/builtin-bit-cast.cpp
Log Message:
-----------
[CIR] Lower __builtin_memcpy/mempcpy to cir.libc.memcpy (#225845)
These previously were lowered to a call to undefined memcpy function
which caused link failures when compiled for AMDGPU since there it is
never resolved to a library function.
cir.libc.memcpy is later lowered to llvm.memcpy intrinsic call which
matches classic codegen.
This also adds alignment attributes to cir.libc.memcpy op so resulting
LLVM IR also has them just like LLVM IR produced by the classic codegen
Assisted by: claude
Commit: d9a236056a778276b286d6df818fecc5766603a6
https://github.com/llvm/llvm-project/commit/d9a236056a778276b286d6df818fecc5766603a6
Author: Ralf Jung <post at ralfj.de>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/docs/LangRef.md
M llvm/docs/UndefinedBehavior.md
Log Message:
-----------
LangRef: mention that willreturn can cause time-traveling UB (#214229)
I think with #192992, the only remaining possible source of
time-traveling UB in LLVM are `willreturn` annotations emitted by the
frontend. So let's add a note about that.
I think ideally we'd also say somewhere "UB cannot time-travel except if
you put `willreturn` on a function that has observable behavior", but I
am not sure what would be a good place for that.
Cc @nikic @dtcxzyw @gonzalobg
Commit: fe1f8494628afdd4252fc607d7bccafa2fb64b35
https://github.com/llvm/llvm-project/commit/fe1f8494628afdd4252fc607d7bccafa2fb64b35
Author: Daniel Cederman <cederman at gaisler.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
A clang/test/Driver/print-enabled-extensions/riscv-gaisler-gr765.c
M clang/test/Driver/riscv-cpus.c
M clang/test/Misc/target-invalid-cpu-note/riscv.c
M llvm/docs/ReleaseNotes.md
M llvm/lib/Target/RISCV/RISCVProcessors.td
Log Message:
-----------
[RISCV] Add processor definition for GR765 (#225638)
Add support for the GR765 processor from Frontgrade Gaisler.
https://www.gaisler.com/products/gr765
Assisted-by: Codex
Commit: 6a9a95bf0c62cccbffed5b481b40cdbae8a5c959
https://github.com/llvm/llvm-project/commit/6a9a95bf0c62cccbffed5b481b40cdbae8a5c959
Author: David Sherwood <david.sherwood at arm.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/include/llvm/Transforms/Utils/ScalarEvolutionExpander.h
M llvm/lib/Transforms/Utils/ScalarEvolutionExpander.cpp
Log Message:
-----------
[Analysis][NFC] Address review comments from PR #213013 (#225800)
Commit: cf8ce56a1f39f9a771d03aeedd9d89475e72a659
https://github.com/llvm/llvm-project/commit/cf8ce56a1f39f9a771d03aeedd9d89475e72a659
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/CodeGen/RegAllocFast.cpp
A llvm/test/CodeGen/X86/regallocfast-implicit-def-live-out.mir
Log Message:
-----------
RegAllocFast: Mark unspilled implicit_def physreg defs dead (#226295)
When a virtual register defined by an IMPLICIT_DEF is live out of the
block, or reloaded below, defineVirtReg deliberately skips the spill.
If there is also no use of the value in the block, the resulting physreg
def has no reader at all, but was left without a dead flag.
This avoids some unnecessary churn between regalloc runs on AMDGPU.
Since RA runs multiple times, missed dead flags in the first RA run get
re-inferred by the later runs which this avoids.
Co-authored-by: Claude Opus 5 <noreply at anthropic.com>
Commit: f131c8c21397e19c439070070348c17cc3ca2112
https://github.com/llvm/llvm-project/commit/f131c8c21397e19c439070070348c17cc3ca2112
Author: ilia-cher <30845429+ilia-cher at users.noreply.github.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/lirp.mir
Log Message:
-----------
[AMDGPU] Use CFG in LIRP tests (#226260)
LIRP tests (llvm/test/CodeGen/AMDGPU/lirp.mir) use live intervals with
gaps and redefinitions.
With added -verify-machineinstrs, current test examples trigger machine
code check failure ("Multiple connected components in live interval").
This PR updates the tests to use CFG (loops with loop-carried vregs)
similar to the real world use cases, to fix the verification, and also
simplifies the tests a bit (using implifit defs and kills).
Test:
```
ninja -C build
ninja -C build check-llvm
./build/bin/llvm-lit -v llvm/test/CodeGen/AMDGPU/lirp.mir
```
Commit: 6bfa1c552ea19edad20a76c773f480175ef58797
https://github.com/llvm/llvm-project/commit/6bfa1c552ea19edad20a76c773f480175ef58797
Author: Aman Maurya <amanmaurya9209 at gmail.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M libc/config/linux/aarch64/entrypoints.txt
M libc/config/linux/riscv/entrypoints.txt
M libc/config/linux/x86_64/entrypoints.txt
M libc/include/sys/select.yaml
M libc/src/__support/OSUtil/linux/syscall_wrappers/CMakeLists.txt
A libc/src/__support/OSUtil/linux/syscall_wrappers/pselect6.h
M libc/src/sys/select/CMakeLists.txt
M libc/src/sys/select/linux/CMakeLists.txt
A libc/src/sys/select/linux/pselect.cpp
M libc/src/sys/select/linux/select.cpp
A libc/src/sys/select/pselect.h
M libc/test/src/sys/select/CMakeLists.txt
A libc/test/src/sys/select/pselect_test.cpp
Log Message:
-----------
[libc] Implement pselect in sys/select (#226237)
Implement the standard POSIX.1-2008 / POSIX.1-2024 function `pselect` in
`<sys/select.h>`, bringing `<sys/select.h>` to 100% POSIX completion.
Fixes #226195.
Commit: 1306a7839d3eb573ff155fea66ee13e97cabf814
https://github.com/llvm/llvm-project/commit/1306a7839d3eb573ff155fea66ee13e97cabf814
Author: Luke Lau <luke at igalia.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/rvv/compressstore.ll
M llvm/test/CodeGen/RISCV/rvv/expandload.ll
Log Message:
-----------
[RISCV] Fix scalable expandload lowering for i8 types (#225141)
This PR adds tests for scalable expandload/compressstore intrinsics, and
also fixes a crash where we tried to query getVectorNumElements on a
scalable vector for i8 element types.
We need to use vrgatherei16 when VLMAX may exceed 255, so compute this
for scalable vectors based off of getRealMaxVLen.
This is in preparation for compress pattern vectorization support in
https://github.com/llvm/llvm-project/pull/214491
Commit: 7bcd6b42a9250baab46ad735d0c4bb4d43e74c37
https://github.com/llvm/llvm-project/commit/7bcd6b42a9250baab46ad735d0c4bb4d43e74c37
Author: Luke Lau <luke at igalia.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/test/Analysis/CostModel/RISCV/rvv-expandload-compressstore.ll
Log Message:
-----------
[RISCV] Return cost for scalable compressstore/expandload intrinsics (#225143)
The type based cost still needs fixed.
Commit: 74c5a6421b6bb260ef09e6d5f941970ae55629ce
https://github.com/llvm/llvm-project/commit/74c5a6421b6bb260ef09e6d5f941970ae55629ce
Author: Luke Lau <luke at igalia.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVSubtarget.cpp
M llvm/lib/Target/RISCV/RISCVSubtarget.h
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
Log Message:
-----------
[RISCV] Remove getMaxLMULForFixedLengthVectors. NFC (#226111)
The value can no longer be overridden after
https://github.com/llvm/llvm-project/pull/207312. Now there's nothing
specific about it to fixed vectors, so just inline it.
Commit: f17893d88ac11a34fc26dacd78f18bde2836334b
https://github.com/llvm/llvm-project/commit/f17893d88ac11a34fc26dacd78f18bde2836334b
Author: Pavel Labath <pavel at labath.sk>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M libc/src/__support/OSUtil/linux/syscall_wrappers/chmod.h
M libc/src/sys/stat/linux/CMakeLists.txt
M libc/test/src/sys/stat/CMakeLists.txt
M libc/test/src/sys/stat/chmod_test.cpp
Log Message:
-----------
[libc] Fix chmod syscall arguments and add symlink test (#226144)
Our Linux chmod wrapper had two bugs in how it invoked syscalls:
- the fchmodat syscall only takes three arguments (dfd, filename, mode),
but we were passing four (with a trailing 0 for flags).
- for fchmodat2, we were (mistakenly) passing AT_SYMLINK_NOFOLLOW, even
though chmod is specified to follow symlinks.
I reorder the checks to prefer fchmodat2 (with flags=0) if available,
and otherwise invoke fchmodat with the three arguments it expects.
I also add a test to verify that chmod follows symlinks and updates the
target file's permissions, and that attempting to chmod a dangling
symlink fails with ENOENT.
Assisted-by: Gemini
Commit: 6c5ea9581684f5a819aa1691f30ae410d2a24df4
https://github.com/llvm/llvm-project/commit/6c5ea9581684f5a819aa1691f30ae410d2a24df4
Author: Jay Foad <jay.foad at amd.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/include/llvm/Analysis/ConstantFolding.h
M llvm/include/llvm/Analysis/InstructionSimplify.h
M llvm/include/llvm/Analysis/LazyValueInfo.h
M llvm/include/llvm/Analysis/Loads.h
M llvm/include/llvm/Analysis/SimplifyQuery.h
M llvm/include/llvm/Analysis/TargetFolder.h
M llvm/include/llvm/Analysis/TargetTransformInfo.h
M llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
M llvm/include/llvm/Analysis/ValueTracking.h
M llvm/include/llvm/CodeGen/BasicTTIImpl.h
M llvm/include/llvm/Transforms/InstCombine/InstCombiner.h
M llvm/include/llvm/Transforms/Scalar/JumpThreading.h
M llvm/include/llvm/Transforms/Utils/Local.h
M llvm/lib/Analysis/BasicAliasAnalysis.cpp
M llvm/lib/Analysis/ConstantFolding.cpp
M llvm/lib/Analysis/InstructionSimplify.cpp
M llvm/lib/Analysis/LazyValueInfo.cpp
M llvm/lib/Analysis/Loads.cpp
M llvm/lib/Analysis/ScalarEvolution.cpp
M llvm/lib/Analysis/TargetTransformInfo.cpp
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/lib/MC/MCPseudoProbe.cpp
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
M llvm/lib/Target/AMDGPU/AMDGPULateCodeGenPrepare.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h
M llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
M llvm/lib/Target/ARM/ARMTargetTransformInfo.h
M llvm/lib/Target/BPF/BPFTargetTransformInfo.h
M llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp
M llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.h
M llvm/lib/Target/Lanai/LanaiTargetTransformInfo.h
M llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.cpp
M llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.h
M llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
M llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
M llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp
M llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.h
M llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.h
M llvm/lib/Target/X86/X86TargetTransformInfo.cpp
M llvm/lib/Target/X86/X86TargetTransformInfo.h
M llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
M llvm/lib/Transforms/InstCombine/InstCombineInternal.h
M llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp
M llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
M llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp
M llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
M llvm/lib/Transforms/Scalar/CorrelatedValuePropagation.cpp
M llvm/lib/Transforms/Scalar/JumpThreading.cpp
M llvm/lib/Transforms/Scalar/MergeICmps.cpp
M llvm/lib/Transforms/Utils/Local.cpp
M llvm/lib/Transforms/Utils/SimplifyCFG.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPCostAnalysis.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPCostAnalysis.h
M llvm/lib/Transforms/Vectorize/VectorCombine.cpp
M llvm/unittests/Analysis/ValueTrackingTest.cpp
M llvm/unittests/FileCheck/FileCheckTest.cpp
Log Message:
-----------
[LLVM] Fix typo "CxtI" (#226137)
LLVM had many instances of both "CxtI" and "CtxI". This patch
standardizes on the latter. I regard the former as a mistake that should
never have spread. In general usage, "ctx" is much more common as an
abbreviation for "context".
Same for "CxtF" and "CxtPhi" which occurred a few times each.
Also fix the few instances of "Cxt" to "Ctx", which was already
overwhelmingly more common.
Commit: b202c00d967c22f5d4d83561024690f1de05bc01
https://github.com/llvm/llvm-project/commit/b202c00d967c22f5d4d83561024690f1de05bc01
Author: Manuel Carrasco <Manuel.Carrasco at amd.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/utils/lit/lit/main.py
M llvm/utils/lit/lit/util.py
A llvm/utils/lit/tests/unit/Histogram.py
Log Message:
-----------
[lit] Include zero-duration tests in the --time-tests histogram (#226132)
`--time-tests` treated an elapsed time of 0 as missing, so they were
omitted from the histogram. That made time-tests.py flaky when FileCheck
expected every test to be listed.
The PR also avoids log(0) when every recorded time is zero.
Fixes
https://github.com/llvm/llvm-project/pull/208444#issuecomment-5805067757.
Commit: 54e14c19be73548fd0c990bc3aac6d9204f3ebf8
https://github.com/llvm/llvm-project/commit/54e14c19be73548fd0c990bc3aac6d9204f3ebf8
Author: Lang Hames <lhames at gmail.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M orc-rt/include/orc-rt/support/Error.h
M orc-rt/test/unit/support/ErrorTest.cpp
Log Message:
-----------
[orc-rt] Make Expected's move operations conditionally noexcept. (#226393)
Expected<T>'s move constructor and move assignment operator are now
noexcept whenever T's storage type is nothrow-move-constructible.
Error's move operations are already noexcept, so this is the only
condition under which moving an Expected can throw.
This allows callables that take Expected<T> by value to be stored in
noexcept-qualified move_only_functions: is_nothrow_invocable includes
the initialization of by-value parameters, which previously used
Expected's potentially-throwing move constructor.
Commit: 0a0e0fa181cf162bcc93be85abf2b1b911027e73
https://github.com/llvm/llvm-project/commit/0a0e0fa181cf162bcc93be85abf2b1b911027e73
Author: yahia <yahia.a.abdrabou at gmail.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M libc/config/linux/aarch64/entrypoints.txt
M libc/config/linux/riscv/entrypoints.txt
M libc/config/linux/x86_64/entrypoints.txt
M libc/include/arpa/inet.yaml
M libc/src/__support/net/CMakeLists.txt
M libc/src/__support/net/address.cpp
M libc/src/__support/net/address.h
M libc/src/arpa/inet/CMakeLists.txt
A libc/src/arpa/inet/inet_pton.cpp
A libc/src/arpa/inet/inet_pton.h
M libc/test/src/arpa/inet/CMakeLists.txt
A libc/test/src/arpa/inet/inet_pton_test.cpp
Log Message:
-----------
Implement inet_pton (#224644)
Implement the `inet_pton` function for `IPV4` and its unit tests.
Assisted-by: gemini
Commit: 1cc5657c4ff663f1284d8a4ba4ef156e4b1664ae
https://github.com/llvm/llvm-project/commit/1cc5657c4ff663f1284d8a4ba4ef156e4b1664ae
Author: Ebuka Ezike <e_ezike at apple.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M lldb/tools/lldb-dap/DAP.cpp
M lldb/tools/lldb-dap/LLDBUtils.h
Log Message:
-----------
[lldb-dap] Create telemetry data only when built with telemetry. (#225785)
I am exploring fuzzing some parts of lldb-dap. but there is a fixed
amount of memory lldb-dap can use before the fuzzing stops to catch
memory leaks.
The telemetry dispatcher always creates telemetry regardless of if lldb
is built with telemetry enabled.
`SBStructuredData::SetFromJSON` adds the telemetry string to the
ConstString pool for every request and grows lldb-dap's memory usage
rapidly.
Commit: 91d5a537b6b2b62eb1d3dbc5c9c358d2d699ff26
https://github.com/llvm/llvm-project/commit/91d5a537b6b2b62eb1d3dbc5c9c358d2d699ff26
Author: Bruno De Fraine <bruno.defraine at globalfoundries.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M clang/CMakeLists.txt
M clang/lib/CIR/CMakeLists.txt
M clang/tools/cir-opt/CMakeLists.txt
Log Message:
-----------
[clang] Drop explicit -Woverloaded-virtual build option (#225359)
Nowadays, Clang and GCC have reasonable (and aligned) default
`-Woverloaded-virtual` warnings when using `-Wall`. Fall back to this
default and omit the more aggressive `-Woverloaded-virtual` warnings
only present in GCC's level 2 mode of the warning.
The motivation for this change is discussed in the following RFC:
https://discourse.llvm.org/t/rfc-drop-explicit-woverloaded-virtual-clang-build-option/91857
Removing the explicit `-Woverloaded-virtual` build option also allows
removing the workaround from e1bd39c.
Commit: 1735c1018def10b48b8bc1c0f6875737ae0fd9da
https://github.com/llvm/llvm-project/commit/1735c1018def10b48b8bc1c0f6875737ae0fd9da
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/test/Instrumentation/SanitizerCoverage/missing_dbg.ll
A llvm/test/Instrumentation/SanitizerCoverage/missing_dbg_stack_depth.ll
Log Message:
-----------
[SanitizerCoverage] Split test (NFC) (#226405)
So these tests can actually be regenerated without heavy manual
editing.
Commit: d9dbd9671c1f2481727a9015d7fa23129a7c396d
https://github.com/llvm/llvm-project/commit/d9dbd9671c1f2481727a9015d7fa23129a7c396d
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanUtils.h
M llvm/test/Transforms/LoopVectorize/X86/x86-interleaved-accesses-masked-group.ll
M llvm/test/Transforms/LoopVectorize/induction-wrapflags.ll
Log Message:
-----------
[VPlan] Only retain NSW when possible in getFlagsFromIndDesc. (#226315)
getFlagsFromIndDesc is used to get the flags to use for wide inductions.
Those are normalized to Adds, with the step negated if the induction
binop is Sub.
Only retain all flags for Add. For Sub, never retain NUW and only keep
NSW if the step is known to not be signed min.
Alive2 Proofs showing incorrect NUW/NSW transfer and transfer of NSW if
step is != signed INT_MIN: https://alive2.llvm.org/ce/z/zGKeZg
Fixes https://github.com/llvm/llvm-project/issues/224024.
Commit: a465ac2be931ec1f21c9807434d59cb3b92d4b06
https://github.com/llvm/llvm-project/commit/a465ac2be931ec1f21c9807434d59cb3b92d4b06
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M clang/lib/AST/APValue.cpp
Log Message:
-----------
[clang][NFC] Use llvm::ListSeparator in APValue::printPretty (#226125)
Instead of the manual `First` flag tracking.
Commit: 81e2e4474b3eb6a06e4269b97c7d33c561a3f14f
https://github.com/llvm/llvm-project/commit/81e2e4474b3eb6a06e4269b97c7d33c561a3f14f
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/Analysis/ScalarEvolution.cpp
M llvm/test/Analysis/ScalarEvolution/trip-count13.ll
Log Message:
-----------
[SCEV] Set BTC to zero, if constant max BTC < BECountIfTaken. (#226098)
If ConstantMaxBECount < BECountIfTaken, we know that the backedge is
never taken and BTC is zero.
No changes in
https://github.com/dtcxzyw/llvm-opt-benchmark-nightly/pull/1426.
The main motivation is to remove another difference between
howManyLessThans
and howManyGreaterThans, which does not have the BECountIfBackedgeTaken
logic and would compute tighter bounds for backedges never taken.
No compile-time impact:
https://llvm-compile-time-tracker.com/compare.php?from=022fdfa1e5a0b85dc785d30b17be3880768b22dc&to=475eeff40ba520620a406a3f615d660ed7c3eec0&stat=instructions:u
PR: https://github.com/llvm/llvm-project/pull/226098
Commit: 99b454814e243b4d5f206d9605d3ab5b6e73f4b4
https://github.com/llvm/llvm-project/commit/99b454814e243b4d5f206d9605d3ab5b6e73f4b4
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/test/Instrumentation/InstrProfiling/conditional-counter-updates.ll
Log Message:
-----------
[InstrProfiling] Generate test checks (NFC) (#226409)
Commit: 41165fd5d503b4297cb1033fdeb1688ce0863b68
https://github.com/llvm/llvm-project/commit/41165fd5d503b4297cb1033fdeb1688ce0863b68
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3bf16.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3f16.v2f16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3i16.v2i16.ll
M llvm/test/CodeGen/X86/bfloat.ll
M llvm/test/CodeGen/X86/dag-topological-sort.ll
M llvm/test/CodeGen/X86/load-partial-dot-product.ll
Log Message:
-----------
[DAG] SimplifyMultipleUseDemandedBits - simplify ISD::SCALAR_TO_VECTOR to ISD::POISON if we don't demand 0th element (#225530)
Equivalent fold to SimplifyDemandedBits/SimplifyDemandedVectorElts
Fixes a number of minor regressions from #217185
Commit: d689d0fd01a0ffcfbc1c947ec3a14997f96217d0
https://github.com/llvm/llvm-project/commit/d689d0fd01a0ffcfbc1c947ec3a14997f96217d0
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/test/Instrumentation/DataFlowSanitizer/origin_load.ll
M llvm/test/Instrumentation/DataFlowSanitizer/origin_select.ll
M llvm/test/Instrumentation/DataFlowSanitizer/origin_store.ll
Log Message:
-----------
[DFSan] Generate test checks (NFC) (#226410)
Commit: af8da03a34ba80c310b9253c4cb062fdfdd5a143
https://github.com/llvm/llvm-project/commit/af8da03a34ba80c310b9253c4cb062fdfdd5a143
Author: Lang Hames <lhames at gmail.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M orc-rt/include/orc-rt/bedrock/Session.h
M orc-rt/lib/bedrock/NativeDylibManager.cpp
M orc-rt/test/unit/CommonTestUtils.h
M orc-rt/test/unit/bedrock/SessionTest.cpp
M orc-rt/test/unit/bedrock/sps/SimpleRemoteCAOverSocketTest.cpp
M orc-rt/test/unit/bedrock/sps/SimpleRemoteCATest.cpp
M orc-rt/tools/ogre/ogre.cpp
Log Message:
-----------
[orc-rt] Make more Session callbacks noexcept. (#226385)
Session's OnDisconnectFn, OnDetachFn, and OnShutdownFn callbacks should
not throw exceptions.
Commit: f4620e36f5d06df795fda3ef4fd421509609ca5a
https://github.com/llvm/llvm-project/commit/f4620e36f5d06df795fda3ef4fd421509609ca5a
Author: Andrew Ng <andrew.ng at sony.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M lld/ELF/MarkLive.cpp
M lld/test/ELF/why-live.test
Log Message:
-----------
[LLD][ELF] Skip symbols to dead mergeable section pieces for --why-live (#226238)
Before this change, `--why-live=*` in "why-live.test" incorrectly prints
`live symbol: b.o:(dead)`.
Commit: 75811754a2e6c846543354358317ee02c32c2ce4
https://github.com/llvm/llvm-project/commit/75811754a2e6c846543354358317ee02c32c2ce4
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M mlir/lib/Dialect/Tensor/Transforms/ScalarizeFunctionResult.cpp
Log Message:
-----------
[mlir][Tensor] Stop using `getAttrs()` and only copy discardable call attributes explicitly (#226412)
Preserve discardable metadata when recreating a typed direct call; its
builder supplies the inherent fields.
Part of #155475
Assisted-by: Codex
Commit: 728813099e29e7255e2c4ab7098297ba0eb9b320
https://github.com/llvm/llvm-project/commit/728813099e29e7255e2c4ab7098297ba0eb9b320
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M mlir/lib/Dialect/OpenACC/Transforms/ACCRoutineLowering.cpp
Log Message:
-----------
[mlir][OpenACC] Stop using getAttrs() and copy function properties separately (NFC) (#226414)
Copy inherent properties and discardable attributes explicitly when
staging a device function.
Part of #155475
Assisted-by: Codex
Commit: 0e232314ca9eda04abe27bc8c7cf7c10666c54c1
https://github.com/llvm/llvm-project/commit/0e232314ca9eda04abe27bc8c7cf7c10666c54c1
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M mlir/lib/Dialect/Quant/Transforms/NormalizeQuantTypes.cpp
Log Message:
-----------
[mlir][Quant] Stop using Operation::getAttrs (NFC) (#226413)
Pass raw attributes separately from property storage when recreating an
operation.
Part of #155475
Assisted-by: Codex
Commit: e6115bc07692e0e9e632c88b2b4da99728d2951d
https://github.com/llvm/llvm-project/commit/e6115bc07692e0e9e632c88b2b4da99728d2951d
Author: Jay Foad <jay.foad at amd.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp
Log Message:
-----------
[AMDGPU] Make setImpSCCDefDead default to true. NFC. (#226406)
In SILowerControlFlow, in helper function setImpSCCDefDead, make
parameter IsDead default to true to match MachineOperand::setIsDead.
Commit: afa81ffa95ca08a20c28d9e9487404ea06a89c55
https://github.com/llvm/llvm-project/commit/afa81ffa95ca08a20c28d9e9487404ea06a89c55
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
Log Message:
-----------
[mlir][LLVM] Stop using Operation::getAttrs in custom printers (NCF) (#226418)
At the moment, the assembly format for these operations mixes
discardable and inherent attributes. We should fix it. But for now, stop
using the `getAttrs()` API that is on its way to deprecation.
Part of #155475
Assisted-by: Codex
Commit: 51b1c275718891743493f3ed5d9e54d91a027e2d
https://github.com/llvm/llvm-project/commit/51b1c275718891743493f3ed5d9e54d91a027e2d
Author: John Brawn <john.brawn at arm.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Scalar/SROA.cpp
A llvm/test/Transforms/SROA/load-store-overlap.ll
Log Message:
-----------
[SROA] Pre-split overlapping move slices within a partition (#210061)
When we have an overlapping load and store within an alloca, e.g. due to
a memmove that has been transformed into a load+store by InstCombine,
then currently SROA can't do anything with it. By pre-splitting such
loads and stores we eliminate any overlap between slices and thus SROA
can optimize them.
Commit: 581edb7b4a7cd8a274aec9ea4ce067eae4aaec70
https://github.com/llvm/llvm-project/commit/581edb7b4a7cd8a274aec9ea4ce067eae4aaec70
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M mlir/lib/Conversion/XeVMToLLVM/XeVMToLLVM.cpp
Log Message:
-----------
[mlir][XeVM] Stop using `getAttrs()`: explicitly preserve properties when cloning operations (NFC) (#226420)
Pass raw attributes and serialized properties separately through
OperationState when cloning an operation.
Part of #155475
Assisted-by: Codex
Commit: dc744d9839ca01185a9d19790f0b6bc18361d667
https://github.com/llvm/llvm-project/commit/dc744d9839ca01185a9d19790f0b6bc18361d667
Author: Abid Qadeer <haqadeer at amd.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M flang/include/flang/Optimizer/Dialect/FIROps.td
M flang/include/flang/Optimizer/Dialect/FIROpsSupport.h
M flang/lib/Lower/Bridge.cpp
M flang/lib/Optimizer/Transforms/AddDebugInfo.cpp
M flang/test/Fir/fir-ops.fir
A flang/test/Integration/debug-submodule-ancestor.F90
A flang/test/Integration/debug-submodule-nested.F90
M flang/test/Integration/debug-submodule-procedure.F90
A flang/test/Lower/debug-submodule.f90
M flang/test/Transforms/debug-module-submodule-procedure.fir
A flang/test/Transforms/debug-submodule.fir
Log Message:
-----------
[flang][debug] Describe submodules in the debug info (#225852)
A submodule had no presence of its own in the debug info. Everything it
defined was attributed to the module at the root of its ancestry, so a
debugger showed one module per source file, every one of them carrying
the
name and the line of that ancestor, and it listed the variables of a
submodule as if the ancestor had declared them.
This PR describes a submodule in its own right. There are two
independent strands to it, and they meet only in that both decide which
module an entity is scoped in.
## Thread A: describing the submodule
### Recording the ancestry
A submodule is not a first class entity in FIR. It is not mangled into
the name of anything it declares in a way that distinguishes it from a
module, and its own name is unqualified, so nothing downstream could
tell `impl` of
`shapes` from a module called `impl`. Lowering now records the ancestry
on `fir.module_debug_imports`, which it already emits once for every
module and submodule it compiles:
```
fir.module_debug_imports "shapes" { }
fir.module_debug_imports "impl" in "shapes" parent "shapes" { }
fir.module_debug_imports "deep" in "shapes" parent "impl" { }
```
`ancestor_module` is the module at the root, and `parent_module` is the
one directly above, which is that same module for a first level
submodule and a submodule of it otherwise. Both are needed and neither
can be derived from
the other in a unit that compiles the submodule alone. The division
mirrors semantics, which keeps `ModuleDetails::ancestor()` and
`ModuleDetails::parent()` apart for the same reason.
### Naming
DWARF has no way to say that a module entry is a submodule, so the name
has to carry it. The submodule is named after the module at the root of
its ancestry and itself, joined with a `.`, which is what gfortran does:
```
DW_TAG_module DW_AT_name ("shapes.impl")
DW_TAG_module DW_AT_name ("shapes.deep")
```
The standard makes the pair unique among the submodules of a program,
and a `.` cannot appear in a Fortran identifier, so the result can never
be confused with a module that is really called that. A nested submodule
is named after the root and itself, not after the submodule containing
it, so `deep` of `shapes:impl` is `shapes.deep`. That too follows
gfortran, and it keeps the name independent of how deep the nesting
happens to be.
### Importing the parent
Scoping the entities of a submodule at the submodule loses something: a
submodule also has access to everything declared above it, and nothing
in the name of a module entry says so. Each submodule therefore imports
the one
directly above it:
```
DW_TAG_module DW_AT_name ("shapes.impl")
DW_TAG_imported_module DW_AT_import ("shapes")
DW_TAG_module DW_AT_name ("shapes.deep")
DW_TAG_imported_module DW_AT_import ("shapes.impl")
```
A debugger walks that chain up from wherever it is stopped, so an entity
declared anywhere above a submodule is still found by name. This is
again what gfortran emits, down to importing the immediate parent rather
than the root.
The entries hang off the compile unit rather than off any one procedure,
so that a submodule needs a single one however many procedures it holds.
That makes the compile unit name a module that names the compile unit
back, so it
is built as a recursive attribute, the same way a subprogram holding
imported entities already is. A unit that compiles no submodule is
unchanged.
## Thread B: separate module procedures
A separate module procedure is mangled with the module that declares its
interface rather than the submodule that defines it, because that is the
name its callers use:
```fortran
module shapes
interface
module function square(n) result(r) ! declared here
```
```fortran
submodule (shapes) impl
contains
module function square(n) result(r) ! defined here
```
```
DW_AT_linkage_name ("_QMshapesPsquare") ! names shapes, not impl
```
Every other entity of a submodule carries the whole chain in its uniqued
name: `_QMshapesSimplSdeepEdeep_var` names `shapes`, `impl` and `deep`
in turn. A separate module procedure names only the ancestor, so the
submodule defining it is recorded nowhere, and the procedure was
reported as belonging to the ancestor. Lowering now notes that submodule
on the function as `fir.defining_submodule`.
With that, nothing is scoped at the ancestor of a submodule any more,
and `AddDebugInfoPass::markSubmoduleAncestorsDefined` goes away. It
marked the ancestor as defined wherever a submodule was compiled, so
that the entities hanging off it could reach a compile unit; its comment
said it should go once submodules were described in their own right.
## What this looks like in a debugger
Given a module, a submodule defining its procedure, and a program
calling it:
```fortran
module subpar
interface
module subroutine hello()
end subroutine
end interface
end module subpar
```
```fortran
submodule (subpar) subkid
contains
module subroutine hello()
print *, 'hello from submodule'
end subroutine hello
end submodule subkid
```
A breakpoint on the bare name works before and after, but it now reports
where
the procedure really is, and it can be qualified that way too:
| `gdb -batch -ex 'break ...'` | before | after |
| --- | --- | --- |
| `hello` | `in subpar::hello at kid.f90:4` | `in subpar.subkid::hello
at kid.f90:4` |
| `subpar.subkid::hello` | `Function ... not defined.` | `in
subpar.subkid::hello at kid.f90:4` |
| `subpar::hello` | `in subpar::hello at kid.f90:4` | `Function ... not
defined.` |
The last row is the one to note: `break subpar::hello` stops working,
since the procedure is no longer described as belonging to `subpar`
alone. That is a deliberate change rather than a step backwards and
gfortran behaves exactly as this patch does on all three spellings, so
this brings flang into line with it rather than away from it.
The import is what keeps name lookup working from inside a submodule.
Stopped in a procedure of `submodule (par3) kid3`, which uses `pv`, `pk`
and `ptbl` from `par3` and its own `sq`:
```
(gdb) print pv $1 = 1
(gdb) print pk $1 = 5
(gdb) print ptbl $1 = (7, 8, 9)
(gdb) print sq $1 = (9, 8, 7)
```
Fixes https://github.com/llvm/llvm-project/issues/215811
Assisted By: Cursor
---------
Co-authored-by: Cursor <cursoragent at cursor.com>
Commit: 771af157a35d7342a895a016f87b62b02a54aceb
https://github.com/llvm/llvm-project/commit/771af157a35d7342a895a016f87b62b02a54aceb
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M flang/lib/Optimizer/Transforms/CUDA/CUFDeviceFuncTransform.cpp
Log Message:
-----------
[flang][CUDA] Stop using Operation::getAttrs in host stubs (NFC) (#226421)
Copy function properties and discardable attributes separately when
creating a host stub.
Part of #155475
Assisted-by: Codex
Commit: fb13f6fa52cbcd501b0dcac128254818e2d24214
https://github.com/llvm/llvm-project/commit/fb13f6fa52cbcd501b0dcac128254818e2d24214
Author: Luke Lau <luke at igalia.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h
M llvm/lib/Transforms/Vectorize/VPlan.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.h
M llvm/lib/Transforms/Vectorize/VPlanUtils.h
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-complex-mask.ll
Log Message:
-----------
[VPlan] Append recipes created via builder to worklist
(#213900)
The previous PR appended the top most created recipe to the worklist,
and this PR extends it to any other nested recipes that were created,
similar to InstCombine.
This removes the header mask in a good few more places on RISC-V as
measured on SPEC CPU 2017, e.g. for the following loop:
```c
long f(const int *p, const int *q, long n) {
long a = 0, b = 0;
for (long i = 0;; i++) {
if (p[i] && q[i]) { a += i; b += i; }
if (i + 1 == n) break;
}
return a + b;
}
```
Before:
```asm
LBB0_1:
sh2add a4, a3, a0
vsetvli a5, a2, e32, m1, ta, ma
vle32.v v16, (a4)
vmsne.vi v0, v16, 0
sh2add a4, a3, a1
vsetvli zero, zero, e64, m2, ta, ma
vmsltu.vx v16, v10, a5
vle32.v v17, (a4), v0.t
vsetvli zero, zero, e32, m1, ta, ma
vmsne.vi v17, v17, 0
vmand.mm v17, v0, v17
vmand.mm v0, v16, v17
vsetvli zero, zero, e64, m2, tu, mu
vadd.vv v8, v14, v8, v0.t
vadd.vv v12, v14, v12, v0.t
vsetvli zero, zero, e64, m2, ta, ma
vadd.vx v14, v14, a5
sub a2, a2, a5
add a3, a3, a5
bnez a2, .LBB0_1
```
After:
```asm
.LBB0_1:
sh2add a4, a3, a0
vsetvli a5, a2, e32, m1, ta, ma
vle32.v v14, (a4)
vmsne.vi v0, v14, 0
sh2add a4, a3, a1
vle32.v v14, (a4), v0.t
vmsne.vi v14, v14, 0
vmand.mm v0, v0, v14
vsetvli zero, zero, e64, m2, tu, mu
vadd.vv v8, v12, v8, v0.t
vadd.vv v10, v12, v10, v0.t
vsetvli zero, zero, e64, m2, ta, ma
vadd.vx v12, v12, a5
sub a2, a2, a5
add a3, a3, a5
bnez a2, .LBB0_1
```
We can also remove the (X && Y) | (X && !Y) -> X combine, but this is
left for another NFC PR.
Commit: 4b66c9678662933ff13f8362e3a208cbe6284808
https://github.com/llvm/llvm-project/commit/4b66c9678662933ff13f8362e3a208cbe6284808
Author: Luke Lau <luke at igalia.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/include/llvm/CodeGen/SDPatternMatch.h
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/unittests/CodeGen/SelectionDAGPatternMatchTest.cpp
Log Message:
-----------
[SDPatternMatch] Remove MatchContext. NFC (#218372)
This removes the match context templating now that trivial VP nodes are
gone.
`m_Negative` and the other computeKnownBits matchers previously used the
DAG within the match context. But they're now unused after #220527, so
this removes them. Since computeKnownBits is an expensive operation, any
combines in future that need to check the sign should likely call
computeKnownBits outside of the pattern match
Commit: a631bc15c5445e48124a06a884ecf4bf9ec491e2
https://github.com/llvm/llvm-project/commit/a631bc15c5445e48124a06a884ecf4bf9ec491e2
Author: Gaëtan Bossu <gaetan.bossu at arm.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/docs/LangRef.md
M llvm/include/llvm/CodeGen/ISDOpcodes.h
M llvm/include/llvm/IR/Intrinsics.td
M llvm/include/llvm/Target/TargetSelectionDAG.td
M llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
M llvm/lib/IR/Verifier.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.h
M llvm/lib/Target/AArch64/SVEInstrFormats.td
A llvm/test/CodeGen/AArch64/sve-vector-repeat.ll
A llvm/test/Verifier/vector-repeat-intrinsic-invalid.ll
A llvm/test/Verifier/vector-repeat-intrinsic-valid.ll
M llvm/unittests/CodeGen/SelectionDAGNodeConstructionTest.cpp
Log Message:
-----------
[IR][REVEC] Define llvm.vector.repeat intrinsic (#208212)
This intrinsic is used to repeat a <N x Ty> fixed-length vector `vscale`
times to form a <vscale x N x Ty> scalable vector. The patch adds
legalisation support and ISel for AArch64.
This intrinsic is required to support re-vectorisation of fixed-length
vectors to scalable ones, as shufflevector instructions do not support
scalable vectors. Re-vectorisation was discussed in this RFC:
https://discourse.llvm.org/t/rfc-re-vectorisation-to-wider-vectors-in-loopvectorizer/91071
Assisted-by: codex (tests)
Commit: 22312472de3ef8b4c5318da0b527510c5d498ae9
https://github.com/llvm/llvm-project/commit/22312472de3ef8b4c5318da0b527510c5d498ae9
Author: Timur Baidusenov <timurbaidusenov at gmail.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/docs/LangRef.md
M llvm/lib/IR/Verifier.cpp
M llvm/test/Transforms/MemCpyOpt/vscale-crashes.ll
A llvm/test/Verifier/byval-scalable.ll
Log Message:
-----------
[IR] Reject a scalable byval argument in the verifier (#226170)
A byval argument is copied into the caller's frame, and the current
implementation needs the size of that copy at compile time, which a
scalable type does not have. Plain `llc` fails on such IR today, and
SafeStack crashed on it in #182759. Nothing in the tree produces it and
no target needs it yet, so rather than teach SafeStack to step around it
(#225067), disallow it in the LangRef and reject it in the verifier
until the necessary support exists. `isScalableTy()` also covers a
struct with a scalable member.
Fixes #182759.
Commit: ffcb13aadde867aca18819f8716972afaccf124f
https://github.com/llvm/llvm-project/commit/ffcb13aadde867aca18819f8716972afaccf124f
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/include/llvm/ExecutionEngine/Orc/JITTargetMachineBuilder.h
M llvm/lib/ExecutionEngine/Orc/JITTargetMachineBuilder.cpp
Log Message:
-----------
Orc: Move getDefaultDataLayoutForTarget out of line (#226416)
Try to fix link errors with shared library builds.
Commit: 3897817145ffa3204e2593cb0b26c535724221c2
https://github.com/llvm/llvm-project/commit/3897817145ffa3204e2593cb0b26c535724221c2
Author: Gaëtan Bossu <gaetan.bossu at arm.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/test/Analysis/CostModel/AArch64/masked_ldst.ll
M llvm/test/Analysis/CostModel/AArch64/sve-arith.ll
M llvm/test/Analysis/CostModel/AArch64/sve-ldst.ll
M llvm/test/CodeGen/AArch64/sve-int-arith.ll
M llvm/test/Transforms/LoopVectorize/AArch64/force-scalable-vectorization-always.ll
M llvm/test/Transforms/LoopVectorize/AArch64/invalid-costs.ll
M llvm/test/Transforms/LoopVectorize/AArch64/scalable-alloca.ll
M llvm/test/Transforms/LoopVectorize/AArch64/scalable-call.ll
M llvm/test/Transforms/LoopVectorize/AArch64/scalable-vectorization-cost-tuning.ll
Log Message:
-----------
[AArch64][CostModel] Consider some nxv1 operations as legal (#214471)
This is allowing some operations on vscale x 1 types, namely:
- load/store
- masked load/store
- arithmetic instructions like add/sub/mul
For those, there is already codegen coverage. See e.g.
- llvm/test/CodeGen/AArch64/sve-int-arith.ll
- llvm/test/CodeGen/AArch64/sve-load-store-legalisation.ll
- llvm/test/CodeGen/AArch64/sve-masked-gather.ll
- llvm/test/CodeGen/AArch64/sve-masked-scatter.ll
These types are relevant for enabling REVEC in LoopVectorizer. For
AArch64, the main target there is turning NEON vector sizes into SVE
vector size, i.e. using VF = "vscale x 1". For loops with mixed vector
and scalar types, we'll want to allow vectorising scalar types with such
a VF.
Commit: 55b498466a7b2620d09fcdf1b2300f71a35f6d8b
https://github.com/llvm/llvm-project/commit/55b498466a7b2620d09fcdf1b2300f71a35f6d8b
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M clang/lib/AST/ByteCode/ByteCodeEmitter.h
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ByteCode/Context.cpp
M clang/lib/AST/ByteCode/Disasm.cpp
M clang/lib/AST/ByteCode/EvalEmitter.cpp
M clang/lib/AST/ByteCode/EvalEmitter.h
M clang/lib/AST/ByteCode/EvaluationResult.cpp
M clang/lib/AST/ByteCode/EvaluationResult.h
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/InterpBuiltinObjectSize.cpp
M clang/lib/AST/ByteCode/Pointer.cpp
M clang/lib/AST/ByteCode/Pointer.h
M clang/lib/AST/ExprConstShared.h
M clang/lib/AST/ExprConstant.cpp
M clang/test/AST/ByteCode/builtin-functions.cpp
M clang/test/AST/ByteCode/codegen-constexpr-unknown.cpp
M clang/test/AST/ByteCode/references.cpp
M clang/test/CodeGenCXX/global-init.cpp
M clang/test/SemaCXX/PR19955.cpp
M clang/test/SemaCXX/cxx2c-expansion-stmts.cpp
Log Message:
-----------
[clang][bytecode] Stop relying on `CheckEvaluationResult()` (#186045)
We already have to do a lot of check in `EvaluationResult` ourselves, only to redo some of them on the `APValue` we create. Just do all the checks before creating the `APValue` in the first place.
Commit: 76c1ac4608e9cabf9e27e95094f7cd11dcc8ebcb
https://github.com/llvm/llvm-project/commit/76c1ac4608e9cabf9e27e95094f7cd11dcc8ebcb
Author: forking-google-bazel-bot[bot] <265904573+forking-google-bazel-bot[bot]@users.noreply.github.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
Log Message:
-----------
[Bazel] Fixes 0a0e0fa (#226400)
This fixes 0a0e0fa181cf162bcc93be85abf2b1b911027e73 (#224644).
Buildkite error link:
https://buildkite.com/llvm-project/upstream-bazel/builds?commit=0a0e0fa181cf162bcc93be85abf2b1b911027e73
Co-authored-by: Google Bazel Bot <google-bazel-bot at google.com>
Commit: e34e31190233a5733d6b7751160a29e50cd8b41c
https://github.com/llvm/llvm-project/commit/e34e31190233a5733d6b7751160a29e50cd8b41c
Author: Akash Manna <akash.manna.mymail at gmail.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M clang/docs/ReleaseNotes.md
M clang/lib/CodeGen/CGStmtOpenMP.cpp
A clang/test/OpenMP/target_map_address_space_codegen.c
Log Message:
-----------
[clang][OpenMP] Cast by-reference captures to the address space of the captured field (#226229)
Fixes #140069
Sema strips all qualifiers, including the address space, from the type
of a variable captured by an OpenMP region, so the outlined function for
a `target` region takes `int __seg_gs a;` as a plain `int &`, i.e. a
pointer in the default address space. That is the intended model: inside
the region the variable is an ordinary object, and the host's segment
address space means nothing on a device. `GenerateOpenMPCapturedVars`
ignored the captured field's type for by-reference captures though, and
passed the variable's own address. With `map(alloc: a)` that is a `ptr
addrspace(256)` argument for a `ptr` parameter, and emitting the host
fallback call tripped the "Calling a function with a bad signature"
assertion. The same call is emitted on the `omp_offload.failed` path
when offloading targets are given, so this wasn't limited to host-only
compiles.
By-reference captures now convert the address to the type of the
captured field, adding an `addrspacecast` only when the address spaces
differ. On x86 the cast doesn't change the pointer value, so the region
gets the linear address of the object, which is also what the mapping
passes to the runtime and what GCC does for the same code. Captures
whose address already has the right type are untouched.
Commit: c6c8f3006f378079cf2c89e4e4bddc0adb15f8ea
https://github.com/llvm/llvm-project/commit/c6c8f3006f378079cf2c89e4e4bddc0adb15f8ea
Author: Walter Lee <49250218+googlewalt at users.noreply.github.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
Log Message:
-----------
Fix Bazel build for aa6b03e (#226426)
Buildkite error link:
https://buildkite.com/llvm-project/upstream-bazel/builds?commit=aa6b03ed5a9ffe5ba6f0d945fac9961884b5c6ed
Co-authored-by: Google Bazel Bot <google-bazel-bot at google.com>
Commit: b7c4b2171d5f4e902dad4b207625bc08c45e8cbf
https://github.com/llvm/llvm-project/commit/b7c4b2171d5f4e902dad4b207625bc08c45e8cbf
Author: Tomas Matheson <Tomas.Matheson at arm.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/Transforms/IPO/AttributorAttributes.cpp
A llvm/test/Transforms/Attributor/callback-noalias.ll
M llvm/test/Transforms/Attributor/callbacks.ll
M llvm/test/Transforms/OpenMP/parallel_deletion.ll
Log Message:
-----------
[Attributor] Check callback broker argument aliases correctly (#218672)
Fix a bug in AANoAliasCallSiteArgument. AbstractCallSite uses separate
callback argument and broker operand numbers. Example:
```llvm
call void @broker(
ptr @callee, # broker arg 0
ptr %slot, # broker arg 1
ptr %slot # broker arg 2
) !callback !0
define internal void @callee(
ptr align 8 dereferenceable(8) %a, # callback arg 0
ptr align 8 dereferenceable(8) %b # callback arg 1
) {
```
In `mayAliasWithArgument`, `OtherArgNo` is the broker (call-site) arg
number (0, 1 or 2), so it should be compared against
`getCallSiteArgNo()` not `getCalleeArgNo()`. Otherwise it will compare
the argument with itself, and skip some comparisons with other args, and
wrongly infer/fail to infer `noalias`.
Commit: 02f6eaf60dcc3794ed563c0d3953de2d029f024f
https://github.com/llvm/llvm-project/commit/02f6eaf60dcc3794ed563c0d3953de2d029f024f
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/X86/extracted-subfields.ll
Log Message:
-----------
[SLP]Extract vectorized source of gathered sub-fields
The bitcast emitted for gathered sub-fields used the source scalar
directly, even if it was vectorized and erased, causes the crash,
register the bitcast as an external user of the vectorized source.
Fixes the crash reported in #224919.
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/226437
Commit: a98f7ed68ea1cbe43a6786a68c3f9f2e1b9cceb7
https://github.com/llvm/llvm-project/commit/a98f7ed68ea1cbe43a6786a68c3f9f2e1b9cceb7
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp
M llvm/test/CodeGen/AMDGPU/si-init-whole-wave.mir
Log Message:
-----------
AMDGPU: Mark SCC def dead in init exec lowering (#226373)
Co-authored-by: Claude Opus 5 <noreply at anthropic.com>
Commit: a8250aacd1436752d3862005155e611da512710e
https://github.com/llvm/llvm-project/commit/a8250aacd1436752d3862005155e611da512710e
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_mul_one.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_pixelshader.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_raw_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_struct_buffer.ll
M llvm/test/CodeGen/AMDGPU/insert_waitcnt_for_precise_memory.ll
Log Message:
-----------
AMDGPU: Mark SCC def dead in wave reduction expansions (#226370)
Co-authored-by: Claude Opus 5 <noreply at anthropic.com>
Commit: 0ebe3a65e87819ff5068f21fb5a6615b3d580e64
https://github.com/llvm/llvm-project/commit/0ebe3a65e87819ff5068f21fb5a6615b3d580e64
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/PhaseOrdering/X86/avg.ll
M llvm/test/Transforms/PhaseOrdering/X86/vector-reductions.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/abs-mul-buildvector-in-loop.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/div.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/fma-reduce-regression.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/gather-buildvector-with-minbitwidth-user.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/lcssa-phi-extract-scale.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/loop-accumulator-reduction.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/recalc-copyable-deps-on-reorder.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/splat-gather-subtree-cost.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/splat-gather-subtree-drop-schedule.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/splat-gather-subtree-drop.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/splat-gather-subtree-keep-drop.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/splat-gather-subtree-loop-extracts.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/splat-gather-subtree-reuse.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/splat-gather-subtree-satd.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/splat-gather-subtree-store-chain.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/buildvector-all-external-scalars.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/complex-loads.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/partial-vec-invalid-cost.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/reordered-buildvector-scalars.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/splat-gather-extracts.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/splat-gather-trim-combined.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/splat-gather-trim.ll
M llvm/test/Transforms/SLPVectorizer/X86/deleted-instructions-clear.ll
M llvm/test/Transforms/SLPVectorizer/X86/div-possibly-extended-with-poisons.ll
M llvm/test/Transforms/SLPVectorizer/X86/external-bin-op-user.ll
M llvm/test/Transforms/SLPVectorizer/X86/gathered-loads-non-full-reg.ll
M llvm/test/Transforms/SLPVectorizer/X86/lookahead.ll
M llvm/test/Transforms/SLPVectorizer/X86/original-inst-scheduled-after-copyable.ll
M llvm/test/Transforms/SLPVectorizer/X86/reassoc-copyable-in-another-entry.ll
M llvm/test/Transforms/SLPVectorizer/X86/reassoc-flattened-copyable-operand.ll
M llvm/test/Transforms/SLPVectorizer/X86/reorder_phi.ll
M llvm/test/Transforms/SLPVectorizer/X86/select-copyable-cmp-poison.ll
M llvm/test/Transforms/SLPVectorizer/X86/split-node-reorder-node-with-ops.ll
M llvm/test/Transforms/SLPVectorizer/X86/subvector-minbitwidth-unsigned-value.ll
M llvm/test/Transforms/SLPVectorizer/X86/trimmed-subtree-schedule.ll
Log Message:
-----------
[SLP]Cancel scheduling of the trimmed nodes
The nodes, trimmed during throttling, are not vectorized, but their
bundles were still scheduled by the final scheduling.
Cancel these bundles before the final scheduling, recalculate the
dependencies and schedule their scalars as separate instructions, so
they keep their original order and stay close to their users, which
helps instructions scheduler and save some time for bundles scheduling.
Assisted-by: Cursor
Reviewers: bababuck, RKSimon
Pull Request: https://github.com/llvm/llvm-project/pull/226268
Commit: 57e112ccb2a509c0e1d36963b187fccdd59566de
https://github.com/llvm/llvm-project/commit/57e112ccb2a509c0e1d36963b187fccdd59566de
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/IR/RuntimeLibcalls.cpp
A llvm/test/Transforms/Util/DeclareRuntimeLibcalls/divmod.ll
Log Message:
-----------
RuntimeLibcalls: Describe register-returning divmod libcall ABIs (#217825)
Teach RuntimeLibcallsInfo::getFunctionTy about the ARM AEABI
(__aeabi_*divmod) and Windows (__rt_*div*) divmod signatures. Currently
the custom lowering to these calls hardcodes the call signature
information, but in the future this should be automatically handled.
Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
Commit: 2fe83ee7dc5bb40e2f15e164c21a01bec01c1792
https://github.com/llvm/llvm-project/commit/2fe83ee7dc5bb40e2f15e164c21a01bec01c1792
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/Target/SystemZ/SystemZFrameLowering.cpp
M llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
M llvm/test/CodeGen/SystemZ/atomicrmw-fadd-04.ll
M llvm/test/CodeGen/SystemZ/cmpxchg-01.ll
M llvm/test/CodeGen/SystemZ/cmpxchg-02.ll
A llvm/test/CodeGen/SystemZ/dead-cc-defs.ll
Log Message:
-----------
SystemZ: Mark unread CC defs dead at build time (#226434)
The custom inserters for the subword atomic pseudos and for probed
allocas, plus the inline stack probe emitted by frame lowering, build
instructions whose CC def is never read. Set the dead flags.
Marking the RISBG32 in the subword cmpxchg loop dead lets MachineSink
move it out of the compare block and into the store block, so it is
skipped when the comparison fails.
Co-authored-by: Claude Opus 5 <noreply at anthropic.com>
Commit: 4e50049d9d5b44028c9cca9763f6ceeda1c667fb
https://github.com/llvm/llvm-project/commit/4e50049d9d5b44028c9cca9763f6ceeda1c667fb
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-phis-no-lane-mask-merging.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-used-outside-loop.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-structurizer.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-i1.ll
M llvm/test/CodeGen/AMDGPU/block-should-not-be-in-alive-blocks.mir
M llvm/test/CodeGen/AMDGPU/branch-folding-implicit-def-subreg.ll
M llvm/test/CodeGen/AMDGPU/collapse-endcf.mir
M llvm/test/CodeGen/AMDGPU/divergent-branch-uniform-condition.ll
M llvm/test/CodeGen/AMDGPU/i1-copy-from-loop.ll
M llvm/test/CodeGen/AMDGPU/insert-waitcnts-merge.ll
M llvm/test/CodeGen/AMDGPU/loop_break.ll
M llvm/test/CodeGen/AMDGPU/lower-control-flow-live-intervals.mir
M llvm/test/CodeGen/AMDGPU/lower-control-flow-live-variables-update.mir
M llvm/test/CodeGen/AMDGPU/lower-control-flow-other-terminators.mir
M llvm/test/CodeGen/AMDGPU/sgpr-scavenge-fi-stack-id.ll
M llvm/test/CodeGen/AMDGPU/si-lower-control-flow-remove-redundant-block-liveintervals.mir
M llvm/test/CodeGen/AMDGPU/si-lower-control-flow.mir
M llvm/test/CodeGen/AMDGPU/transform-block-with-return-to-epilog.ll
Log Message:
-----------
AMDGPU: Mark the SCC def dead when expanding CF pseudos (#226249)
The control flow pseudos start with dead flags on the implicit scc def,
but did not transfer to the replacement instruction
Co-Authored-By: Claude Opus 5 <noreply at anthropic.com>
Commit: 319529bbe0ef99a5262fef91317e1327fa1e8453
https://github.com/llvm/llvm-project/commit/319529bbe0ef99a5262fef91317e1327fa1e8453
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/test/CodeGen/AMDGPU/add_sub_u64_pseudos.mir
Log Message:
-----------
AMDGPU: Mark the SCC def dead when expanding 64-bit scalar add/sub (#226269)
Co-authored-by: Claude Opus 5 <noreply at anthropic.com>
Commit: 01b8b4dfc99e46273b9811cb4663a90c2fb61676
https://github.com/llvm/llvm-project/commit/01b8b4dfc99e46273b9811cb4663a90c2fb61676
Author: Gaëtan Bossu <gaetan.bossu at arm.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
Log Message:
-----------
[AArch64] Remove variable only used in assert (#226433)
This caused a buildbot failure after the variable was introduced in #208212
Commit: 0e7fb8bcf11a59d564bf45d0568d528bf1e9bdcf
https://github.com/llvm/llvm-project/commit/0e7fb8bcf11a59d564bf45d0568d528bf1e9bdcf
Author: Dhairyashil R G <dhairyashil25 at gmail.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M mlir/include/mlir/Dialect/Vector/Transforms/VectorTransforms.h
M mlir/lib/Dialect/Vector/Transforms/VectorMaskElimination.cpp
M mlir/test/Dialect/Vector/eliminate-masks.mlir
M mlir/test/lib/Dialect/Vector/TestVectorTransforms.cpp
Log Message:
-----------
[mlir][vector] Support fixed-size masks in `eliminateVectorMasks` (#221595)
`eliminateVectorMasks` returned immediately unless a `VscaleRange` was
supplied. The TODO above that early return argued the fixed-size case
was unlikely to be useful, because "for fixed-size code dimensions are
all static so masks tend to fold away".
That is only true when the mask operand is constant. When it comes from
an induction variable, which is what tiling produces, the operand is not
constant and no fold removes the mask, even though value-bounds analysis
can prove it all-true. For example, `-canonicalize` leaves this alone:
```mlir
scf.for %i = %c0 to %c1024 step %c4 {
%rem = arith.subi %c1024, %i : index
%mask = vector.create_mask %rem : vector<4xi1>
%v = vector.transfer_read %t[%i], %f0, %mask : tensor<1024xf32>, vector<4xf32>
...
}
```
`%i <= 1020`, so `%rem >= 4` and the mask is all-true.
The algorithm was never scalable-specific; only the bound query was.
This makes `vscaleRange` genuinely optional: without one, the lower
bound is computed with `ValueBoundsConstraintSet::computeConstantBound`
and compared against the mask dimension. Scalable dimensions still need
a range and bail without one, so a fixed-size caller cannot prove a
dimension whose runtime size is `vscale` times the size in the type. The
scalable path is unchanged, and the existing test still passes with its
RUN line untouched.
### Behaviour change for downstream callers
An omitted `vscaleRange` used to make the call a no-op. It now runs the
fixed-size analysis.
No in-tree caller relies on the old meaning, but IREE does call this
unconditionally in `Codegen/Common/GenericVectorization.cpp`, passing
`getDefaultVscaleRange()`, which returns `std::nullopt` for every target
other than AArch64+SVE. For those targets this patch turns a no-op into
live mask elimination. That is the intended benefit, but it is worth
knowing before the next integrate. The added cost is bounded: constant
and `vscale`-multiple operands short-circuit before any analysis, so
only `create_mask` ops with unknown operands pay for a bound query.
### Tests
New `eliminate-masks-fixed-size.mlir`, run through a `fixed-size` option
added to the test pass: two cases that are eliminated (the tiled loop
above, and a dynamic operand bounded by `arith.maxsi`) and three that
are not (an unbounded operand, a lower bound smaller than the mask
dimension, and a scalable dimension with no vscale range). Each negative
was checked to fail for the stated reason, by making the smallest change
that flips it.
Context:
https://discourse.llvm.org/t/rfc-should-vector-transfer-read-write-keep-in-bounds-measurements-on-the-masking-alternative/91649
Assisted-by: Claude
Commit: 675c1cfa5d925232db882942674a40de41654bc5
https://github.com/llvm/llvm-project/commit/675c1cfa5d925232db882942674a40de41654bc5
Author: Paul Walker <paul.walker at arm.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64PTrueCoalescing.cpp
M llvm/test/CodeGen/AArch64/insert-subvector-res-legalization.ll
M llvm/test/CodeGen/AArch64/llvm-ir-to-intrinsic.ll
M llvm/test/CodeGen/AArch64/masked-srem-scalable.ll
M llvm/test/CodeGen/AArch64/masked-urem-scalable.ll
M llvm/test/CodeGen/AArch64/sve-bf16-combines.ll
M llvm/test/CodeGen/AArch64/sve-bf16-int-converts.ll
M llvm/test/CodeGen/AArch64/sve-bitcast.ll
M llvm/test/CodeGen/AArch64/sve-fpext-load.ll
M llvm/test/CodeGen/AArch64/sve-ld1-addressing-mode-reg-imm.ll
M llvm/test/CodeGen/AArch64/sve-load-store-legalisation.ll
M llvm/test/CodeGen/AArch64/sve-lsrchain.ll
M llvm/test/CodeGen/AArch64/sve-partial-reduce-dot-product.ll
M llvm/test/CodeGen/AArch64/sve-partial-reduce-wide-add.ll
M llvm/test/CodeGen/AArch64/sve-pred-selectop2.ll
M llvm/test/CodeGen/AArch64/sve-shift-trunc-combine.ll
M llvm/test/CodeGen/AArch64/sve-st1-addressing-mode-reg-imm.ll
M llvm/test/CodeGen/AArch64/vec-combine-compare-to-bitmask.ll
M llvm/test/CodeGen/AArch64/vector-absolute-difference.ll
M llvm/test/Transforms/LoopStrengthReduce/AArch64/vscale-fixups.ll
Log Message:
-----------
[LLVM][CodeGen] Enable the AArch64PTrueCoalescing pass. (#225830)
Fixes https://github.com/llvm/llvm-project/issues/137040
Commit: 68a9cd31fd277f9f6b8a8ab95e18d00a786e7c12
https://github.com/llvm/llvm-project/commit/68a9cd31fd277f9f6b8a8ab95e18d00a786e7c12
Author: Timur Baidusenov <timurbaidusenov at gmail.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M polly/lib/Analysis/ScopBuilder.cpp
A polly/test/ScopInfo/user-assumption-cached-precondition.ll
Log Message:
-----------
[Polly] Detect preconditions of cached user assumption translations (#226204)
`addUserAssumptions` detected preconditions of a user assumption by
checking whether building its condition recorded new assumptions, but
`SCEVAffinator` caches translated expressions, so a precondition shared
with an earlier assumption (e.g. the same truncation) was missed and the
assumption went into the context, removing the runtime check it relied
on. For example, with `__builtin_assume((signed char)n >= 0)` and
`__builtin_assume((signed char)n < 10)`, the `n >= 128` check was
dropped, although `n = 261` satisfies both assumptions. Instead, check
the invalid domain of each assumption, which is also cached, and if it
is non-empty, add the assumption to the defined behavior context as in
#189350.
Assisted-by: Claude (Anthropic)
Commit: 940105295f88426cb85b01b075f44f36a90c12fd
https://github.com/llvm/llvm-project/commit/940105295f88426cb85b01b075f44f36a90c12fd
Author: Sergey Semenov <sergey.semenov at intel.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M .github/workflows/sycl-tests.yml
Log Message:
-----------
[CI][libsycl] Enable -Werror in libsycl precommit testing (#226129)
Commit: 952fa726ae35661f86ea92ed989d0efa36e69c7f
https://github.com/llvm/llvm-project/commit/952fa726ae35661f86ea92ed989d0efa36e69c7f
Author: Andrzej Warzyński <andrzej.warzynski at arm.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
R clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_len.c
M clang/test/CodeGen/AArch64/sve/len.c
Log Message:
-----------
[clang][AArch64] Consolidate codegen tests for SVE's LEN intrinsics (#226131)
This patch completes the migration of the tests from:
* clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_len.c
to:
* clang/test/CodeGen/AArch64/sve/len.c
`len.c` covers all the cases previously tested by `acle_sve_len.c`.
However, unlike `acle_sve_dup.c`, it was only tested as C. Add `-x c++`
RUN lines to provide the equivalent C++ coverage, including lowering
via CIR.
Commit: f1c5f1e98cac5bf9d688272f2137da992ab005da
https://github.com/llvm/llvm-project/commit/f1c5f1e98cac5bf9d688272f2137da992ab005da
Author: Lang Hames <lhames at gmail.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M orc-rt/include/orc-rt/bedrock/BootstrapInfo.h
M orc-rt/lib/bedrock/BootstrapInfo.cpp
Log Message:
-----------
[orc-rt] Make BootstrapInfo construction noexcept. (#226459)
These methods should never throw.
Commit: df26d549b9115ff7c32b6fb9031250994d0f3515
https://github.com/llvm/llvm-project/commit/df26d549b9115ff7c32b6fb9031250994d0f3515
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/lib/Target/ARM/ARMISelLowering.cpp
Log Message:
-----------
ARM: Use divmod type signatures from RuntimeLibcallsInfo (#217869)
Start moving towards an API to emit calls from RuntimeLibcallsInfo's
knowledge about the type signature of a function instead of manually
computing an IR type from the EVT of the operation.
Also change the swap of arguments to be based on the libcall impl,
rather than the ABI since it's logically a property of the function
itself.
Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
Commit: dcdeeebef2ef008326211b661cfb81d1d35b4086
https://github.com/llvm/llvm-project/commit/dcdeeebef2ef008326211b661cfb81d1d35b4086
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/test/CodeGen/LoongArch/pr177863.ll
A llvm/test/CodeGen/X86/vec_setcc-3.ll
Log Message:
-----------
[DAG] SimplifySetCC - adjust setcc result type when peeking through truncates (#226422)
For the "(setcc (trunc x) (trunc y)) -> (setcc x y)" fold with non vXi1
cmp result type, make sure we adjust the type and then trunc/extend it
correctly using BooleanContent.
Fixes #226365
Commit: a509a4e98a50a2acc172a5f6eba77b8df020e3cd
https://github.com/llvm/llvm-project/commit/a509a4e98a50a2acc172a5f6eba77b8df020e3cd
Author: Benedek Kaibas <82393336+benedekaibas at users.noreply.github.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M clang/docs/LifetimeSafety.md
M clang/docs/ReleaseNotes.md
M clang/include/clang/Basic/LangOptions.def
M clang/include/clang/Options/Options.td
M clang/lib/Driver/ToolChains/Clang.cpp
A clang/test/Driver/flifetime-safety-c.c
M clang/test/Sema/LifetimeSafety/annotation-suggestions-fixits.c
M clang/test/Sema/LifetimeSafety/safety-c.c
Log Message:
-----------
[LifetimeSafety] Enable C support by default under -Wlifetime-safety (#224028)
This PR extends the lifetime safety analysis to C. When the analysis is
enabled with `-Wlifetime-safety`, it now also runs on C code without the
extra `-fexperimental-lifetime-safety-c` flag.
I have renamed `-fexperimental-lifetime-safety-c` to
`-flifetime-safety-c` since it is on by default from now on. The
`-fno-lifetime-safety-c` flag disables the analysis for C. I have
updated the documentation and the release notes and rewrote the RUN
lines of the test cases that used the old flag.
Commit: b60afea0d31f4da34b9d867a00817a0e53dbdb05
https://github.com/llvm/llvm-project/commit/b60afea0d31f4da34b9d867a00817a0e53dbdb05
Author: Akash Manna <akash.manna.mymail at gmail.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Utils/SimplifyCFG.cpp
A llvm/test/Transforms/SimplifyCFG/fold-branch-to-common-dest-call-debugloc.ll
Log Message:
-----------
[SimplifyCFG] Keep a debug location on calls cloned by `FoldBranchToCommonDest` (#224247)
Fixes #220848
When folding a branch to a common destination, SimplifyCFG clones the
bonus instructions into the predecessor and resets their debug
locations, so the debugger doesn't step onto code from a branch that
wasn't taken. It did that with `setDebugLoc(DebugLoc::getDropped())` for
every instruction. That's fine for an `icmp`, but with
`-bonus-inst-threshold=2` a `speculatable` call can be a bonus
instruction too, and an inlinable call in a function with debug info
must have a `!dbg` location, otherwise the inliner can't set up the
inlined-at scope. The verifier rejects the module with "inlinable
function call in a function with debug info must have a !dbg location".
The clone now uses `Instruction::dropLocation()`, which is what
`speculativelyExecuteBB` in the same file already does. Non-call
instructions still lose their location as before, while calls get a line
0 location in the function's scope, so nothing misleading shows up when
stepping and the IR stays valid. `dropLocation()` needs the parent
function, so the clone is inserted into the predecessor before its
location is updated. An earlier attempt at this swap (674f57870f4c) was
reverted after buildbot crashes; the clone was still unparented when
`dropLocation()` ran there, which would explain them.
Commit: eae3e9e64de82ae5a162783808c89521cfea7742
https://github.com/llvm/llvm-project/commit/eae3e9e64de82ae5a162783808c89521cfea7742
Author: Lang Hames <lhames at gmail.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M orc-rt/include/orc-rt/support/move_only_function.h
M orc-rt/test/unit/support/move_only_function-test.cpp
Log Message:
-----------
[orc-rt] Fix move_only_function storing references to lvalue callables. (#226474)
move_only_function's converting constructor instantiated CallableImpl
with the deduced forwarding-reference type, so constructing from an
lvalue callable stored a reference to it rather than a copy, leaving the
move_only_function dangling once the original went out of scope.
This commit decays the callable type before instantiating CallableImpl,
and adds a static_assert to CallableImpl to enforce that it's only
instantiated with decayed types.
Commit: 176a24691b1b315cfd0f15ee8bb8adcc086683be
https://github.com/llvm/llvm-project/commit/176a24691b1b315cfd0f15ee8bb8adcc086683be
Author: George Burgess IV <george.burgess.iv at gmail.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M clang/docs/SourceBasedCodeCoverage.md
M compiler-rt/include/profile/instr_prof_interface.h
M compiler-rt/lib/profile/InstrProfiling.h
M compiler-rt/test/profile/instrprof-api.c
Log Message:
-----------
[docs][clang] Document additional public profile runtime APIs (#224424)
Android's code coverage runtime started using these functions recently,
and I noticed they were undocumented (and the reviewer highlighted
that `instr_prof_interface.h` exists).
So this commit:
- Moves their declarations to that header
- Updates `SourceBasedCodeCoverage.md` to highlight that header
- Adds quips to said `.md` file for these functions
An LLM was used to take a first pass at this; I reviewed and refined.
Commit: 8de4cb45931adab063265b565408ff2b72be668d
https://github.com/llvm/llvm-project/commit/8de4cb45931adab063265b565408ff2b72be668d
Author: Lang Hames <lhames at gmail.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M orc-rt/test/unit/support/move_only_function-test.cpp
Log Message:
-----------
[orc-rt] Tighten move_only_function ShouldCopyInitialize test. (#226483)
ShouldCopyInitialize only checked that constructing a move_only_function
from an lvalue didn't move the callable, so it passed when the callable
was held by reference and never copied at all.
This commit replaces the moved flag with copy and move counters, and
checks that construction performs exactly one copy and no moves.
Commit: 83589c854329a8366672f9932ee27b422902038f
https://github.com/llvm/llvm-project/commit/83589c854329a8366672f9932ee27b422902038f
Author: google-yfyang <yfyang at google.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
Log Message:
-----------
Fix Bazel build for 0a0e0fa (#226489)
Buildkite error link:
https://buildkite.com/llvm-project/upstream-bazel/builds?commit=0a0e0fa181cf162bcc93be85abf2b1b911027e73
Co-authored-by: Google Bazel Bot <google-bazel-bot at google.com>
Commit: 84d75c8ab6eb610cde0048458f96085f923fc392
https://github.com/llvm/llvm-project/commit/84d75c8ab6eb610cde0048458f96085f923fc392
Author: Nico Weber <thakis at chromium.org>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/TargetParser/AArch64TargetParser.cpp
Log Message:
-----------
[AArch64] Make compiling arm_neon.h faster (#226378)
Replace two linear scans with map lookups.
On my system, reduces time to compile a TU that does nothing but
`#include <arm_neon.h>` from 92.0 ms ± 1.4 ms to 70.9 ms ± 1.3 ms.
No behavior change.
Commit: f2f70fc15fca532f4968ba211e430e269dd18489
https://github.com/llvm/llvm-project/commit/f2f70fc15fca532f4968ba211e430e269dd18489
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
A llvm/test/tools/llubi/main_declaration.ll
M llvm/tools/llubi/llubi.cpp
Log Message:
-----------
[llubi] Error if main is not a definition (#226475)
Currently this crashes. Ran into this while using llubi with
llvm-reduce.
Commit: 2dc2a1f1b94f1953f0ef52bd748fb1f0c07cd780
https://github.com/llvm/llvm-project/commit/2dc2a1f1b94f1953f0ef52bd748fb1f0c07cd780
Author: Anonmiraj <ezzibrahimx at gmail.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M libc/src/__support/math/lgammaf.h
Log Message:
-----------
[libc][math] Fix lgammaf 1-ULP errors in non-FMA builds (#225449)
There were some inaccuracies in the non-FMA builds.
I retested exhaustively with FMA both enabled and disabled, and all
tests seems to pass noww.
Commit: e1dc804fcc352b841e798efe0aa4a6c40ba1f2b3
https://github.com/llvm/llvm-project/commit/e1dc804fcc352b841e798efe0aa4a6c40ba1f2b3
Author: Nico Weber <thakis at chromium.org>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/test/tools/llvm-objdump/MachO/AArch64/macho-arm64-subtypes.test
M llvm/test/tools/llvm-objdump/MachO/universal-arm64.test
Log Message:
-----------
Add more llvm-objdump test coverage for arm64e.x1 (#224110)
Commit: 6ad85f11c5151f18a3686322e37f8e64a48be327
https://github.com/llvm/llvm-project/commit/6ad85f11c5151f18a3686322e37f8e64a48be327
Author: Timur Baidusenov <timurbaidusenov at gmail.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M polly/lib/Analysis/ScopBuilder.cpp
M polly/test/ScopInfo/issue190128.ll
M polly/test/ScopInfo/simple_loop_unsigned.ll
A polly/test/ScopInfo/zext-loop-bound-unbounded.ll
Log Message:
-----------
[Polly] Do not assume loops to be bounded if latch conditions are invalid (#226202)
If a loop with an `<nsw>` induction variable appears to be unbounded for
some parameter values, `addLoopBoundsToHeaderDomain` removes them from
its domain without a runtime check, but the loop may only appear
unbounded because its latch condition is modeled incorrectly for these
values, e.g. `(zext i16 %n to i64)` is modeled as `n` under the
assumption `n >= 0`. Removing them also dropped that assumption, so for
`n < 0` the loop was not executed at all instead of running `65536 + n`
iterations. Exclude the parameter values for which the latch conditions
are invalid by a runtime check instead.
Fixes #192616 and #192618.
Assisted-by: Claude (Anthropic)
Commit: 9de286c070e3f3176e7bbfb79d3c4d95807e19a5
https://github.com/llvm/llvm-project/commit/9de286c070e3f3176e7bbfb79d3c4d95807e19a5
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M flang/lib/Semantics/check-omp-structure.cpp
M flang/lib/Semantics/check-omp-structure.h
M flang/lib/Semantics/check-omp-syntax.cpp
M flang/lib/Semantics/check-omp-variant.cpp
Log Message:
-----------
[flang][OpenMP] Rename some symbols in check-omp-syntax.cpp (#226484)
Some function names did not conform to the naming convention. Include a
couple of other non-significant changes.
Commit: ff5f397d6cd06d0eb72f798b4454d490050fb442
https://github.com/llvm/llvm-project/commit/ff5f397d6cd06d0eb72f798b4454d490050fb442
Author: Lei Zhang <antiagainst at gmail.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUMachineFunctionInfo.cpp
A llvm/test/CodeGen/AMDGPU/lds-dynamic-direct-and-indirect-use.ll
Log Message:
-----------
[AMDGPU] Fix dynamic LDS consistency check in setDynLDSAlign (#225825)
5bf967cb132b ("[RFC][AMDGPU] Add BARRIER address space") changed the
absolute-address check in `setDynLDSAlign` to read the dynamic LDS
global being lowered (`GV`) instead of the kernel's representative
`llvm.amdgcn.<kernel>.dynlds` variable (`Dyn`).
`amdgpu-lower-module-lds` attaches `!absolute_symbol` only to the
representative; uses of the original dynamic LDS global inside the
kernel are left in place and never carry that metadata. As a result, a
kernel that accesses dynamic LDS both directly and through a non-inlined
callee now aborts with "Inconsistent metadata on dynamic LDS variable".
Commit: a514ce406f06bfbebeb5d8d9bc76e9cc5ec6a92b
https://github.com/llvm/llvm-project/commit/a514ce406f06bfbebeb5d8d9bc76e9cc5ec6a92b
Author: Nico Weber <thakis at chromium.org>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/utils/gn/secondary/clang/tools/driver/BUILD.gn
Log Message:
-----------
[gn] Add clang_static_plugin_sources to link out-of-tree plugins into clang (#226381)
This is useful for testing and profiling e.g. Chromium's clang plugins
without having to export symbols from the clang binary.
# args.gn
clang_static_plugin_sources = [
"/path/to/chromium/src/tools/clang/plugins/FindBadConstructsAction.cpp",
...
]
clang_static_plugin_include_dirs = [ "/path/to/chromium/src" ]
...or put the above in a gni file and put just `import("plugins.gni")`
in args.gn
No behavior change if the list is empty (the default).
Commit: 1978a469493fec319cd61e2eac42abade837fafc
https://github.com/llvm/llvm-project/commit/1978a469493fec319cd61e2eac42abade837fafc
Author: Kazu Hirata <kazu at google.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M clang/lib/AST/ASTImporter.cpp
M clang/lib/CodeGen/CGBlocks.cpp
M clang/lib/Serialization/ASTWriterStmt.cpp
Log Message:
-----------
[clang] Migrate away from PointerUnion::dyn_cast (NFC) (#226390)
Note that PointerUnion::dyn_cast has been soft deprecated in
PointerUnion.h:
// FIXME: Replace the uses of is(), get() and dyn_cast() with
// isa<T>, cast<T> and the llvm::dyn_cast<T>
Literal migration would result in dyn_cast_if_present (see the
definition of PointerUnion::dyn_cast), but this patch uses dyn_cast on
ExprWithCleanups::CleanupObject because it is always nonnull.
Specifically, ExprWithCleanups::getObjects() is populated from a slice
of Sema::ExprCleanupObjects, which only receives nonnull pointers in
the following places:
- Sema::BuildCompoundLiteralExpr
- Sema::ActOnBlockStmtExpr
- Sema::BuildBlockForLambdaConversion
Assisted-by: Antigravity
Commit: 76d4a51fe990d5915c8b30587b09d57e45d533a2
https://github.com/llvm/llvm-project/commit/76d4a51fe990d5915c8b30587b09d57e45d533a2
Author: Kazu Hirata <kazu at google.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanHelpers.h
M llvm/lib/Transforms/Vectorize/VPlanValue.h
Log Message:
-----------
[Vectorize] Remove unused functions (NFC) (#226392)
BoUpSLP::TreeEntry::isOneOf:
The last caller was removed on April 1, 2025 in commit
0e3049c562ccdea288c3b1f3b3d1ce5992d284b0.
BoUpSLP::ScheduleCopyableData::verify:
Introduced on August 11, 2025 in commit
2d7b55a028139dde58a994a65895841190dfde96 without any callers.
HorizontalReduction::hasSameParent:
The last caller was removed on July 29, 2024 in commit
197f4a90519df308d9bfddcc931f7683a5ae9cb9.
VPBlockBase::getHierarchicalPredecessors:
The last caller was removed on May 24, 2025 in commit
dcef154b5caf6556e69bb18bbb0506d274aa474e.
VPIRFlags::isNonNeg:
The last caller was removed on July 1, 2025 in commit
6b3d2b629cc3805d483ec4522cc97e2540070ae1.
VPHistogramRecipe::getOpcode:
Introduced on September 27, 2024 in commit
6f1a8c2da278a04565877e277bc4d5b70055ac74 without any callers.
VPWidenInductionRecipe::setStepValue:
The last caller was removed on May 22, 2026 in commit
5c853423f4f9e7296b7596b7f3ccade481686bfd.
VPReductionPHIRecipe::isPartialReduction:
Introduced on November 26, 2025 in commit
071d1fb8beda4c0ec9ede0acab12a382f34758fe without any callers.
VPTransformState::reset:
The last callers were removed on May 3, 2026 in commit
efd429fdfb6f3f0a6991d9d08ab15ca89f27a7c3.
VPValue::hasDefiningRecipe:
The last caller was removed on June 28, 2026 in commit
7abad0faf4bfe1cb674d7fd362cc31edb1d0c460.
Assisted-by: Antigravity
Commit: 58e81dc9a3e25cc41ad26f7cf222dea2c4aa391b
https://github.com/llvm/llvm-project/commit/58e81dc9a3e25cc41ad26f7cf222dea2c4aa391b
Author: Luke Lau <luke at igalia.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/early_exit_costs.ll
M llvm/test/Transforms/LoopVectorize/AArch64/simple_early_exit.ll
M llvm/test/Transforms/LoopVectorize/AArch64/single-early-exit-interleave.ll
M llvm/test/Transforms/LoopVectorize/RISCV/early-exit-live-out.ll
M llvm/test/Transforms/LoopVectorize/RISCV/sink-to-early-exit.ll
M llvm/test/Transforms/LoopVectorize/VPlan/uncountable-early-exit-vplan.ll
M llvm/test/Transforms/LoopVectorize/dereferenceable-info-from-assumption-constant-size.ll
M llvm/test/Transforms/LoopVectorize/early-exit-calls.ll
M llvm/test/Transforms/LoopVectorize/early-exit-load-live-out.ll
M llvm/test/Transforms/LoopVectorize/early-exit-unary-ops.ll
M llvm/test/Transforms/LoopVectorize/multiple-early-exits.ll
M llvm/test/Transforms/LoopVectorize/predicated-early-exits-interleave.ll
M llvm/test/Transforms/LoopVectorize/predicated-multiple-exits.ll
M llvm/test/Transforms/LoopVectorize/predicated-single-exit.ll
M llvm/test/Transforms/LoopVectorize/single-early-exit-cond-poison.ll
M llvm/test/Transforms/LoopVectorize/single-early-exit-deref-assumptions.ll
M llvm/test/Transforms/LoopVectorize/single-early-exit-interleave-only.ll
M llvm/test/Transforms/LoopVectorize/single-early-exit-interleave.ll
M llvm/test/Transforms/LoopVectorize/single_early_exit.ll
M llvm/test/Transforms/LoopVectorize/single_early_exit_live_outs.ll
M llvm/test/Transforms/LoopVectorize/sink-to-early-exit.ll
M llvm/test/Transforms/LoopVectorize/vector-loop-backedge-elimination-early-exit.ll
M llvm/test/Transforms/LoopVectorize/vector-loop-backedge-elimination-predicated-early-exit.ll
Log Message:
-----------
[VPlan] Use frozen combined condition in early exit first-active-lane (#223643)
Combined is used both to compute if an early exit was taken via
VPInstruction::AnyOf, as well as the index of the early-exited lane in
VPInstruction::FirstActiveLane.
Combined can have poison lanes past the exited lane, so the AnyOf uses
freeze to prevent branching on poison. However FirstActiveLane on a
vector with a poison lane is poison (see #223935), so we need to also
use the frozen version of Combined to prevent poison there.
Commit: 7af28a7e7b3073593d5f394d02b10f382d6cbab1
https://github.com/llvm/llvm-project/commit/7af28a7e7b3073593d5f394d02b10f382d6cbab1
Author: Kai Nacke <kai.peter.nacke at ibm.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/MC/GOFFObjectWriter.cpp
M llvm/test/CodeGen/SystemZ/zos-section-1.ll
M llvm/test/CodeGen/SystemZ/zos-section-2.ll
M llvm/test/CodeGen/SystemZ/zos-symbol-2.ll
Log Message:
-----------
[SystemZ][z/OS] Use section ordinal for temporary symbols (#226306)
A relocation involving a temporary symbol is interpreted as offset of
the symbol to the section begin. Currently, this is resolved via the
begin symbol of the section. However, that symbol may also have the
temporary flag set, and therefore has an index of 0. Since a symbol is
emitted of reach section, it is safe to use the ordinal of the section
instead, avoiding all issues with temporary symbols.
Commit: 621e088c0f5d435506a0d344d3b62ddc11f16147
https://github.com/llvm/llvm-project/commit/621e088c0f5d435506a0d344d3b62ddc11f16147
Author: Ebuka Ezike <e_ezike at apple.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M lldb/packages/Python/lldbsuite/test/tools/lldb_dap/session_helpers.py
M lldb/tools/lldb-dap/Handler/ThreadsRequestHandler.cpp
Log Message:
-----------
[lldb-dap] Always return the up-to-date thread if possible. (#226140)
Only send the initial thread list if the process is not stopped and only
the first time.
Remove the workaround in tests. This should not affect tests since we
mostly get the `threadId` from a stopped event.
Commit: edd241997b82b7803bd496933e340762cc06bd77
https://github.com/llvm/llvm-project/commit/edd241997b82b7803bd496933e340762cc06bd77
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h
Log Message:
-----------
[LV] Remove unused VectorizationFactor comparison operators (NFC) (#226511)
VectorizationFactor::operator== and operator!= have no users. Remove it.
Commit: 8ccb1826dad0257eda59d88b5fd35a0bc3b933f8
https://github.com/llvm/llvm-project/commit/8ccb1826dad0257eda59d88b5fd35a0bc3b933f8
Author: Pedro Vicente <pmadcv at gmail.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/docs/LangRef.md
M llvm/docs/ReleaseNotes.md
M llvm/include/llvm-c/Core.h
M llvm/include/llvm/Analysis/InstSimplifyFolder.h
M llvm/include/llvm/Analysis/TargetFolder.h
M llvm/include/llvm/AsmParser/LLParser.h
M llvm/include/llvm/AsmParser/LLToken.h
M llvm/include/llvm/Bitcode/LLVMBitCodes.h
M llvm/include/llvm/IR/ConstantFolder.h
M llvm/include/llvm/IR/IRBuilder.h
M llvm/include/llvm/IR/IRBuilderFolder.h
M llvm/include/llvm/IR/InstVisitor.h
M llvm/include/llvm/IR/Instruction.def
M llvm/include/llvm/IR/Instructions.h
M llvm/include/llvm/IR/NoFolder.h
M llvm/lib/AsmParser/LLLexer.cpp
M llvm/lib/AsmParser/LLParser.cpp
M llvm/lib/Bitcode/Reader/BitcodeReader.cpp
M llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
M llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h
M llvm/lib/CodeGen/TargetLoweringBase.cpp
M llvm/lib/IR/AsmWriter.cpp
M llvm/lib/IR/Core.cpp
M llvm/lib/IR/Instruction.cpp
M llvm/lib/IR/Instructions.cpp
M llvm/lib/IR/Verifier.cpp
M llvm/test/Analysis/IR2Vec/Inputs/reference_default_vocab_print.txt
M llvm/test/Analysis/IR2Vec/Inputs/reference_wtd1_vocab_print.txt
M llvm/test/Analysis/IR2Vec/Inputs/reference_wtd2_vocab_print.txt
A llvm/test/Assembler/bitinsert-bitextract-invalid.ll
A llvm/test/Assembler/bitinsert-bitextract.ll
M llvm/test/Bitcode/compatibility.ll
A llvm/test/CodeGen/AArch64/bitinsert-bitextract-common-offsets.ll
A llvm/test/CodeGen/AArch64/bitinsert-bitextract-fp.ll
A llvm/test/CodeGen/AArch64/bitinsert-bitextract.ll
A llvm/test/CodeGen/AMDGPU/bitinsert-bitextract-common-offsets.ll
A llvm/test/CodeGen/AMDGPU/bitinsert-bitextract-fp.ll
A llvm/test/CodeGen/AMDGPU/bitinsert-bitextract.ll
A llvm/test/CodeGen/ARM/bitinsert-bitextract-common-offsets.ll
A llvm/test/CodeGen/ARM/bitinsert-bitextract-fp.ll
A llvm/test/CodeGen/ARM/bitinsert-bitextract.ll
A llvm/test/CodeGen/PowerPC/bitinsert-bitextract-common-offsets.ll
A llvm/test/CodeGen/PowerPC/bitinsert-bitextract-fp.ll
A llvm/test/CodeGen/PowerPC/bitinsert-bitextract.ll
A llvm/test/CodeGen/RISCV/bitinsert-bitextract-common-offsets.ll
A llvm/test/CodeGen/RISCV/bitinsert-bitextract-fp.ll
A llvm/test/CodeGen/RISCV/bitinsert-bitextract.ll
A llvm/test/CodeGen/X86/GlobalISel/bitinsert-bitextract.ll
A llvm/test/CodeGen/X86/bitinsert-bitextract-common-offsets.ll
A llvm/test/CodeGen/X86/bitinsert-bitextract-fp.ll
A llvm/test/CodeGen/X86/bitinsert-bitextract.ll
A llvm/test/Verifier/bitextract-bitinsert-invalid-verifier.ll
M llvm/test/tools/llvm-ir2vec/entities.ll
M llvm/test/tools/llvm-ir2vec/triplets.ll
M llvm/tools/llvm-c-test/echo.cpp
M llvm/unittests/Analysis/IR2VecTest.cpp
Log Message:
-----------
[IR] Implementation and lowering of `bitinsert` and `bitextract` (#200605)
This PR introduces `bitinsert` and `bitextract` instructions for LLVM
IR. These allow bit manipulation for byte types. Both were lowered to
GlobalIsel and SDag.
Tests were added for AArch64, AMDGPU, ARM, PowerPC, RISCV, x86 and LLVM
IR.
The LangRef was updated to document the new instructions.
The lowering of `bitextract` and `bitinsert` instructions are
implemented using integer operations.
In order to obtain the results for `bitextract`, a shift right
instruction with a specific offset is used (that can be a variable or an
immediate).
Relative to floating-point, in `bitinsert`, we reinterpret the bits of
the floating-point value as if it is an integer.
Pointer operands and results are reinterpreted as if by bitcast, as
specified in the LangRef.
This PR is based on the RFC:
https://discourse.llvm.org/t/rfc-bitinsert-and-bitextract-instructions-for-llvm-ir-2/90764
Commit: 5b8e65685b4fe99191a217bfa0527c51cf36925c
https://github.com/llvm/llvm-project/commit/5b8e65685b4fe99191a217bfa0527c51cf36925c
Author: Jason Van Beusekom <jason.van-beusekom at hpe.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M offload/include/Shared/SourceInfo.h
M openmp/docs/ReleaseNotes.md
Log Message:
-----------
[Offload][OpenMP] remove SourceInfo::removePath (#226283)
Following discussion on
https://discourse.llvm.org/t/rfc-add-opt-in-option-for-full-source-paths-in-offload-info-output/91901
this commit removes SourceInfo::removePath which changes
LIBOMPTARGET_INFO to provide a non truncated source path:
``` c
#include <stdio.h>
#define N 4
int main(void) {
int a[N];
for (int i = 0; i < N; ++i)
a[i] = 0;
#pragma omp target map(tofrom : a[0 : N])
{
a[0] = 1;
}
printf("%d\n", a[0]); /* expect 1 */
return 0;
}
```
``` bash
clang -fopenmp -fopenmp-targets=amdgcn-amd-amdhsa -g ./test/test.c
# new
LIBOMPTARGET_INFO=-1 ./a.out
omptarget device 0 info: Entering OpenMP kernel at ./test/test.c:9:1 with 1 arguments:
# old
LIBOMPTARGET_INFO=-1 ./a.out
omptarget device 0 info: Entering OpenMP kernel at test.c:9:1 with 1 arguments:
```
Commit: 0551d60c516c2dc161007ee9ed466f36be40667d
https://github.com/llvm/llvm-project/commit/0551d60c516c2dc161007ee9ed466f36be40667d
Author: Zorojuro <sawantsukumar at gmail.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M libc/src/__support/math/bf16sub.h
M libc/src/__support/math/bf16subf.h
M libc/src/__support/math/bf16subf128.h
M libc/test/shared/shared_math_constexpr_test.cpp
Log Message:
-----------
[libc] Make bf16sub functions constexpr (#223506)
Makes the bf16sub for all types constexpr along with tests
Commit: d4c354ca333192d2db3d45b2b028a98f9fbbd347
https://github.com/llvm/llvm-project/commit/d4c354ca333192d2db3d45b2b028a98f9fbbd347
Author: Maksim Levental <maksim.levental at gmail.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M mlir/include/mlir-c/Rewrite.h
M mlir/lib/CAPI/Transforms/Rewrite.cpp
M mlir/test/CAPI/CMakeLists.txt
M mlir/test/CAPI/rewrite.c
Log Message:
-----------
[mlir-c] Add mlirDialectMaterializeConstant (#206553)
Exposes `Dialect::materializeConstant` through the MLIR C API, letting
callers ask a dialect to build a constant operation for a given
attribute and type.
Assisted by: Claude
Commit: 14f451262dc753b53f79a103744dd6988894467f
https://github.com/llvm/llvm-project/commit/14f451262dc753b53f79a103744dd6988894467f
Author: Derek Schuff <dschuff at chromium.org>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M clang/lib/Basic/Targets/WebAssembly.cpp
M clang/lib/Basic/Targets/WebAssembly.h
M clang/test/CodeGen/thread-model.c
M clang/test/CodeGenCXX/static-init-wasm.cpp
M clang/test/Preprocessor/init.c
M llvm/lib/Target/WebAssembly/WebAssemblyCoalesceFeaturesAndStripAtomics.cpp
M llvm/lib/TargetParser/Triple.cpp
R llvm/test/CodeGen/WebAssembly/coalesce-features-thread-model.ll
Log Message:
-----------
[clang][WeAssembly] Do not override thread model when building without atomics (#225981)
This change does 2 things. The first is to revert #223917, setting the
Triple's
default thread model back to posix. The second is to stop overriding it
when
atomics are not enabled.
This means that compiles with no thread- or atomics-related flags will
get the default posix thread model, independently of whether they get
_REENTRANT defined or the atomics feature is enabled. Practically this
means that the thread model will always be posix unless explicitly
overridden at the driver command line.
The leftover setting of Opts.POSIXThreads became a no-op when used
with the clang driver because the logic would only activate when
-pthread
was not already used (since the driver has separate logic linking
several
flags together).
This is a safer version of the status quo before the thread-model
module flag was introduced, because atomics are still lowered
in the same way but there is no risk of unsafe initialization
or LICM in such scenarios. We could probably further simplify
the interaction between various thread- and atomics-related
flags and thread agnosticism, but this is a small step
that fixes a known hazard.
Commit: 73fc71b19905b15e6ff14ae3149c6fabce961c1b
https://github.com/llvm/llvm-project/commit/73fc71b19905b15e6ff14ae3149c6fabce961c1b
Author: Jan Svoboda <jan_svoboda at apple.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M clang/unittests/Lex/LexerTest.cpp
Log Message:
-----------
[clang][test] Fix lifetimes of HS/PP options (#225885)
PR #133467 changed how lifetimes work for `PreprocessorOptions`. In
LexerTest.cpp, the lifetimes were set up incorrectly, leading to
potential use-after-free crashes. This PR fixes that by expanding the
lifetime of both `PreprocessorOptions` and `HeaderSearchOptions`.
Commit: 9068aede6fcbd3e47602fce96fbb077e3e4d8cc4
https://github.com/llvm/llvm-project/commit/9068aede6fcbd3e47602fce96fbb077e3e4d8cc4
Author: Luke Lau <luke at igalia.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/test/Transforms/LoopVectorize/early-exit-live-out-extract-lane.ll
Log Message:
-----------
[LV] Fix early exit tests after #223643. NFC (#226521)
Commit: 44f262eb67778e6bcb7675599384e010062cae10
https://github.com/llvm/llvm-project/commit/44f262eb67778e6bcb7675599384e010062cae10
Author: Alison Zhang <alisonzhang at ibm.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M clang/test/Analysis/Scalable/ssaf-src-edit-merge/conflict-preserves-unrelated-zero-length-insert.test
M clang/test/Analysis/Scalable/ssaf-src-edit-merge/conflict-stderr-without-sarif.test
M clang/test/Analysis/Scalable/ssaf-src-edit-merge/empty-input.test
M clang/test/Analysis/Scalable/ssaf-src-edit-merge/identical-overlap.test
M clang/test/Analysis/Scalable/ssaf-src-edit-merge/no-conflict-sarif-empty.test
M clang/test/Analysis/Scalable/ssaf-src-edit-merge/non-overlapping.test
M clang/test/Analysis/Scalable/ssaf-src-edit-merge/order-invariance.test
M clang/test/Analysis/Scalable/ssaf-src-edit-merge/parent-dir-missing.test
M clang/test/Analysis/Scalable/ssaf-src-edit-merge/pre-dedup-identical-non-zero-length.test
M clang/test/Analysis/Scalable/ssaf-src-edit-merge/pre-dedup-zero-length-insert.test
M clang/test/Analysis/Scalable/ssaf-src-edit-merge/range-overlap-cluster-of-three-sarif.test
M clang/test/Analysis/Scalable/ssaf-src-edit-merge/range-overlap-conflict-sarif.test
M clang/test/Analysis/Scalable/ssaf-src-edit-merge/sarif-out-parent-dir-missing.test
M clang/test/Analysis/Scalable/ssaf-src-edit-merge/single-input-internal-conflict.test
M clang/test/Analysis/Scalable/ssaf-src-edit-merge/single-input.test
M clang/test/Analysis/Scalable/ssaf-src-edit-merge/three-input-all-conflict.test
M clang/test/Analysis/Scalable/ssaf-src-edit-merge/three-input-conflict-sarif.test
M clang/test/Analysis/Scalable/ssaf-src-edit-merge/two-conflicts-different-offsets-sarif.test
M clang/test/Analysis/Scalable/ssaf-src-edit-merge/two-input-conflict-sarif.test
M clang/test/Analysis/Scalable/ssaf-src-edit-merge/two-input-conflict.test
Log Message:
-----------
[test][ssaf][AIX] Fix sed -i portability for AIX (#226293)
AIX's sed does not support the `-i` flag, causing the tests added in
https://github.com/llvm/llvm-project/pull/216183 to fail on AIX. This
patch updates the tests to use a POSIX-compliant redirect instead.
Commit: f1129f338806da062347a8ce019b88b51452917f
https://github.com/llvm/llvm-project/commit/f1129f338806da062347a8ce019b88b51452917f
Author: Ellis Hoag <ellis.sparky.hoag at gmail.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
R llvm/test/Transforms/PGOProfile/Inputs/indirect_call.proftext
M llvm/test/Transforms/PGOProfile/indirect_call_annotation.ll
Log Message:
-----------
[NFC][PGOProfile] Inline icall annotation proftext test (#226324)
Commit: 378ceb307bbc729bb918601a28c468df419b4d34
https://github.com/llvm/llvm-project/commit/378ceb307bbc729bb918601a28c468df419b4d34
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M clang/include/clang/Basic/BuiltinsRISCV.td
M clang/lib/CodeGen/TargetBuiltins/RISCV.cpp
M clang/lib/Headers/riscv_packed_simd.h
M clang/test/CodeGen/RISCV/rvp-intrinsics.c
M llvm/include/llvm/IR/IntrinsicsRISCV.td
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoP.td
M llvm/test/CodeGen/RISCV/rvp-simd-32.ll
M llvm/test/CodeGen/RISCV/rvp-simd-64.ll
Log Message:
-----------
[RISCV][P-Ext] Add builtins and IR intrinsics for packed shifts. (#225968)
The packed shift instructions use 5-bit shift amounts regardless of
element width. The C intrinsic should match this which means we can't
use C shift operators to implement them.
Rename RISCVISD::PSHL to RISCVISD::PSLL.
Commit: 1f9d3b2506fa32981fd281aab56357404af53ffe
https://github.com/llvm/llvm-project/commit/1f9d3b2506fa32981fd281aab56357404af53ffe
Author: Ellis Hoag <ellis.sparky.hoag at gmail.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
Log Message:
-----------
[NFC][PGOProfile] Inline icall annotation proftext test (#226324)
Commit: bff7b7503c1cdfdba72bcd12ef8208ad42130946
https://github.com/llvm/llvm-project/commit/bff7b7503c1cdfdba72bcd12ef8208ad42130946
Author: Ömer Sinan Ağacan <omer at osa1.net>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-vmax.ll
Log Message:
-----------
[msan] Update intrinsic list in arm64-vmax.ll (NFC) (#226387)
The intrinsics llvm.aarch64.neon.{u,s}{min,max} were removed in
0ce1b5f91add535d1e8b910ee90c178e054c65eb, remove the mentions of them in
the test file as per the review comment in #225339.
Commit: 6ec87e7ec4b3ca6f665a02e05d0e5fe9c37cd6cc
https://github.com/llvm/llvm-project/commit/6ec87e7ec4b3ca6f665a02e05d0e5fe9c37cd6cc
Author: Anshul Nigham <nigham at google.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/lldb/BUILD.bazel
Log Message:
-----------
[Bazel] Add Telemetry dependency to lldb-dap (#226526)
Fixes lldb-dap bazel layering failure introduced in commit 1cc5657c4ff6,
where LLDBUtils.h includes llvm/Telemetry/Telemetry.h.
Commit: 23e12c97a04c034a9487f4b95e3531d1ead90c59
https://github.com/llvm/llvm-project/commit/23e12c97a04c034a9487f4b95e3531d1ead90c59
Author: Kunal Dubey <xakep8 at protonmail.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M clang/include/clang/CIR/Dialect/IR/CIRAttrs.td
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/lib/CIR/CodeGen/CIRGenBuilder.h
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
M clang/test/CIR/IR/enum-attrs.cir
M clang/test/CIR/Lowering/call-llvm-intrinsic.cir
Log Message:
-----------
[CIR] Added fast-math flags to LLVM intrinsic calls (#224899)
Added fast-math flags attribute to CIR which cir.call_llvm_intrinsic now
carries through DirectToLLVM lowering. CIR now preserves fast-math flags
such as reassoc when lowering to llvm.call_intrinsic.
Added test for the same.
Commit: 774b4527fd60dc5ef7ed6539a8f2e6fe100e337b
https://github.com/llvm/llvm-project/commit/774b4527fd60dc5ef7ed6539a8f2e6fe100e337b
Author: Ryan Buchner <rbuchner at qti.qualcomm.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/include/llvm/Analysis/TargetTransformInfo.h
M llvm/include/llvm/CodeGen/BasicTTIImpl.h
M llvm/lib/Target/RISCV/RISCVProcessors.td
M llvm/lib/Target/RISCV/RISCVSubtarget.h
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/test/Analysis/CostModel/RISCV/vp-intrinsics.ll
Log Message:
-----------
[Analysis][RISCV] More accurately estimate the cost of strided vector loads (#175135)
For small constant strides, attempt to predict the amount of coalescing
that will be done by the target machine to give a better cost estimate.
Currently, strided loads/stores are costed as having a cost of 1 per
element (i.e. being equivalent to scalar loads/stores).
---------
Co-authored-by: Luke Lau <luke_lau at icloud.com>
Commit: f2b3ba3affb147bf085fd58f1f7261dd32ae91c8
https://github.com/llvm/llvm-project/commit/f2b3ba3affb147bf085fd58f1f7261dd32ae91c8
Author: Sang Ik Lee <sang.ik.lee at intel.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
A mlir/test/Integration/Dialect/XeGPU/WG/simple_gemm_bf16.mlir
R mlir/test/Integration/Dialect/XeGPU/WG/simple_mxfp_gemm.mlir
A mlir/test/Integration/Dialect/XeGPU/WG/simple_mxfp_gemm_F4.mlir
A mlir/test/Integration/Dialect/XeGPU/WG/simple_mxfp_gemm_F8.mlir
M mlir/test/Integration/Dialect/XeGPU/WG/simple_mxfp_gemm_dequantizeB_F4.mlir
A mlir/test/Integration/Dialect/XeGPU/WG/simple_mxfp_gemm_dequantizeB_F8.mlir
M mlir/test/Integration/Dialect/XeGPU/WG/simple_mxfp_gemm_quantizeA_F4.mlir
A mlir/test/Integration/Dialect/XeGPU/WG/simple_mxfp_gemm_quantizeA_F8.mlir
Log Message:
-----------
[MLIR][XeGPU] Add MXFP fp8 WG GEMM tests and use shared input set (#225944)
Adds four workgroup-level tests, updates two and renames one, so that
seven tests covering bf16, mx-fp4 and mx-fp8 exercise the same
arithmetic on the same operand values and check against the same
expected result.
1. simple_mxfp_gemm -> simple_mxfp_gemm_F4 - renamed, for consistency
with the F4/F8 suffixes used by the quantize and dequantize tests
2. (new) simple_gemm_bf16 - non-quantized bf16 GEMM at the MXFP problem
size, as the unquantized comparison point, and where the shared input
set is documented
3. (new) simple_mxfp_gemm_F8 - f8E5M2 operands with f8E8M0FNU scales
4. (new) simple_mxfp_gemm_dequantizeB_F8
5. (new) simple_mxfp_gemm_quantizeA_F8 - fp8 counterparts of the
existing fp4 tests
6. simple_mxfp_gemm_dequantizeB_F4 and simple_mxfp_gemm_quantizeA_F4 are
updated in place.
What the update changes:
* Meaningful operand values. The tests previously used all-ones
operands, which cannot distinguish a correct kernel from one that swaps
the two fp4 values in a byte, misapplies a scale, or mixes up lanes or
tiles. Operands are now drawn from the 8 magnitudes e2m1 can represent -
0, 0.5, 1, 1.5, 2, 3, 4, 6 - indexed by (i + k) % 8 and (j + k) % 8, so
consecutive K values differ and the packing is exercised. Every value is
exact in f4E2M1FN, f8E5M2, bf16 and f32, which is what lets one input
set serve all three formats.
* Non-unit block scales. A carries a per-K-block divisor and B a
per-K-block scale, three of each, all powers of two, cycling per block
of 32. The quantized formats realise the same values through their own
scales, so a scale that is ignored or applied to the wrong block now
changes the result.
* One reference result. Each test computes its expected C with a host
f32 GEMM over f32 shadows of the operands, filled in the same loop that
writes the device operands so the two cannot drift. Every product is a
multiple of 0.25 and the largest result is well under 2^24, so the
accumulation is exact and the comparison is bit-for-bit rather than
approximate.
* A labelled result line. verifyMemRefF32's mismatch count is printed as
"mismatches: <n>" via printString/printI64/printNewline and matched with
{{^mismatches: 0$}}. A bare "0" check is a substring match over all of
stdout, so it passes on any 0 the runtime happens to print, including
one inside a larger number, and cannot distinguish a correct run from a
kernel that never ran.
* A fix for the fp4 A operand in simple_mxfp_gemm_F4.
gpu.alloc/memcpy/dealloc size a memref by rounding the element type up
to a whole byte - the size is lowered as gep(null, numElements) on i4,
which LLVM strides by 1 byte - so a packed fp4 memref is sized at twice
its real footprint. The test allocated A as memref<256x4096xf4E2M1FN>,
giving a 512 KB overread of a 524288-byte host buffer; because
mgpuMemcpy is asynchronous the fault surfaces later, at the stream sync
inside the first mgpuMemFree, so the test passed regardless. A now
crosses as memref<524288xi8> and is viewed as fp4 on the device, which
is what the B operand already does.
All seven follow the existing convention in this directory: the mlir-opt
compile is the active RUN line and the mlir-runner pipeline is kept
behind RUN-DISABLED with a MISMATCH check prefix, so no device is needed
and the compile-only run cannot pick up the result check.
Commit: b3ed324d42c0487e38980f4beddbb67c096f5f3f
https://github.com/llvm/llvm-project/commit/b3ed324d42c0487e38980f4beddbb67c096f5f3f
Author: Keith Smiley <keithbsmiley at gmail.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M lld/test/Unit/lit.cfg.py
M lld/unittests/AsLibELF/CMakeLists.txt
M lld/unittests/AsLibELF/OutputStream.cpp
M lld/unittests/AsLibELF/ROCm.cpp
Log Message:
-----------
[lld][test] Use LLVM helpers for input file discovery (#220404)
This was a suggestion on #220340 to avoid the custom env var handling
and use the `getInputFileDirectory` helper from the LLVM support library
Commit: 07aec21c88f48907b5da1d42f4522e106d30a9f1
https://github.com/llvm/llvm-project/commit/07aec21c88f48907b5da1d42f4522e106d30a9f1
Author: Guo Chen <guochen2 at amd.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.h
M llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/CMakeLists.txt
A llvm/lib/Target/AMDGPU/SIPostRA16BitMovFolding.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/merge-values-s16-true16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/usubsat.ll
M llvm/test/CodeGen/AMDGPU/add.v2i16.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.32bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.48bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.64bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll
M llvm/test/CodeGen/AMDGPU/flat-saddr-load.ll
M llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll
M llvm/test/CodeGen/AMDGPU/llc-pipeline.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.gather4.a16.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.msaa.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.a16.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.g16.encode.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.g16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.waitcnt.out.order.ll
M llvm/test/CodeGen/AMDGPU/mad-mix-hi-bf16.ll
M llvm/test/CodeGen/AMDGPU/repeated-divisor.ll
M llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll
A llvm/test/CodeGen/AMDGPU/si-post-ra-merge-v-mov-b16.mir
M llvm/test/CodeGen/AMDGPU/sub.v2i16.ll
M llvm/test/CodeGen/AMDGPU/v_swap_b16.ll
M llvm/test/CodeGen/AMDGPU/vector_shuffle.packed.ll
Log Message:
-----------
[AMDGPU] merge 16bit mov pairs in post-RA peephole (#208625)
Address https://github.com/llvm/llvm-project/issues/207011. Add 5
patterns to merge 16bit mov pairs.
Since we hoist instruction which might cross the waitcnt boundary,
insert a new pass before waitcnt for this transformation
Co-Authored-By: Claude
Commit: 3621db6aff701dcd9e6ff54ea281d24ee2f43448
https://github.com/llvm/llvm-project/commit/3621db6aff701dcd9e6ff54ea281d24ee2f43448
Author: Akash Manna <akash.manna.mymail at gmail.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M clang/docs/ReleaseNotes.md
M clang/lib/Sema/SemaOpenMP.cpp
A clang/test/OpenMP/for_loop_bitint_messages.c
Log Message:
-----------
[Clang][OpenMP] Fix crash on `_BitInt` loop bounds and counters in loop analysis (#226464)
Fixes #140074
When building the iteration count of an OpenMP loop, Sema derives a few
integer types from bit widths, e.g. to promote the upper bound to an
unsigned type as wide as the wider bound so that `upper - lower` cannot
overflow. Those types came from `ASTContext::getIntTypeForBitwidth`,
which only knows the standard integer widths and returns a null type for
anything else. With a bound or loop counter of type `_BitInt(931)` the
request was for a 960-bit type, the result was null, and it went
straight into `PerformImplicitConversion`, which asserted. The
`collapse(2)` in the reduced reproducer is incidental; a plain `#pragma
omp for` on the same loop crashes the same way.
The loop analysis now goes through a small helper that asks for the
standard type first and otherwise builds the `_BitInt` type of that
width and signedness with `ASTContext::getBitIntType`. It is used at the
three places that derive a type from a loop width: the upper-bound
promotion in `calculateNumIters`, the conversion to the loop variable's
width in `buildNumIterations`, and the logical iteration type in
`ActOnOpenMPCanonicalLoop`. Wide `_BitInt` loop variables are then
narrowed to the runtime's 64-bit iteration variable with the existing
warning, the same as `__int128` today.
Commit: 05f0bf084929c4fdbb5ac2952047ed00cd1d8b57
https://github.com/llvm/llvm-project/commit/05f0bf084929c4fdbb5ac2952047ed00cd1d8b57
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/Target/Mips/MipsSubtarget.cpp
M llvm/lib/Target/Mips/MipsSubtarget.h
Log Message:
-----------
Mips: Remove redundant Triple copy from the subtarget (#226528)
MCSubtargetInfo already stores the target triple, so MipsSubtarget's own
copy is unnecessary.
Co-authored-by: Claude Opus 5 <noreply at anthropic.com>
Commit: 3bcbae4bed67f5cadd9f68d39af47ae5b5af1794
https://github.com/llvm/llvm-project/commit/3bcbae4bed67f5cadd9f68d39af47ae5b5af1794
Author: Alex Langford <alangford at apple.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M lldb/include/lldb/Target/DynamicRegisterInfo.h
M lldb/source/Target/DynamicRegisterInfo.cpp
Log Message:
-----------
[lldb] Introduce DynamicRegisterInfo::RegisterSetWithStorage (#225555)
The RegisterSet struct is created in 2 different ways:
1.) Statically in headers/source files for register sets that are known
ahead of time.
2.) Dynamically according to input from outside of LLDB. Usually this is
through the gdb-remote stub, but may also come from a python script or
by determining an ISA variant's features (e.g. in RISCV).
This PR aims to address the lifetime of strings in RegisterSet. In
scenario (1), the lifetime of all data in a RegisterSet is static and
there is no concern about dangling pointers. However, in scenario (2),
DynamicRegisterInfo maintains a vector of RegisterSets. Until now, it
has relied on ConstString to persist the storage for the strings
indefinitely. As part of my quest to remove ConstString, I am
introducing a new struct wrapping RegisterSet that is responsible for
the storage and lifetime of the underlying RegisterSet strings.
Commit: d220d5e8239db918bd68f404dae589385a8029e8
https://github.com/llvm/llvm-project/commit/d220d5e8239db918bd68f404dae589385a8029e8
Author: Aditya Sinha <155882262+AdityaSinha149 at users.noreply.github.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M clang/include/clang/Interpreter/Interpreter.h
M clang/lib/Interpreter/Interpreter.cpp
A clang/test/Interpreter/HIP/hip-environment.hip
A clang/test/Interpreter/HIP/lit.local.cfg
M clang/test/lit.cfg.py
M clang/tools/clang-repl/ClangRepl.cpp
Log Message:
-----------
[clang-repl] Initialized HIP environment for clang-repl (#217582)
This PR initializes the HIP environment for clang-repl. Since an
IncrementalHipDeviceParser does not exist yet, a message is printed
after the environment setup indicating that the HIP environment was set
up but is not yet supported.
It also adds a test file that runs clang-repl with the -hip option and
checks that this message is printed. Once the parser is built, the
current test file will be removed and replaced with tests that verify
the complete flow.
This PR has a prerequisite, #217228, which skips emitting the
`__hip_cuid_` global under incremental extensions. Without it,
clang-repl's HIP mode would emit the same symbol in every incremental
module and fail at JIT link with a duplicate-symbol error.
Assisted by Claude Opus 4.8
Commit: 0ae27ad06c80796bdae576e27a44b2877e5c2a4f
https://github.com/llvm/llvm-project/commit/0ae27ad06c80796bdae576e27a44b2877e5c2a4f
Author: Gaëtan Bossu <gaetan.bossu at arm.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/test/Analysis/CostModel/AArch64/masked_ldst.ll
M llvm/test/Analysis/CostModel/AArch64/sve-arith.ll
M llvm/test/Analysis/CostModel/AArch64/sve-ldst.ll
M llvm/test/CodeGen/AArch64/sve-int-arith.ll
M llvm/test/Transforms/LoopVectorize/AArch64/force-scalable-vectorization-always.ll
M llvm/test/Transforms/LoopVectorize/AArch64/invalid-costs.ll
M llvm/test/Transforms/LoopVectorize/AArch64/scalable-alloca.ll
M llvm/test/Transforms/LoopVectorize/AArch64/scalable-call.ll
M llvm/test/Transforms/LoopVectorize/AArch64/scalable-vectorization-cost-tuning.ll
Log Message:
-----------
Revert "[AArch64][CostModel] Consider some nxv1 operations as legal" (#226531)
Reverts llvm/llvm-project#214471
This caused a failure in
https://lab.llvm.org/buildbot/#/builders/198/builds/15417 and I want to
spend a bit more time to test the ISel for vector_reverse and
vector_splice. It's also quite surprising that the test picked a VF of
`vscale x 1`
Commit: 9214c04da2ea302b773797f50ad11636c7bab097
https://github.com/llvm/llvm-project/commit/9214c04da2ea302b773797f50ad11636c7bab097
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M clang/lib/CodeGen/CGLoopInfo.cpp
M clang/test/CodeGen/align-loops.c
Log Message:
-----------
clang: Emit llvm.loop.align metadata for -falign-loops (#223147)
Commit: 9dcb4291cea195b9f0941d39540a4f2ccb9ff6bd
https://github.com/llvm/llvm-project/commit/9dcb4291cea195b9f0941d39540a4f2ccb9ff6bd
Author: Charles Zablit <c_zablit at apple.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M lldb/test/API/python_api/value/TestValueAPI.py
Log Message:
-----------
[lldb][test] Skip the sp/rsp check in register sets that have no rsp (#226176)
The test asserts the ABI name `"sp"` resolves to `"rsp"` within the same
register set. However, on Windows the architectural 16-bit `"sp"` lives
in `"supplementary registers"` while `"rsp"` is in `"General Purpose
Registers"`, so there is nothing to compare against.
https://learn.microsoft.com/en-us/windows-hardware/drivers/debugger/x64-architecture
This fixes `python_api/value/TestValueAPI.py` (`test_register`) on
Windows in swiftlang.
Commit: 51ccdfeadcfe29b1d46f978e8582ada109aebb91
https://github.com/llvm/llvm-project/commit/51ccdfeadcfe29b1d46f978e8582ada109aebb91
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M libcxx/test/benchmarks/containers/string.bench.cpp
Log Message:
-----------
[libc++] Add benchmark for string::pop_back() (#223729)
Commit: 68d354f5795682ea1fe03304ac3e7b2a43a36b0d
https://github.com/llvm/llvm-project/commit/68d354f5795682ea1fe03304ac3e7b2a43a36b0d
Author: Jason Van Beusekom <jason.van-beusekom at hpe.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M offload/include/Shared/SourceInfo.h
M openmp/docs/ReleaseNotes.md
Log Message:
-----------
Revert "[Offload][OpenMP] remove SourceInfo::removePath (#226283)" (#226557)
This reverts commit 5b8e65685b4fe99191a217bfa0527c51cf36925c.
In https://github.com/llvm/llvm-project/pull/226283 I forgot to update
info.c to account for the full file paths in its output, will update
commit with fixed test and re open PR
Commit: d92a0c1e5eba51dbf9a4c2a61a709b6758f2e40d
https://github.com/llvm/llvm-project/commit/d92a0c1e5eba51dbf9a4c2a61a709b6758f2e40d
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M mlir/include/mlir/IR/BuiltinDialect.td
M mlir/include/mlir/IR/BuiltinOps.td
M mlir/test/IR/module-op.mlir
M mlir/test/Transforms/sccp-callgraph.mlir
M mlir/test/Transforms/test-symbol-dce.mlir
M mlir/test/python/dialects/ml_program.py
Log Message:
-----------
[MLIR] Enable strict assembly properties for the builtin dialect (#225750)
Commit: 48884d2ddba0718960f68eb01a5b8c42c089f27c
https://github.com/llvm/llvm-project/commit/48884d2ddba0718960f68eb01a5b8c42c089f27c
Author: Cyndy Ishida <cyndy_ishida at apple.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M clang/lib/Lex/HeaderSearch.cpp
A clang/test/ClangScanDeps/modules-context-hash-case-sensitive-vfs-paths.c
M clang/test/ClangScanDeps/modules-context-hash-module-map-path.c
A clang/test/Modules/implicit-module-map-path-case-sensitive.c
Log Message:
-----------
[clang][Modules] Respect case sensitivity when hashing implicit module map path (#226339)
Before this patch, the implicit module hash normalized the module map
path, but explicit modules always respected the case in paths. This
worked by depending on FileEntry caching and/or relocation checking to
resolve correctly. This behavior was both subtle and difficult to
understand. Instead, respect the casing in paths for hashing to match
explicitly built modules so they can never diverge.
This patch also updates `modules-context-hash-module-map-path.c` to
match a downstream version that already tested for the case where vfs
overlay entries differ by case but point to the same file.
`modules-context-hash-case-sensitive-vfs-paths.c` is the same but points
to different underlying files.
Commit: 36e7743d8ec9e743ae66485ddf2a6b27549c8833
https://github.com/llvm/llvm-project/commit/36e7743d8ec9e743ae66485ddf2a6b27549c8833
Author: Anshil Gandhi <95053726+gandhi56 at users.noreply.github.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/Passes/LoadStoreVec.h
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/VecUtils.h
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/Passes/LoadStoreVec.cpp
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/VecUtils.cpp
Log Message:
-----------
[SandboxVec][LoadStoreVec][NFC] Tighten bundle element types (#226348)
Use Instruction*/Constant* for LoadStoreVec APIs where that is what
callers hold, and template getCombinedVectorTypeFor so BndlRef is not
forced through a non-covariant Value* conversion.
Co-authored-by: Cursor <cursoragent at cursor.com>
Commit: 72674697a28c25467649c4993eb033dc4af65951
https://github.com/llvm/llvm-project/commit/72674697a28c25467649c4993eb033dc4af65951
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/test/Transforms/LoopVectorize/VPlan/execution-frequencies-match-bfi.ll
M llvm/test/Transforms/LoopVectorize/X86/predicated-instruction-cost.ll
M llvm/test/Transforms/LoopVectorize/replicate-region-branch-weights.ll
Log Message:
-----------
[LV] Add tests for zero branch weights and execution frequencies (NFC). (#226553)
Add missing test coverage for VPlan-based execution frequency
computation:
* blocks entered via an edge with zero branch weight,
* blocks whose sibling edge has zero weight,
* nested branches whose skipping edges have zero weight,
* a block executing on all paths through the loop after a switch whose
probabilities do not add up to 1,
* frequencies below the smallest representable non-zero one
* all-zero weights making a join's frequency unknown
* estimated frequencies propagating through a branch with weights.
Also updates
llvm/test/Transforms/LoopVectorize/VPlan/execution-frequencies-match-bfi.ll
to check frequencies directly after the frequencies have been recorded.
Commit: a9809116ca6130906f20c727464ba8e878b59aa5
https://github.com/llvm/llvm-project/commit/a9809116ca6130906f20c727464ba8e878b59aa5
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M .github/workflows/libcxx-benchmark-commit.yml
M .github/workflows/libcxx-benchmark-cron.yml
M .github/workflows/libcxx-pr-benchmark.yml
M libcxx/utils/ci/lnt/README.md
M libcxx/utils/ci/lnt/machines.json
M libcxx/utils/ci/lnt/run-benchmarks
M libcxx/utils/ci/run-buildbot
Log Message:
-----------
[libc++] Add a benchmark machine for libstdc++ (#226346)
Add a machine that benchmarks the libstdc++ shipped with GCC 16 on macOS
instead of a libc++ build. To enable that, generalize the scripts and
workflows to make more aspects of machines.json optional (e.g. support
machines that don't need to build libc++).
Commit: 8dc7b3d92cc6371d942dc7619a81faa1f56de938
https://github.com/llvm/llvm-project/commit/8dc7b3d92cc6371d942dc7619a81faa1f56de938
Author: Joshua Batista <jbatista at microsoft.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M clang/include/clang/Basic/Builtins.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Basic/HLSLIntrinsics.td
M clang/lib/CodeGen/CGHLSLBuiltins.cpp
M clang/lib/CodeGen/CGHLSLRuntime.h
M clang/lib/Sema/SemaHLSL.cpp
A clang/test/CodeGenHLSL/builtins/WaveReadLaneFirst.hlsl
A clang/test/SemaHLSL/BuiltIns/WaveReadLaneFirst-errors.hlsl
M clang/test/SemaHLSL/WaveBuiltinAvailability.hlsl
M llvm/include/llvm/IR/IntrinsicsDirectX.td
M llvm/include/llvm/IR/IntrinsicsSPIRV.td
M llvm/lib/Target/DirectX/DXIL.td
M llvm/lib/Target/DirectX/DXILShaderFlags.cpp
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
A llvm/test/CodeGen/DirectX/LongVector/wave-readlane-first.ll
M llvm/test/CodeGen/DirectX/ShaderFlags/wave-ops.ll
A llvm/test/CodeGen/DirectX/WaveReadLaneFirst.ll
A llvm/test/CodeGen/DirectX/WaveReadLaneFirst_mat.ll
A llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_long_vector/wave-readlane-first.ll
A llvm/test/CodeGen/SPIRV/hlsl-intrinsics/WaveReadLaneFirst.ll
A llvm/test/CodeGen/SPIRV/hlsl-intrinsics/WaveReadLaneFirst_mat.ll
Log Message:
-----------
Add WaveReadLaneFirst HLSL function (#220373)
This PR adds the `WaveReadLaneFirst` HLSL function.
Fixes https://github.com/llvm/llvm-project/issues/99164
Assisted by: Github Copilot
Commit: 7b42d2f9991c3680627878a49b1b323cb56176a0
https://github.com/llvm/llvm-project/commit/7b42d2f9991c3680627878a49b1b323cb56176a0
Author: Nico Weber <thakis at chromium.org>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/Target/AMDGPU/BUILD.gn
Log Message:
-----------
[gn build] Port 07aec21c88f4 (#226571)
Commit: cc527d5399997024a68be6241e3a70a6f05a338e
https://github.com/llvm/llvm-project/commit/cc527d5399997024a68be6241e3a70a6f05a338e
Author: Nico Weber <thakis at chromium.org>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/utils/gn/secondary/lld/unittests/AsLibELF/BUILD.gn
Log Message:
-----------
[gn] port b3ed324d42c04 (#226570)
Commit: bbd2e0f7ce13d2a1ff8336018d3b034eb3c698a0
https://github.com/llvm/llvm-project/commit/bbd2e0f7ce13d2a1ff8336018d3b034eb3c698a0
Author: Jiaxun Yang <jiaxun.yang at flygoat.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/Target/Mips/MipsISelLowering.cpp
M llvm/test/CodeGen/Mips/extins.ll
Log Message:
-----------
[Mips] Enable generic bitfield extract preparation (#226491)
Enable CodeGenPrepare's shift sinking when the subtarget supports
bitfield extract instructions. This exposes shift-and-mask patterns
across basic blocks to the existing MIPS extract combine.
Use hasExtractInsert() to keep this disabled for pre-r2 targets and
MIPS16. Add a minimal cross-block regression case to extins.ll.
Commit: 5bc083e278a59853fcfcf3649ba7a20457ead1e5
https://github.com/llvm/llvm-project/commit/5bc083e278a59853fcfcf3649ba7a20457ead1e5
Author: Nico Weber <thakis at chromium.org>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/utils/gn/secondary/lld/unittests/AsLibELF/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/DebugInfo/LogicalView/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/DebugInfo/PDB/BUILD.gn
Log Message:
-----------
[gn] port b3ed324d42c04 more (#226574)
Commit: 0a21a0712b800a3cc1af87e1d0ceb1a84f2b24bd
https://github.com/llvm/llvm-project/commit/0a21a0712b800a3cc1af87e1d0ceb1a84f2b24bd
Author: Patrick Rachford <pat at modular.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/MC/WasmObjectWriter.cpp
M llvm/test/MC/WebAssembly/reloc-pic64.s
Log Message:
-----------
[WebAssembly] Emit i64 GOT import globals on wasm64 (#226326)
WasmObjectWriter hardcodes the synthetic GOT import globals
(GOT.mem/GOT.func) to i32, but on wasm64 they hold 64-bit addresses, so
the object is type-invalid against the i64 global.get that consumes
them. wasm-ld already emits i64 GOT imports on wasm64, so this aligns
the object writer with the linker: the import type is gated on
is64Bit(), and the reloc-pic64 expectations are updated. The wasm32
checks are unchanged.
Commit: 229e7000493f118d49d23073d3bfa613b3798d85
https://github.com/llvm/llvm-project/commit/229e7000493f118d49d23073d3bfa613b3798d85
Author: Marcos Ramirez Joos <mramirezjoos.oss at proton.me>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M libc/src/__support/FPUtil/FEnvImpl.h
Log Message:
-----------
[libc] Avoid system fenv.h in FEnvImpl.h when LIBC_MATH_HAS_NO_EXCEPT is set (#224384)
The warning being added under #199009 triggers errors in subprojects
(e.g., flang) using libc headers that gate the use of `#pragma STDC
FENV_ACCESS ON` on the internal libc
`LIBC_COMPILER_HAS_STDC_FENV_ACCESS` flag, when building under
`-Wfenv-access -Werror`. As the idea is for these subprojects to not
access the libc FP environment (see
https://github.com/llvm/llvm-project/pull/199009#issuecomment-5299119396),
gating the use of system fenv.h functions on the
`LIBC_MATH_HAS_NO_EXCEPT` flag avoids having to specify the
`LIBC_COMPILER_HAS_STDC_FENV_ACCESS` flag when building them.
The three line removals are a clean-up related to
https://github.com/llvm/llvm-project/pull/200268. These uses are
redundant as the called functions already use the pragma when
appropriate.
Commit: 7ca0ce59bb82557a3052666562cc8f0d6d03ec41
https://github.com/llvm/llvm-project/commit/7ca0ce59bb82557a3052666562cc8f0d6d03ec41
Author: Finn Plummer <mail at inbelic.dev>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/Target/DirectX/DXILOpBuilder.cpp
M llvm/test/CodeGen/DirectX/LoadInput.ll
M llvm/test/CodeGen/DirectX/StoreOutput.ll
Log Message:
-----------
[DirectX] Preserve all shader-stage bits during DXIL op lowering (#225874)
The vertex-stage bit is above bit 15 and was lost when the mask was
narrowed to uint16_t. This would cause an incorrect lowering error:
https://godbolt.org/z/rEMj8ssK9.
Corrected by keeping it as a 32 bit value.
Assisted by: ChatGPT 6 Astra
Commit: 44c84768990686eb1e24b4d1dcbd13fff37442bb
https://github.com/llvm/llvm-project/commit/44c84768990686eb1e24b4d1dcbd13fff37442bb
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVExpandPseudoPostRA.cpp
M llvm/lib/Target/RISCV/RISCVExpandPseudoPreEmit.cpp
M llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
M llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
M llvm/lib/Target/RISCV/RISCVLoadStoreOptimizer.cpp
M llvm/lib/Target/RISCV/RISCVZilsdOptimizer.cpp
Log Message:
-----------
[RISCV] Replace uses of RegState::Define. NFC (#226569)
Either pass the destination register to the BuildMI call or use addDef
if there are multiple defs or other flags are set.
Commit: 19d72fd6deab2ea3addd8b945807abd02b1bbb70
https://github.com/llvm/llvm-project/commit/19d72fd6deab2ea3addd8b945807abd02b1bbb70
Author: Kerry McLaughlin <kerry.mclaughlin at arm.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M clang/lib/CodeGen/TargetBuiltins/ARM.cpp
M clang/lib/Sema/SemaARM.cpp
M llvm/include/llvm/Support/AArch64MemoryHints.h
M llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
Log Message:
-----------
[AArch64] Rename memory hints to avoid clash with arm_acle.h macros (#226432)
Renames the hints in AArch64MemoryHints.h, as HINT_STSHH_KEEP and
HINT_STSHH_STRM are already defined in arm_acle.h.
Commit: e76dd51398a8ceac33e9e5bf3253dd6b03b965dd
https://github.com/llvm/llvm-project/commit/e76dd51398a8ceac33e9e5bf3253dd6b03b965dd
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
A llvm/test/Transforms/SLPVectorizer/RISCV/trimmed-node-matching-gather.ll
Log Message:
-----------
[SLP][NFC]ADd a test with the missed vectorization, NFC
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/226581
Commit: d506ee743cdaef27448964890f813bd3b7da7953
https://github.com/llvm/llvm-project/commit/d506ee743cdaef27448964890f813bd3b7da7953
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/RISCV/trimmed-node-matching-gather.ll
Log Message:
-----------
[SLP]Reuse the trimmed nodes in the perfectly matched gathers of the same user
The gather node, perfectly matching the node of the same user
transformed to gather during throttling, did not treat this node as a
reuse source, and was costed and emitted as a separate buildvector.
Fixes #219030
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/226582
Commit: f57595ff59a0f012e0481c69613be907942c30b1
https://github.com/llvm/llvm-project/commit/f57595ff59a0f012e0481c69613be907942c30b1
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanVerifier.cpp
M llvm/unittests/Transforms/Vectorize/VPlanVerifierTest.cpp
Log Message:
-----------
[VPlan] Only exempt MaskedCond from cross-block dominance in verifier. (#226512)
Previously the verifier skipped all use-before-def checks for
MaskedCond, including uses in the same block before the definition.
Restrict the exemption to users in blocks not dominated by the
MaskedCond's block, so same-block use-before-def is still diagnosed.
Commit: 08af99fae9e079b448cd8877fc57376efe680cda
https://github.com/llvm/llvm-project/commit/08af99fae9e079b448cd8877fc57376efe680cda
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/include/llvm/CodeGen/SDPatternMatch.h
Log Message:
-----------
[SDPatternMatch] Implement m_True/False using SelectionDAG::isBoolConstant. (#226216)
Better than duplicating existing functionality.
Commit: e4af48bd3b330282f36f075d6fa7a4a0742376c1
https://github.com/llvm/llvm-project/commit/e4af48bd3b330282f36f075d6fa7a4a0742376c1
Author: Ehsan Amiri <ehsan.amiri at huawei.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Scalar/LoopFuse.cpp
A llvm/test/Transforms/LoopFusion/guard_skip_empty_block.ll
Log Message:
-----------
[LoopFusion] Cleanup control flow before Fusion (#226289)
Non-loop successor of loop guard is sometimes modified by JumpThreading
(and potentially some other passes) to jump to a new block, that doesn't
post dominate the exit block of the loop:
Guard: br %c, %Preheader, %Skip
Skip: br %Merge
...
Exit: br %Merge
Merge: ...
Later on, this block becomes empty, so it can be removed. Its presence
prevents Loop::getLoopGuardBranch() from detecting the loop guard which
results in missed fusion opportunities. SimplifyCFG will run when "Skip"
is still not optimzied, so it cannot resolve this issue.
Assisted by Claude Code
Commit: ee3b6b045bc37b156c3860481090d68367e961dc
https://github.com/llvm/llvm-project/commit/ee3b6b045bc37b156c3860481090d68367e961dc
Author: agozillon <Andrew.Gozillon at amd.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M flang/lib/Lower/OpenMP/ClauseProcessor.cpp
M flang/lib/Lower/OpenMP/Utils.cpp
M flang/lib/Lower/OpenMP/Utils.h
M flang/test/Lower/OpenMP/declare-mapper.f90
A flang/test/Lower/OpenMP/target-map-nested-dtype-allocatable-member.f90
Log Message:
-----------
[Flang][OpenMP] Fix broken offload test caused by MapInfoFinalization code movement (#226384)
This change addresses the breakage in
target-map-nested-dtype-allocatable-member.f90 I inadvertently broke it
by removing the excess bit of implicit mapping code in the
MapInfoFinalizaiton pass without correctly addressing it.
This PR tries to do so by allowing mappers to be generated for member
maps such as var1%b, var2%b, which were previously being blocked.
Currently (and conveniently for this patch) we do avoid duplicate maps
in the scenario where we specify something along the lines of:
map(tofrom: var1, var1%b, var2, var2%b)
But that is through the fact that we completely negate var1/var2's
mapper attachment in this scenario, which I do not believe is the
correct behavior. But it's the existing behavior and facilitates this
patch, but it is something I'll see if I can address in a follow up PR
in the near future, the logic might need a bit of debating. For now this
simply seeks to amend the existing test without rocking the boat more
than required (that's the hope at least).
Commit: ae614a9564425ab206940f2b91607b1d77826068
https://github.com/llvm/llvm-project/commit/ae614a9564425ab206940f2b91607b1d77826068
Author: Aaron <58265908+aaronsms at users.noreply.github.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M clang/lib/Format/ContinuationIndenter.cpp
M clang/unittests/Format/FormatTest.cpp
Log Message:
-----------
[clang-format] Preserve enum initializer continuation indentation (#223435)
Fixes #223011
Enum assignment operators are annotated as TT_EnumEqual so they can be
aligned independently in #194154. However, this means
ContinuationIndenter no longer recognizes a wrapped enum `=` as
TT_BinaryOperator. As a result, it may force unnecessary breaks within
the RHS binary expression.
Co-authored-by: Aaron Saw Min Sern <aaron at aaronsms.com>
Commit: 4db3dceb8d7bffa4b69042fe043652d616396237
https://github.com/llvm/llvm-project/commit/4db3dceb8d7bffa4b69042fe043652d616396237
Author: Jeremy Kun <jkun at google.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/Support/StringRef.cpp
M llvm/unittests/ADT/StringRefTest.cpp
Log Message:
-----------
[llvm] produce a more consistent estimates of bit width needed when parsing an integer (#205947)
A colleague of mine noticed that `"12535824225335233"` parses in MLIR's
integer attribute parser as a 68-bit integer, even though it is a 53-bit
constant. I traced this back to `StringRef::consumeInteger`'s heuristic
estimate of the bit size. This change replaces that heuristic with a
default 64-bit storage, doubling the storage as more digits are parsed.
This produces a potentially larger over-estimate of the total storage
required, but does so in a less arbitrary manner and reduces the
over-approximation for numbers close to the 64-bit boundary.
Nb., A first iteration of this change tightened that estimate to at most
a 1-bit overapproximation with a lookup-table.
Assisted by Gemini
Commit: 1b4e7f41268eb3db5300e79256764140e509e3f5
https://github.com/llvm/llvm-project/commit/1b4e7f41268eb3db5300e79256764140e509e3f5
Author: Akash Manna <akash.manna.mymail at gmail.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M clang/docs/ReleaseNotes.md
M clang/lib/Sema/SemaType.cpp
M clang/test/Sema/large-bit-int.c
M clang/test/Sema/types.c
M clang/test/SemaCXX/vector.cpp
Log Message:
-----------
[Clang] Enforce the same size limits for `vector_size` and `ext_vector_type` (#226375)
Fixes #165458
A `bool` vector declared with `ext_vector_type` isn't lowered as an LLVM
vector in memory: `ConvertTypeForMem` packs it into a single integer
with one bit per element. `BuildExtVectorType` only checked that the
element count fits in 32 bits, though, so a vector of 187,553,262 bools
got through Sema and the first consumer that needed its memory type (the
zero initializer of a tentative definition here) asked
`IntegerType::get` for far more than the 2^23 bits it supports. The
count matters for every element type, not just `bool`, because Sema also
forms bool vectors out of other vectors (`c ? true : false` with a
`char` vector condition), and `vector_size` was no better off with its
limits of 2^32 elements and 2^61 bytes.
Both attributes now go through the same two limits when the type is
built, reusing the existing "vector size too large" error: at most
`llvm::IntegerType::MAX_INT_BITS` (2^23) elements, and at most 2^28
bytes so that the natural alignment, the size rounded up to a power of
two, still fits in the `unsigned` alignment of `TypeInfo`. These replace
the old `isIntN(61)` and `UINT32_MAX` checks in `BuildVectorType`.
Commit: 210ecf77c9021941ee32c496df8b715615163df4
https://github.com/llvm/llvm-project/commit/210ecf77c9021941ee32c496df8b715615163df4
Author: Eli Friedman <efriedma at qti.qualcomm.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/Transforms/IPO/Instrumentor.cpp
Log Message:
-----------
[Instrumentor] Use CreateAllocationSize to compute size of alloca (#226330)
No significant functional change, but the IR might look slightly
different.
Commit: 14e819f14307fd85fe830cf9fe8d168a27b3db89
https://github.com/llvm/llvm-project/commit/14e819f14307fd85fe830cf9fe8d168a27b3db89
Author: Eli Friedman <efriedma at qti.qualcomm.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/include/llvm/Transforms/IPO/InstrumentorUtils.h
Log Message:
-----------
[Instrumentor] Delete dead code from getAlloca() (#226331)
Commit: 8af5ec67c2001eb379d53cc61ccce0ca521a6c3c
https://github.com/llvm/llvm-project/commit/8af5ec67c2001eb379d53cc61ccce0ca521a6c3c
Author: Abhay Kanhere <a_kanhere at apple.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/include/llvm/IR/AutoUpgrade.h
M llvm/lib/Bitcode/Reader/MetadataLoader.cpp
M llvm/lib/IR/AutoUpgrade.cpp
A llvm/test/Bitcode/upgrade-tbaa-struct.ll
A llvm/test/Bitcode/upgrade-tbaa-struct.ll.bc
Log Message:
-----------
[AutoUpgrade] Upgrade old-style !tbaa.struct field tags (#225967)
Extend the TBAA auto-upgrade to rewrite old-style scalar field tags
inside !tbaa.struct
to the struct-path aware format. bitcode (MetadataLoader) upgraded to
match the existing top-level !tbaa upgrade.
Commit: 35df00b0aa5d9f4deec215306dc24d247f5eb66c
https://github.com/llvm/llvm-project/commit/35df00b0aa5d9f4deec215306dc24d247f5eb66c
Author: Abhay Kanhere <a_kanhere at apple.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/Analysis/TypeBasedAliasAnalysis.cpp
M llvm/test/Transforms/InstCombine/struct-assign-tbaa.ll
Log Message:
-----------
[TBAA] Recover !tbaa for a memcpy of struct with same type fields (#214116)
When InstCombine widens a small same-typed aggregate copy into an
integer load/store, it derives no !tbaa, and !tbaa.struct is nulled out,
so the load/store are left untyped. An untyped access may-alias every
typed access and blocks optimization:
struct Coord { int x, y; };
void copy_if_inbounds(Coord *dst, const Coord *src, const long *bound,
int n) {
for (int i = 0; i < n; ++i)
if (i < *bound)
dst[i] = *src; // {int,int} copy -> memcpy + !tbaa.struct
}
compare this to field-by-field copy, which has typed field access
void copy_fields_if_inbounds(Coord *dst, const Coord *src, const long
*bound, int n) {
for (int i = 0; i < n; ++i)
if (i < *bound) { dst[i].x = src->x; dst[i].y = src->y; } // per-field,
typed
}
Commit: 1173687801b5ab1e996f1aef21b760318e5da8c9
https://github.com/llvm/llvm-project/commit/1173687801b5ab1e996f1aef21b760318e5da8c9
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlan.cpp
M llvm/lib/Transforms/Vectorize/VPlanHelpers.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
Log Message:
-----------
[VPlan] Use NeedsSingleScalar consistently for ::get (NFC). (#226494)
IsScalar/IsSingleScalar as used currently may be consfusing, as it could
be read as implying that the VPValue is a single-scalar, see
https://github.com/llvm/llvm-project/pull/226153.
But here it means that the caller only needs a single scalar. Update
wording.
PR: https://github.com/llvm/llvm-project/pull/226494
Commit: b4842bea58e6ca2a3de8692d5214b2441285513d
https://github.com/llvm/llvm-project/commit/b4842bea58e6ca2a3de8692d5214b2441285513d
Author: Alex MacLean <amaclean at nvidia.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-undef.mir
M llvm/test/CodeGen/AMDGPU/call-constant.ll
M llvm/test/CodeGen/AMDGPU/invalid-addrspacecast.ll
M llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-pal.ll
Log Message:
-----------
[GlobalISel] Preserve volatile and ordered atomic stores of undef (#226265)
Guard `erase_undef_store` with `isUnordered()`, matching InstCombine.
Ensures volatile and ordered atomic stores are preserved.
---------
Co-authored-by: Hongyu Chen <hongchen at nvidia.com>
Commit: f9f5ed22a7026261aec0075caa9862953a8a5fe6
https://github.com/llvm/llvm-project/commit/f9f5ed22a7026261aec0075caa9862953a8a5fe6
Author: Joseph Huber <huberjn at outlook.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/runtimes/CMakeLists.txt
Log Message:
-----------
[LLVM] Use complete runtime dependency list for multilibs (#226580)
Summary:
The current handling makes the multilib job depend on the base runtimes
job. This means that we will potentially depend on things that don't
necessarily need to be built to fulfil the multilibs job. Instead, just
depend on the individual targets for that multilib.
Commit: 91d0e2e91e2dc4c4729cbe911f67388453ee509d
https://github.com/llvm/llvm-project/commit/91d0e2e91e2dc4c4729cbe911f67388453ee509d
Author: Jason Van Beusekom <jason.van-beusekom at hpe.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M offload/include/Shared/SourceInfo.h
M offload/test/offloading/info.c
M openmp/docs/ReleaseNotes.md
Log Message:
-----------
[Offload][OpenMP] remove SourceInfo::removePath (#226586)
This Pr is the same as https://github.com/llvm/llvm-project/pull/226283
(which was reverted in https://github.com/llvm/llvm-project/pull/226557)
This Pr is the same as https://github.com/llvm/llvm-project/pull/226283
but with an update to info.c to account for the new full path output.
Commit: 5f3a611fa194ca76c91d3889adb68532cef44cee
https://github.com/llvm/llvm-project/commit/5f3a611fa194ca76c91d3889adb68532cef44cee
Author: Jackson Stogel <jtstogel at gmail.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M utils/bazel/MODULE.bazel.lock
M utils/bazel/linux_uapi.bzl
Log Message:
-----------
[bazel] Download linux UAPI headers when no local dir is set (#216868)
This PR defines a hermetic source for `@linux_api//:linux_uapi_headers`
that will be used in CI. If no `LINUX_UAPI_INCLUDE_DIR` value is
specified, then Bazel will download the linux-libc-dev debian package
and use its headers.
I originally wanted to pull from https://github.com/torvalds/linux and
build UAPI headers from source as it gives more control, but the repo is
rather large and took ~20s to download and ~10s to build. Using the
debian package's headers is closer to what the LLVM-libc fullbuild CI
[currently
does](https://github.com/llvm/llvm-project/blob/007551bacb899a409218574908d96b0633d52018/.github/workflows/containers/libc/Dockerfile#L38)
and is very fast.
Commit: c4195f63a560990bdb854357d66f759259bf1d3e
https://github.com/llvm/llvm-project/commit/c4195f63a560990bdb854357d66f759259bf1d3e
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M mlir/docs/Interfaces.md
M mlir/include/mlir/Dialect/OpenMP/OpenMPOpsInterfaces.td
M mlir/test/mlir-tblgen/op-interface.td
M mlir/tools/mlir-tblgen/OpInterfacesGen.cpp
Log Message:
-----------
[mlir][ODS] Share operation interface methods with raw-op bodies (NFC) (#226317)
Allow an operation interface method to use a shared callback when its
body only needs the raw Operation. Use it for OpenMP block-argument
indexing and slicing methods, avoiding per-operation wrappers while
preserving the existing fallback and external model paths.
Reduces the size of the OpenMP dialect text section by 1.68%.
Assisted-by: Codex
Commit: 7fbfd203131aa597c63d89e45392454280f89cfa
https://github.com/llvm/llvm-project/commit/7fbfd203131aa597c63d89e45392454280f89cfa
Author: Med Ismail Bennani <ismail at bennani.ma>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M lldb/include/lldb/Utility/StructuredData.h
M lldb/source/Commands/CommandObjectVersion.cpp
M lldb/source/Utility/StructuredData.cpp
Log Message:
-----------
[lldb] Add StructuredData::Dictionary::ForEachSorted (NFC) (#226597)
`Dictionary::Serialize`, `Dictionary::GetDescription` and the build
configuration dump in `CommandObjectVersion` each collect the
dictionary's keys and sort them before iterating, so that the output
doesn't depend on StringMap's ordering. Factor that into a new
`ForEachSorted` method.
Signed-off-by: Med Ismail Bennani <ismail at bennani.ma>
Commit: 5cab2963e13496c272a482145b11796e9e26eeb4
https://github.com/llvm/llvm-project/commit/5cab2963e13496c272a482145b11796e9e26eeb4
Author: Demetrios Chiuratto Agourakis <demetrios at agourakis.med.br>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
M llvm/test/CodeGen/X86/llvm.frexp.ll
Log Message:
-----------
[SelectionDAG] Fix result index and vector width in unrollExpandedOp (#225886)
Fixes #224127.
In `DAGTypeLegalizer::WidenVectorResult`, `unrollExpandedOp` computes
the unroll count and widened vector type from the result being legalized
(`ResNo`) rather than unconditionally using result 0. For multi-result
nodes where result types differ (e.g. `ISD::FFREXP`), this prevents
mismatched vector widths and preserves the correct result index from
`DAG.UnrollVectorOp`.
Assisted-by: Claude
---------
Co-authored-by: Demetrios Chiuratto Agourakis <agourakis82 at gmail.com>
Commit: 5aa8fcc29bc47056411b3d23b0e7acc981ec3934
https://github.com/llvm/llvm-project/commit/5aa8fcc29bc47056411b3d23b0e7acc981ec3934
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/rvv/trunc-select-to-max-usat.ll
Log Message:
-----------
[RISCV] Support swapped select operands in combineTruncSelectToSMaxUSat. (#226584)
Handle (trunc (vselect (setugt X, 2^N-1), (sext (setgt X, 0)), X)) in
addition to the existing (trunc (vselect (setult X, 2^N), X,
(sext (setgt X, 0)))) form.
Co-Authored-By: Claude Opus 5.5 (1M context) <noreply at anthropic.com>
Commit: 7e91ef5d6aeaa7191a9354ddcff67d84bd8aebaf
https://github.com/llvm/llvm-project/commit/7e91ef5d6aeaa7191a9354ddcff67d84bd8aebaf
Author: Michael G. Kazakov <mike.kazakov at gmail.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M libcxx/include/CMakeLists.txt
M libcxx/include/__algorithm/pstl.h
M libcxx/include/__pstl/backend_fwd.h
M libcxx/include/__pstl/backends/default.h
M libcxx/include/__pstl/backends/libdispatch.h
M libcxx/include/__pstl/backends/serial.h
M libcxx/include/__pstl/backends/std_thread.h
A libcxx/include/__pstl/cpu_algos/swap_ranges.h
M libcxx/include/module.modulemap.in
M libcxx/test/libcxx/algorithms/pstl.iterator-requirements.verify.cpp
A libcxx/test/std/algorithms/alg.modifying.operations/alg.swap/pstl.swap_ranges.pass.cpp
M libcxx/test/std/algorithms/pstl.exception_handling.pass.cpp
Log Message:
-----------
[libc++][pstl] Implementation of parallel std::swap_ranges() based on parallel __for_each (#224967)
This PR adds an implementation of parallel `std::swap_ranges()` based on
`__parallel_for_each_iter_pair()`.
The implementation is effectively a one-liner, but has to deal with
iterator ranges, thus is located in `cpu_algos`:
```c++
__pstl::__parallel_for_each_iter_pair<_Backend>(
first1, last1, first2,
[](ForwardIterator1 brick_first1, ForwardIterator1 brick_last1, ForwardIterator2 brick_first2) {
std::swap_ranges(std::move(brick_first1), std::move(brick_last1), std::move(brick_first2));
});
```
Part of #99938
Commit: 7fc4f276a4d0a4b1f968003d863ee50dc9ebcedd
https://github.com/llvm/llvm-project/commit/7fc4f276a4d0a4b1f968003d863ee50dc9ebcedd
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M flang/lib/Parser/openacc-parsers.cpp
M flang/test/Parser/acc-label-do.f90
Log Message:
-----------
[flang][openacc] Build full shared-label DO nests in AccNonBlockDoConstruct (#225997)
When an `!$acc loop` is associated with a labeled DO,
AccNonBlockDoConstruct
turned only that outer loop into a DoConstruct and left sibling
LabelDoStmts
that share the same terminator for later CanonicalizeDo. An inner `!$acc
loop`
then swallowed the shared terminator into its own DoConstruct, so
AnalyzeLabels (which runs before CanonicalizeDo) rejected the remaining
LabelDoStmts with "Label 'N' is not in DO loop scope".
Recurse on nested LabelDoStmts while parsing the associated loop so the
whole shared-label nest is a DoConstruct before label analysis. Add a
parser test where only the outer and innermost loops have LOOP
directives.
Commit: ce8e98386b89cf25065349c0e8147f839afda5dd
https://github.com/llvm/llvm-project/commit/ce8e98386b89cf25065349c0e8147f839afda5dd
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M mlir/include/mlir/Dialect/Linalg/IR/LinalgInterfaces.td
M mlir/include/mlir/Dialect/OpenACC/OpenACCOpsInterfaces.td
M mlir/include/mlir/Dialect/OpenMP/OpenMPOpsInterfaces.td
M mlir/include/mlir/Dialect/SparseTensor/IR/SparseTensorInterfaces.td
M mlir/include/mlir/Dialect/WasmSSA/IR/WasmSSAInterfaces.td
M mlir/include/mlir/Interfaces/ControlFlowInterfaces.td
Log Message:
-----------
[mlir][Interfaces] Share more operation interface bodies (NFC) (#226603)
Use raw operation access for methods that do not depend on the concrete
operation type. Keep typed access where operation-specific APIs are
needed.
This save a little bit of code size and improves build time.
Assisted-by: Codex
Commit: b5426c132f47b14874de7ce26a4e1bca80182e4c
https://github.com/llvm/llvm-project/commit/b5426c132f47b14874de7ce26a4e1bca80182e4c
Author: Lang Hames <lhames at gmail.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M orc-rt/include/orc-rt-c/support/Logging.h
M orc-rt/test/unit/support/LoggingTest.cpp
Log Message:
-----------
[orc-rt] Add ORC_RT_LOG_ENABLED macro. (#226500)
ORC_RT_LOG_ENABLED(Level) reports whether log sites at the given level
are compiled in, taking into account both the backend and the
ORC_RT_LOG_LEVEL floor. It takes the same level token as ORC_RT_LOG and
can be used in preprocessor conditionals, allowing code that relies on
logging to surface something important (e.g. a logging error reporter)
to choose an alternative when logging is compiled out.
Commit: f739fbc831cbd670b9dc3044a492240cfede20c3
https://github.com/llvm/llvm-project/commit/f739fbc831cbd670b9dc3044a492240cfede20c3
Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
A llvm/test/Transforms/LoopVectorize/AArch64/diff-checks-force-interleave-count.ll
Log Message:
-----------
[LV] Honor -force-vector-interleave when generating diff checks (#225768)
We use both IC and UserIC in the checks below. However, once those
checks are done, UserIC will always override IC if it's non-zero. That
means using the max is unnecessary and can result in overly conservative
checks when UserIC < IC.
Commit: 201e76d4559e9d8acdfec1c202df8f2269acbd8b
https://github.com/llvm/llvm-project/commit/201e76d4559e9d8acdfec1c202df8f2269acbd8b
Author: Changpeng Fang <changpeng.fang at amd.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/CodeGen/DetectDeadLanes.cpp
A llvm/test/CodeGen/AMDGPU/detect-dead-lanes-reg-sequence-narrow-slot.mir
M llvm/test/CodeGen/AMDGPU/frem.ll
A llvm/test/CodeGen/AMDGPU/true16-uniform-f16-phi-copysign.ll
Log Message:
-----------
[CodeGen] Fix DetectDeadLanes for same-class copies with mismatched widths (#226556)
isCrossCopy() returned early whenever source and destination shared a
register class, treating the transfer as lane-for-lane. That is wrong
when a REG_SEQUENCE names a subregister slot narrower than the source
operand, e.g. a 32-bit vreg used as the lo16 piece of another 32-bit
vreg. Only take the early exit when the two widths match; otherwise fall
through to findCommonRegClass().
Fixes: ROCM-31212
Commit: 3a2787d5ca6ba0271f7203997f8a9b65679398a4
https://github.com/llvm/llvm-project/commit/3a2787d5ca6ba0271f7203997f8a9b65679398a4
Author: Lang Hames <lhames at gmail.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M orc-rt/include/orc-rt-c/config.h.in
M orc-rt/include/orc-rt-c/support/Logging.h
Log Message:
-----------
[orc-rt] Move ORC_RT_LOG_ENABLED into config.h. (#226617)
ORC_RT_LOG_ENABLED depends only on the logging configuration values
defined in config.h, but was defined in Logging.h, so checking whether a
log level is compiled in required pulling in the logging backend's
headers (e.g. <os/log.h>).
This commit moves ORC_RT_LOG_ENABLED (and its level-token aliases) into
config.h, so that headers can check the logging configuration without
including Logging.h.
Commit: f8c2918d49d3a3803ae3c9e1b6c216b24db9ad51
https://github.com/llvm/llvm-project/commit/f8c2918d49d3a3803ae3c9e1b6c216b24db9ad51
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
A llvm/test/Transforms/SLPVectorizer/AArch64/ordered-reduction-of-loads.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/ordered-reduction.ll
Log Message:
-----------
[SLP][NFC]Add extra test for reductions vectorization, NFC
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/226618
Commit: 90c150f868adb53b45dbf7489e93a23c22f6b6b3
https://github.com/llvm/llvm-project/commit/90c150f868adb53b45dbf7489e93a23c22f6b6b3
Author: Fangrui Song <i at maskray.me>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M clang/tools/clang-format/ClangFormat.cpp
M llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
M llvm/lib/Target/AArch64/AArch64CodeLayoutOpt.cpp
Log Message:
-----------
Replace cl::bits with cl::list. NFC (#226399)
cl::bits packs enum values into an unsigned, which would block migration
to TableGen based representation. The three users only test membership.
LLM-aided
Commit: 0b61b734cf84a19491f4bcb61e04956995807051
https://github.com/llvm/llvm-project/commit/0b61b734cf84a19491f4bcb61e04956995807051
Author: Fangrui Song <i at maskray.me>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M clang-tools-extra/clangd/tool/ClangdMain.cpp
Log Message:
-----------
[clangd] Report retired flags after parsing (#226360)
cl::callback will be removed to enable migration to TableGen
https://discourse.llvm.org/t/rfc-declare-library-command-line-options-in-tablegen-one-struct-per-library/91877/3
LLM-aided
Commit: ab08c75ffe0a40626a4dc62ed010d6e3ceece056
https://github.com/llvm/llvm-project/commit/ab08c75ffe0a40626a4dc62ed010d6e3ceece056
Author: Fangrui Song <i at maskray.me>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M bolt/lib/Passes/BinaryPasses.cpp
M bolt/lib/Passes/ReorderFunctions.cpp
M bolt/lib/Profile/DataAggregator.cpp
Log Message:
-----------
[BOLT] Remove cl::callback uses (#226359)
cl::callback will be removed to enable migration to TableGen based
representation.
https://discourse.llvm.org/t/rfc-declare-library-command-line-options-in-tablegen-one-struct-per-library/91877/3
LLM-aided
Commit: e59a0c697552ae7d1c3aeed5774e829cdc5e16b5
https://github.com/llvm/llvm-project/commit/e59a0c697552ae7d1c3aeed5774e829cdc5e16b5
Author: Lang Hames <lhames at gmail.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M orc-rt/include/orc-rt/bedrock/Session.h
M orc-rt/lib/bedrock/Session.cpp
M orc-rt/test/unit/CommonTestUtils.h
M orc-rt/test/unit/bedrock/InProcessControllerAccessTest.cpp
M orc-rt/test/unit/bedrock/SessionTest.cpp
M orc-rt/tools/ogre/ogre.cpp
Log Message:
-----------
[orc-rt] Pass the reporting Session to Session error reporters. (#226622)
Session error reporters previously received only the Error, and had to
be supplied to the Session constructor, so they had no direct way to
refer to the Session reporting the error (e.g. to include its address in
a log message).
This commit changes ErrorReporterFn to take the reporting Session along
with the Error, and adds a Session::logErrors reporter that logs errors
via ORC_RT_LOG at Error level in the Session category. logErrors is only
available when Error-level logging is compiled in
(ORC_RT_LOG_ENABLED(Error)), so that it can't silently discard errors in
configurations where logging is compiled out. The noErrors and
AccumulateErrors test helpers are updated to work as both plain and
Session error reporters.
Commit: 240a9cb75dd9210cae8e987700d0ef6537b723cb
https://github.com/llvm/llvm-project/commit/240a9cb75dd9210cae8e987700d0ef6537b723cb
Author: Twice <twice at apache.org>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M mlir/python/mlir/dialects/ext.py
M mlir/test/python/dialects/ext.py
Log Message:
-----------
[MLIR][Python] Allow `Attribute` to denote unconstrained attributes in Python-defined ops (#224679)
Operation definitions support attribute constraints such as
`IntegerAttr`, `StringAttr`, and `IntegerAttr | StringAttr`, but
currently reject `Attribute` itself.
This change allows `Attribute` to denote an unconstrained attribute,
accepting both built-in and Python-defined attributes:
```python
class MyOp(MyDialect.Operation, name="my_op"):
arg: Operand
attr: Attribute
res: Result
```
This complements the unconstrained `Operand` and `Result` annotations
introduced in #220216. The annotation also works with `attribute()`
field specifiers, including `kw_only` and `default_factory`.
Assisted-by: Codex / GPT6
Commit: 163950475fc724cd5d62e868bdb46ba0c39e5519
https://github.com/llvm/llvm-project/commit/163950475fc724cd5d62e868bdb46ba0c39e5519
Author: Steffen Larsen <sholstla at amd.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M clang/include/clang/CIR/Dialect/Builder/CIRBaseBuilder.h
M clang/lib/CIR/CodeGen/CIRGenDecl.cpp
M clang/test/CIR/CodeGenCUDA/address-spaces.cu
Log Message:
-----------
[CIR] Attach address space to global variables (#226455)
Signed-off-by: Steffen Holst Larsen <sholstla at amd.com>
Commit: 60059de6eb6d647857ac55b48d465580aa3ecdc5
https://github.com/llvm/llvm-project/commit/60059de6eb6d647857ac55b48d465580aa3ecdc5
Author: A. Jiang <de34 at live.cn>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M libcxx/include/__ranges/adjacent_transform_view.h
M libcxx/include/__ranges/adjacent_view.h
M libcxx/include/__ranges/chunk_by_view.h
M libcxx/include/__ranges/common_view.h
M libcxx/include/__ranges/concat_view.h
M libcxx/include/__ranges/counted.h
M libcxx/include/__ranges/drop_view.h
M libcxx/include/__ranges/drop_while_view.h
M libcxx/include/__ranges/elements_view.h
M libcxx/include/__ranges/empty_view.h
M libcxx/include/__ranges/enumerate_view.h
M libcxx/include/__ranges/filter_view.h
M libcxx/include/__ranges/iota_view.h
M libcxx/include/__ranges/join_view.h
M libcxx/include/__ranges/join_with_view.h
M libcxx/include/__ranges/lazy_split_view.h
M libcxx/include/__ranges/movable_box.h
M libcxx/include/__ranges/non_propagating_cache.h
M libcxx/include/__ranges/rbegin.h
M libcxx/include/__ranges/rend.h
M libcxx/include/__ranges/reverse_view.h
M libcxx/include/__ranges/single_view.h
M libcxx/include/__ranges/split_view.h
M libcxx/include/__ranges/stride_view.h
M libcxx/include/__ranges/take_view.h
M libcxx/include/__ranges/take_while_view.h
M libcxx/include/__ranges/to.h
M libcxx/include/__ranges/transform_view.h
M libcxx/include/__ranges/views.h
M libcxx/include/__ranges/zip_transform_view.h
M libcxx/include/__ranges/zip_view.h
Log Message:
-----------
[libc++][NFC] Avoid empty namespace in internal headers of `<ranges>` (#226034)
...in pre-C++20/23 modes. This follows up
0c94a978df783bd67535350eac84088fc482716a and fixes more complaints from
clang-tidy checks in CI.
Commit: 18af9ef08eec59d1bce7b941f164ba3f866acf59
https://github.com/llvm/llvm-project/commit/18af9ef08eec59d1bce7b941f164ba3f866acf59
Author: Douglas Yung <douglas.yung at sony.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M clang/docs/ReleaseNotes.md
M clang/lib/Sema/SemaOpenMP.cpp
R clang/test/OpenMP/error_message.c
M clang/test/OpenMP/error_message.cpp
M clang/test/OpenMP/parallel_message_messages.cpp
Log Message:
-----------
Revert "[clang][OpenMP] Only accept char strings in the message clause" (#226636)
Reverts llvm/llvm-project#226080
The newly added test error_message.c is failing on the PS4 bot
https://lab.llvm.org/buildbot/#/builders/144/builds/66294
Commit: e0316c1b4762263caa49e3c41ddde752a2b6b775
https://github.com/llvm/llvm-project/commit/e0316c1b4762263caa49e3c41ddde752a2b6b775
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M clang/lib/AST/ByteCode/ByteCodeEmitter.h
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ByteCode/Context.cpp
M clang/lib/AST/ByteCode/Disasm.cpp
M clang/lib/AST/ByteCode/EvalEmitter.cpp
M clang/lib/AST/ByteCode/EvalEmitter.h
M clang/lib/AST/ByteCode/EvaluationResult.cpp
M clang/lib/AST/ByteCode/EvaluationResult.h
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/InterpBuiltinObjectSize.cpp
M clang/lib/AST/ByteCode/Pointer.cpp
M clang/lib/AST/ByteCode/Pointer.h
M clang/lib/AST/ExprConstShared.h
M clang/lib/AST/ExprConstant.cpp
M clang/test/AST/ByteCode/builtin-functions.cpp
M clang/test/AST/ByteCode/codegen-constexpr-unknown.cpp
M clang/test/AST/ByteCode/references.cpp
M clang/test/CodeGenCXX/global-init.cpp
M clang/test/SemaCXX/PR19955.cpp
M clang/test/SemaCXX/cxx2c-expansion-stmts.cpp
Log Message:
-----------
Revert "[clang][bytecode] Stop relying on `CheckEvaluationResult()` (… (#226637)
…#186045)"
This reverts commit 55b498466a7b2620d09fcdf1b2300f71a35f6d8b.
This breaks two msan builders and reproducing the failure locally takes
forever.
Commit: 6a37cee09997b28c6cc708dd36b283bbd5bd7147
https://github.com/llvm/llvm-project/commit/6a37cee09997b28c6cc708dd36b283bbd5bd7147
Author: asudarsa-qti <asudarsa at qti.qualcomm.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M clang/lib/Interpreter/IncrementalAction.cpp
A clang/test/Interpreter/nonexistent-xcc-file.cpp
Log Message:
-----------
Fix for a clang-repl crash when passing non-existent file to --Xcc (#225861)
Problem: When clang-repl fails to initialize because an --Xcc file does
not exist, Interpreter::create() destroys the partially initialized
Interpreter. Its destructor unconditionally calls FinalizeAction(),
which invokes FrontendAction::EndSourceFile() without a registered
CompilerInstance and triggers an assertion.
Fix: Track whether interpreter initialization completed successfully and
only finalize the frontend action for successfully initialized
interpreters.
Test: Add a regression test covering a nonexistent --Xcc file.
This change resolves https://github.com/llvm/llvm-project/issues/225429
Assisted by gpt-5.6-luna
---------
Co-authored-by: Anutosh Bhat <andersonbhat491 at gmail.com>
Commit: c4896792fb97b2ad237c5c404cdda2d0cd4fcf61
https://github.com/llvm/llvm-project/commit/c4896792fb97b2ad237c5c404cdda2d0cd4fcf61
Author: Med Ismail Bennani <ismail at bennani.ma>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M lldb/include/lldb/Target/Process.h
M lldb/source/API/SBProcess.cpp
M lldb/source/Target/Process.cpp
M lldb/test/API/python_api/process/address-masks/TestAddressMasks.py
Log Message:
-----------
[lldb] Rebuild stack frames when a process address mask changes (#224989)
Commit: 4257da8ee2e84b3e62d2a2a5010e81823b799805
https://github.com/llvm/llvm-project/commit/4257da8ee2e84b3e62d2a2a5010e81823b799805
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
A llvm/test/Transforms/LoopVectorize/AArch64/low-trip-count-fixed-vf-no-epilogue.ll
M llvm/test/Transforms/LoopVectorize/RISCV/short-trip-count.ll
Log Message:
-----------
[LV] Always try to use fixed VF for low TC loops if no epilogue allowed. (#226318)
Remove the MaxPowerOf2RuntimeVF gate for falling back to using fixed
width VFs when no epilogue is allowed and the trip count is below the
minimum for tail folding.
MaxPowerOf2RuntimeVF being not set means we cannot compute the maximum
runtime VF, due to missing max vscale. In that case we are not able to
determine if a epilogue loop remains for scalable VFs, but we can still
pick a fixed VF, if no epilogue remains for it.
Also updates processLoop to ignore CM_EpilogueNotNeededFoldTail, if the
trip count is below the tail-folding threshold.
PR: https://github.com/llvm/llvm-project/pull/226318
Commit: 825903711948134578537eda6dd94a488ed50319
https://github.com/llvm/llvm-project/commit/825903711948134578537eda6dd94a488ed50319
Author: Lang Hames <lhames at gmail.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M orc-rt/include/orc-rt/support/bind.h
M orc-rt/test/unit/support/bind-test.cpp
Log Message:
-----------
[orc-rt] make bind_front match std::bind_front semantics. (#226646)
orc_rt::bind_front stands in for std::bind_front until the ORC runtime
can use C++20, so code written against it should keep working after the
switch. This commit brings its behavior in line with std::bind_front:
- noexcept propagation
- const and rvalue call operators, forwarding the wrapper's qualifiers
- no fallback to a differently-qualified call operator
- reference return types
- member pointers
- copyable wrappers, including nested binds
The unit tests are reorganized and extended to cover these.
Assisted-by: Claude
Commit: 0b4f72d00bdd2ef1707c5098d12936bfa159b414
https://github.com/llvm/llvm-project/commit/0b4f72d00bdd2ef1707c5098d12936bfa159b414
Author: Aditya Sinha <155882262+AdityaSinha149 at users.noreply.github.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M clang/include/clang/CodeGen/CodeGenAction.h
M clang/include/clang/Interpreter/Interpreter.h
M clang/lib/CodeGen/BackendConsumer.h
M clang/lib/CodeGen/CodeGenAction.cpp
M clang/lib/Interpreter/DeviceOffload.cpp
M clang/lib/Interpreter/DeviceOffload.h
M clang/lib/Interpreter/Interpreter.cpp
M clang/unittests/Basic/CMakeLists.txt
A clang/unittests/Basic/TargetIDTest.cpp
Log Message:
-----------
[clang-repl] Implement IncrementalHIPDeviceParser for HIP device compilation (#218337)
This PR implements the IncrementalHIPDeviceParser. It takes each
incremental statement's device code and lowers it all the way to a
loadable HIP fat binary: linking the ROCm device libraries, running the
AMDGPU optimization/codegen pipeline, producing a .hsaco code object,
and embedding it as __hip_fatbin for the host runtime to register and
launch.
This PR only adds the parser class, wiring it into Interpreter.cpp and
the end-to-end tests will come in a follow-up.
Assisted by Claude Opus 4.8
Commit: 5f609f950d2e80addf5566623013db68394334db
https://github.com/llvm/llvm-project/commit/5f609f950d2e80addf5566623013db68394334db
Author: Fangrui Song <i at maskray.me>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M llvm/docs/CommandLine.md
M llvm/include/llvm/Support/CommandLine.h
M llvm/unittests/Support/CommandLineTest.cpp
Log Message:
-----------
[Support] Remove cl::bits (#226628)
cl::list covers the same use, and cl::bits would block migration to
TableGen based representation.
LLM-aided
Commit: c0b6ee14c2f8dece229da557352e116f9a6d7064
https://github.com/llvm/llvm-project/commit/c0b6ee14c2f8dece229da557352e116f9a6d7064
Author: David Green <david.green at arm.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
A llvm/test/CodeGen/AArch64/sve-fixed-length-shuffle-reverse.ll
Log Message:
-----------
[AArch64] Add tests for sve fixed length reverse shuffles. NFC (#226661)
Commit: 96b5cc3d836494c56c8d5ae1e73e90864eb19a5d
https://github.com/llvm/llvm-project/commit/96b5cc3d836494c56c8d5ae1e73e90864eb19a5d
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M llvm/include/llvm/Analysis/BranchProbabilityInfo.h
M llvm/lib/Analysis/BranchProbabilityInfo.cpp
Log Message:
-----------
[BPI] Add getEdgeProbabilitiesFromWeights (NFC). (#226560)
Move computing edge probabilities from branch weights to a static
helper. This allows re-using the core logic when computing execution
frequencies in VPlan, fixing a number of subtle differences.
While touching the code, also modernize the code slightly.
Note that the helper does not handle the case where all successors are
unreachable. This would need additional info and is not needed for the
VPlan case.
PR: https://github.com/llvm/llvm-project/pull/226560
Commit: 97e9558844822e1ff8f986319ef354fda42b8215
https://github.com/llvm/llvm-project/commit/97e9558844822e1ff8f986319ef354fda42b8215
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M llvm/lib/CodeGen/DetectDeadLanes.cpp
R llvm/test/CodeGen/AMDGPU/detect-dead-lanes-reg-sequence-narrow-slot.mir
M llvm/test/CodeGen/AMDGPU/frem.ll
R llvm/test/CodeGen/AMDGPU/true16-uniform-f16-phi-copysign.ll
Log Message:
-----------
Revert "[CodeGen] Fix DetectDeadLanes for same-class copies with mismatched widths" (#226665)
Reverts llvm/llvm-project#226556
This is handling malformed IR and adding size based instead of register
class based reasoning
Commit: d94f3a52dad756d7354a9ca688b4ac76a97b9d38
https://github.com/llvm/llvm-project/commit/d94f3a52dad756d7354a9ca688b4ac76a97b9d38
Author: Lang Hames <lhames at gmail.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M orc-rt/test/unit/CMakeLists.txt
R orc-rt/test/unit/bedrock/SocketConnectorTest.cpp
M orc-rt/test/unit/bedrock/SocketTestUtils.h
M orc-rt/test/unit/bedrock/sps/SimpleRemoteCAOverSocketTest.cpp
A orc-rt/test/unit/bedrock/sys/posix/SocketConnectorTest.cpp
M orc-rt/test/unit/bedrock/sys/posix/SocketTestUtils.cpp
Log Message:
-----------
[orc-rt] Make socket unit tests portable; build them on POSIX. (#226662)
SimpleRemoteCAOverSocketTest.cpp tests a POSIX-only implementation, so
move it to the POSIX source list. Its tests are portable, so move the
fixture's POSIX code into SocketTestUtils (makeStreamSocketPair,
sendAll, recvAll, makeNativeNonStreamSocket) rather than moving the file
under sys/posix; a Windows transport will need only Windows definitions
of those helpers.
makeStreamSocketPair documents the properties the tests rely on beyond a
connected stream pair: neither direction buffers StallingPayloadSize
bytes, and closing an end delivers what it already sent even if it has
unread data. AF_UNIX provides both; a loopback TCP pair may not.
SocketConnectorTest.cpp tests fd adoption with pipe and fcntl, so it is
a test of the POSIX implementation: move it to sys/posix/.
Assisted-by: Claude
Commit: a4e311d3f80f0bc1b0912d3f9f650a8d949a06e5
https://github.com/llvm/llvm-project/commit/a4e311d3f80f0bc1b0912d3f9f650a8d949a06e5
Author: Lang Hames <lhames at gmail.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M llvm/lib/ExecutionEngine/Orc/ELFNixPlatform.cpp
M llvm/lib/ExecutionEngine/Orc/MachOPlatform.cpp
Log Message:
-----------
[ORC] Call createPThreadKey through a Proxy in MachO/ELFNixPlatform (#226656)
Replace the callSPSWrapper calls in MachOPlatform::createPThreadKey and
ELFNixPlatform::createPThreadKey with a Proxy built over the address
recorded during bootstrap, using a local CI descriptor for each
platform's create_pthread_key wrapper. The address stays in the
platforms' RuntimeFunction table, which is filled uniformly by the
bootstrap recording pass.
Commit: 0407861c32056a8ac57de2d7ef304ebbb3922139
https://github.com/llvm/llvm-project/commit/0407861c32056a8ac57de2d7ef304ebbb3922139
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M llvm/lib/Target/Mips/MipsAsmPrinter.cpp
M llvm/lib/Target/Mips/MipsAsmPrinter.h
M llvm/lib/Target/Mips/MipsBranchExpansion.cpp
M llvm/lib/Target/Mips/MipsCallLowering.cpp
M llvm/lib/Target/Mips/MipsFastISel.cpp
M llvm/lib/Target/Mips/MipsISelLowering.cpp
M llvm/lib/Target/Mips/MipsMachineFunction.cpp
M llvm/lib/Target/Mips/MipsRegisterInfo.cpp
M llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
M llvm/lib/Target/Mips/MipsSERegisterInfo.cpp
Log Message:
-----------
Mips: Route ABI queries through the subtarget (#226667)
Commit: e7019f85692bab245c02f4fa433b37105f2d9c0d
https://github.com/llvm/llvm-project/commit/e7019f85692bab245c02f4fa433b37105f2d9c0d
Author: Ivan Ho <ivan.ho at cl.cam.ac.uk>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M mlir/lib/Dialect/IRDL/IR/IRDL.cpp
M mlir/lib/Target/IRDLToCpp/IRDLToCpp.cpp
M mlir/test/lib/Dialect/TestIRDLToCpp/test_irdl_to_cpp.irdl.mlir
Log Message:
-----------
[MLIR][IRDL] Instantiate "." in IRDL-defined names as nested namespaces (#207035)
In PR #187911, it was revealed that the constraints on IRDL op names
placed by irdl-to-cpp were too restrictive.
This PR will address that by allowing "." in operation names to denote
nested namespaces, but not "$".
To discuss:
- ops like `wmma.f16.16x16x64.bf8_bf` cannot be registered as C++
identifiers cannot begin with a number. In discussions, we have opted to
prefix the generated namespaces with _.
Codex was used to generate the lit tests.
Close #187911.
Assisted-by: OpenAI Codex (GPT-5 and 6)
Commit: e8e4a54cfbbc054ec9801dea03e6c6868bf0708a
https://github.com/llvm/llvm-project/commit/e8e4a54cfbbc054ec9801dea03e6c6868bf0708a
Author: David Green <david.green at arm.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/test/CodeGen/AArch64/sve-fixed-length-shuffle-reverse.ll
Log Message:
-----------
[AArch64] Use SVE rev for full reverse shuffles with SVE128 (#224589)
When the vscale_range is always 1, we can make use of the SVE rev
instruction to perform a full 128bit vector reverse.
Sidesteps #223597 for SVE128
Commit: fccc8632f21fa8a13f7962932b614e8c1079d9ac
https://github.com/llvm/llvm-project/commit/fccc8632f21fa8a13f7962932b614e8c1079d9ac
Author: Lang Hames <lhames at gmail.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M orc-rt/include/orc-rt/bedrock/sps/SimpleRemoteCAOverSocket.h
M orc-rt/lib/bedrock/sys/posix/sps/SimpleRemoteCAOverSocket.cpp
M orc-rt/test/unit/bedrock/sps/SimpleRemoteCAOverSocketTest.cpp
Log Message:
-----------
[orc-rt] SimpleRemoteCAOverSocket: require a stream socket. (#226676)
SimpleRemote framing reads each message in as many parts as the socket
delivers it, which a socket that preserves message boundaries (datagram,
seqpacket) would truncate. Check SO_TYPE up front and reject anything
but SOCK_STREAM; the socket is owned by then, so it is closed on
failure.
Assisted-by: Claude
Commit: e9e27436e89127e5e42863cc6804945b3619b015
https://github.com/llvm/llvm-project/commit/e9e27436e89127e5e42863cc6804945b3619b015
Author: Ben Shi <2283975856 at qq.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M llvm/lib/Target/AVR/AVRAsmPrinter.cpp
M llvm/lib/Target/AVR/AVRDevices.td
M llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp
M llvm/lib/Target/AVR/AVRISelLowering.cpp
M llvm/lib/Target/AVR/AVRInstrInfo.cpp
M llvm/lib/Target/AVR/AVRInstrInfo.td
M llvm/lib/Target/AVR/AVRRegisterInfo.cpp
M llvm/lib/Target/AVR/MCTargetDesc/AVRMCAsmInfo.cpp
M llvm/lib/Target/AVR/MCTargetDesc/AVRMCTargetDesc.h
R llvm/lib/Target/AVR/TODO.md
Log Message:
-----------
[AVR][NFC] Improve some comment messages (#226423)
Commit: c495a9b796c46456e523a5eeb3690415ba99f5db
https://github.com/llvm/llvm-project/commit/c495a9b796c46456e523a5eeb3690415ba99f5db
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M clang/include/clang/CIR/Dialect/IR/CIRDialect.td
M flang/include/flang/Optimizer/Dialect/CUF/CUFDialect.td
M flang/include/flang/Optimizer/Dialect/FIRCG/CGOps.td
M flang/include/flang/Optimizer/Dialect/FIRDialect.td
M flang/include/flang/Optimizer/Dialect/MIF/MIFDialect.td
M flang/include/flang/Optimizer/HLFIR/HLFIROpBase.td
M mlir/docs/DefiningDialects/Operations.md
M mlir/docs/DefiningDialects/_index.md
M mlir/docs/ReleaseNotes.md
M mlir/examples/toy/Ch4/include/toy/Ops.td
M mlir/examples/toy/Ch5/include/toy/Ops.td
M mlir/examples/toy/Ch6/include/toy/Ops.td
M mlir/examples/toy/Ch7/include/toy/Ops.td
M mlir/include/mlir/Dialect/AMDGPU/IR/AMDGPUBase.td
M mlir/include/mlir/Dialect/Affine/IR/AffineOps.td
M mlir/include/mlir/Dialect/Arith/IR/ArithBase.td
M mlir/include/mlir/Dialect/ArmNeon/ArmNeon.td
M mlir/include/mlir/Dialect/ArmSME/IR/ArmSME.td
M mlir/include/mlir/Dialect/ArmSVE/IR/ArmSVE.td
M mlir/include/mlir/Dialect/Async/IR/AsyncDialect.td
M mlir/include/mlir/Dialect/Bufferization/IR/BufferizationBase.td
M mlir/include/mlir/Dialect/Complex/IR/ComplexBase.td
M mlir/include/mlir/Dialect/ControlFlow/IR/ControlFlowOps.td
M mlir/include/mlir/Dialect/DLTI/DLTIBase.td
M mlir/include/mlir/Dialect/EmitC/IR/EmitCBase.td
M mlir/include/mlir/Dialect/Func/IR/FuncOps.td
M mlir/include/mlir/Dialect/GPU/IR/GPUBase.td
M mlir/include/mlir/Dialect/IRDL/IR/IRDL.td
M mlir/include/mlir/Dialect/Index/IR/IndexDialect.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMDialect.td
M mlir/include/mlir/Dialect/LLVMIR/NVVMDialect.td
M mlir/include/mlir/Dialect/LLVMIR/ROCDLDialect.td
M mlir/include/mlir/Dialect/LLVMIR/VCIXOps.td
M mlir/include/mlir/Dialect/LLVMIR/XeVMOps.td
M mlir/include/mlir/Dialect/Linalg/IR/LinalgBase.td
M mlir/include/mlir/Dialect/MLProgram/IR/MLProgramBase.td
M mlir/include/mlir/Dialect/MPI/IR/MPI.td
M mlir/include/mlir/Dialect/Math/IR/MathBase.td
M mlir/include/mlir/Dialect/MemRef/IR/MemRefBase.td
M mlir/include/mlir/Dialect/NVGPU/IR/NVGPU.td
M mlir/include/mlir/Dialect/OpenACC/OpenACCBase.td
M mlir/include/mlir/Dialect/OpenMP/OpenMPDialect.td
M mlir/include/mlir/Dialect/PDL/IR/PDLDialect.td
M mlir/include/mlir/Dialect/PDLInterp/IR/PDLInterpOps.td
M mlir/include/mlir/Dialect/Ptr/IR/PtrDialect.td
M mlir/include/mlir/Dialect/Quant/IR/QuantBase.td
M mlir/include/mlir/Dialect/SCF/IR/SCFOps.td
M mlir/include/mlir/Dialect/SMT/IR/SMTDialect.td
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBase.td
M mlir/include/mlir/Dialect/Shape/IR/ShapeBase.td
M mlir/include/mlir/Dialect/Shard/IR/ShardBase.td
M mlir/include/mlir/Dialect/SparseTensor/IR/SparseTensorBase.td
M mlir/include/mlir/Dialect/Tensor/IR/TensorBase.td
M mlir/include/mlir/Dialect/Tosa/IR/TosaOpBase.td
M mlir/include/mlir/Dialect/Transform/IR/TransformDialect.td
M mlir/include/mlir/Dialect/UB/IR/UBOps.td
M mlir/include/mlir/Dialect/Vector/IR/Vector.td
M mlir/include/mlir/Dialect/WasmSSA/IR/WasmSSABase.td
M mlir/include/mlir/Dialect/X86/X86.td
M mlir/include/mlir/Dialect/XeGPU/IR/XeGPUDialect.td
M mlir/include/mlir/IR/BuiltinDialect.td
M mlir/include/mlir/IR/DialectBase.td
M mlir/test/lib/Dialect/Test/TestDialect.td
M mlir/test/mlir-tblgen/op-format-invalid.td
M mlir/test/mlir-tblgen/op-format.td
M mlir/test/python/python_test_ops.td
Log Message:
-----------
[mlir] Enable strict properties in assembly formats by default (#225742)
Make strict property assembly formats the default and remove redundant
per-dialect settings. Keep legacy test fixtures explicitly opted out and
update the documentation.
Downstream can opt out for now using `let
useStrictPropertiesInAssemblyFormat = 0;` ; This will be removed in a
future release.
Part of #155475
Assisted-by: Codex
Commit: 9f8d812535d90508d9932cc7c7d39756a5e5d2db
https://github.com/llvm/llvm-project/commit/9f8d812535d90508d9932cc7c7d39756a5e5d2db
Author: theRonShark <ron.lieberman at amd.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M clang/include/clang/CodeGen/CodeGenAction.h
M clang/include/clang/Interpreter/Interpreter.h
M clang/lib/CodeGen/BackendConsumer.h
M clang/lib/CodeGen/CodeGenAction.cpp
M clang/lib/Interpreter/DeviceOffload.cpp
M clang/lib/Interpreter/DeviceOffload.h
M clang/lib/Interpreter/Interpreter.cpp
M clang/unittests/Basic/CMakeLists.txt
R clang/unittests/Basic/TargetIDTest.cpp
Log Message:
-----------
Revert "[clang-repl] Implement IncrementalHIPDeviceParser for HIP device compilation" (#226679)
Reverts llvm/llvm-project#218337 buildbot failures
Commit: 10872feadab49e23b8a2ef831dc454b712937ae2
https://github.com/llvm/llvm-project/commit/10872feadab49e23b8a2ef831dc454b712937ae2
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
A llvm/test/Transforms/SLPVectorizer/AArch64/reduced-value-next-to-fused-fmul.ll
A llvm/test/Transforms/SLPVectorizer/AMDGPU/fmul-sunk-into-fadd-block.ll
Log Message:
-----------
[SLP][NFC]Add extra FMA candidates tests, NFC
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/226684
Commit: 8b96ddbf9cb3437ee4e47a9f60dc983a1f2be8d5
https://github.com/llvm/llvm-project/commit/8b96ddbf9cb3437ee4e47a9f60dc983a1f2be8d5
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
A llvm/test/Transforms/SLPVectorizer/X86/trimmed-node-matching-gather-emitted-first.ll
Log Message:
-----------
[SLP]Do not reuse transformed nodes in gathers emitted before their user
Gathers of the users with all scalars used outside the block are emitted
before the user, while the transformed nodes are emitted with the user.
Reusing such a transformed node postponed the gather and moved only the
last instruction of the transformed node buildvector, breaking dominance.
Fixes #226674
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/226687
Commit: ea0493b90c036776652105da246ce3fa56e33901
https://github.com/llvm/llvm-project/commit/ea0493b90c036776652105da246ce3fa56e33901
Author: Balázs Benics <benicsbalazs at gmail.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
A clang/include/clang/ScalableStaticAnalysis/Analyses/VirtualMethodFamily/VirtualMethodFamily.h
M clang/include/clang/ScalableStaticAnalysis/BuiltinAnchorSources.def
M clang/lib/ScalableStaticAnalysis/Analyses/CMakeLists.txt
A clang/lib/ScalableStaticAnalysis/Analyses/VirtualMethodFamily/VirtualMethodEntityExtractor.cpp
A clang/unittests/ScalableStaticAnalysis/Analyses/VirtualMethodFamily/VirtualMethodFamilyExtractorTest.cpp
A clang/unittests/ScalableStaticAnalysis/Analyses/VirtualMethodFamily/VirtualMethodFamilyTestSupport.h
M clang/unittests/ScalableStaticAnalysis/CMakeLists.txt
A clang/unittests/ScalableStaticAnalysis/ParsedAST.h
Log Message:
-----------
[SSAF] Extract the virtual method override relation per TU (#213316)
A virtual call may dispatch to any override of its callee, so a whole-program
analysis cannot reason about a method's parameters and return value in
isolation. It needs to know which method overrides which, and which slots
that relates. Collect this per TU, so a later pass can join the related
slots into families.
JSON serialization lands separately, so the summary is not writable via
`--ssaf-extract-summaries` yet.
§1 of rdar://179151603
Assisted-By: claude
Commit: 2305da864cb3b66e1fe857c3018bf7d94253bb8a
https://github.com/llvm/llvm-project/commit/2305da864cb3b66e1fe857c3018bf7d94253bb8a
Author: Dmitry Sidorov <Dmitry.Sidorov at amd.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
A llvm/test/Transforms/SLPVectorizer/AMDGPU/cross-block-fmul-fadd.ll
Log Message:
-----------
[NFC][SLP][AMDGPU] Precommit a cross-block fmul fadd contraction test (#226609)
Two contract fmuls feed contract fadds in different successors. AMDGPU
sinks such an fmul into the block of its user and fuses the pair, so the
scalar form is one fma per path. Record the current behaviour, the pair
is kept scalar when the fmul is operand 0 of the fadd and paired when it
is operand 1.
Commit: 6b85e67a473ebe127aa31b742adc1fe2d53cb5bf
https://github.com/llvm/llvm-project/commit/6b85e67a473ebe127aa31b742adc1fe2d53cb5bf
Author: Konstantinos Parasyris <koparasy at gmail.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M clang/include/clang/CIR/Dialect/IR/CIRCUDAAttrs.td
M clang/include/clang/CIR/Dialect/IR/CIRDialect.td
M clang/lib/CIR/CodeGen/CIRGenCUDANV.cpp
M clang/lib/CIR/CodeGen/CIRGenModule.cpp
M clang/lib/CIR/Dialect/IR/CIRDialect.cpp
M clang/lib/CIR/Dialect/Transforms/LoweringPrepare.cpp
M clang/test/CIR/CodeGenCUDA/device-stub.cu
A clang/test/CIR/CodeGenCUDA/missing-gpubinary.cu
A clang/test/CIR/Diagnostics/mlir-error-routing.cpp
R clang/test/CIR/Diagnostics/mlir-error-routing.cu
A clang/test/CIR/IR/invalid-cuda-device-binary.cir
Log Message:
-----------
[CIR][CUDA] Read fat binary in CIRGen and store its bytes on the module (#225971)
Two problems with the current implementation of GPU CIR:
1. `LoweringPrepare` read the fat binary from disk, via
`astCtx->getSourceManager().getFileManager().getVirtualFileSystem()`. A
transform pass should not do I/O, and this is one of the `ASTContext`
dependencies that keeps the post-CIRGen pipeline from being IR-to-IR.
Some of the related discussion on this has been done
[here](https://discourse.llvm.org/t/rfc-clangir-making-cir-pipeline-boundaries-first-class-driver-artifacts/90998)
and PR: #219048
2. `#cir.cu.binary_handle` stored the *file path*. That's a build input,
not a
property of the program: it bakes one machine's directory layout into a
`.cir`.
The PR removes the file path and adds an attribute
CIRGen now reads the file in and records the contents
as `#cir.cu.device_binary`, a `StringAttr` of raw bytes. The
attribute is deleted once LoweringPrepare "consumes" it.
A couple of notes:
1. The GPU dialect has a similar representation. We may want to move
towards that direction slowly, but I don't see any value doing this now.
It will confuse the direction of this PR.
2. The test `clang/test/CIR/Diagnostics/mlir-error-routing.cu` has
completely
changed, because it relied on an error occurring when the file attribute
was missing.
Since we deleted that attribute completely, the test was failing.
---------
Co-authored-by: Claude Opus 5 <noreply at anthropic.com>
Commit: 0a90c92d5285cae7f7b7ae26573e39df5898cafc
https://github.com/llvm/llvm-project/commit/0a90c92d5285cae7f7b7ae26573e39df5898cafc
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M mlir/examples/toy/Ch4/include/toy/Ops.td
M mlir/examples/toy/Ch5/include/toy/Ops.td
M mlir/examples/toy/Ch6/include/toy/Ops.td
M mlir/examples/toy/Ch7/include/toy/Ops.td
M mlir/test/Analysis/DataFlow/test-last-modified-callgraph.mlir
M mlir/test/Analysis/DataFlow/test-last-modified.mlir
M mlir/test/Analysis/DataFlow/test-next-access.mlir
M mlir/test/Analysis/DataFlow/test-strided-metadata-range-analysis.mlir
M mlir/test/Dialect/Affine/affine-loop-normalize.mlir
M mlir/test/Dialect/Affine/int-range-interface.mlir
M mlir/test/Dialect/Affine/simplify-min-max-ops.mlir
M mlir/test/Dialect/Affine/simplify-with-bounds.mlir
M mlir/test/Dialect/Affine/transform-op-simplify-min-max-ops.mlir
M mlir/test/Dialect/Arith/int-range-analysis-convergence.mlir
M mlir/test/Dialect/Arith/int-range-interface.mlir
M mlir/test/Dialect/Arith/int-range-loop-iter-args.mlir
M mlir/test/Dialect/Arith/int-range-narrowing.mlir
M mlir/test/Dialect/Arith/int-range-opts-bug-119045.mlir
M mlir/test/Dialect/Arith/int-range-opts.mlir
M mlir/test/Dialect/GPU/int-range-interface-cluster.mlir
M mlir/test/Dialect/GPU/int-range-interface.mlir
M mlir/test/Dialect/MLProgram/pipeline-globals.mlir
M mlir/test/Dialect/MemRef/int-range-inference.mlir
M mlir/test/Dialect/OpenACC/acc-implicit-routine.mlir
M mlir/test/Dialect/Tensor/int-range-inference.mlir
M mlir/test/Dialect/Vector/int-range-interface.mlir
M mlir/test/IR/attribute.mlir
M mlir/test/Interfaces/InferIntRangeInterface/infer-int-range-test-ops-invalid.mlir
M mlir/test/Interfaces/InferIntRangeInterface/infer-int-range-test-ops.mlir
M mlir/test/Transforms/loop-invariant-code-motion.mlir
M mlir/test/Transforms/make-composed-folded-affine-apply.mlir
M mlir/test/lib/Dialect/Test/TestDialect.td
M mlir/test/lib/Dialect/Test/TestOps.td
M mlir/test/lib/Dialect/Test/TestOpsSyntax.td
M mlir/test/mlir-tblgen/constant-str-attr-invalid.mlir
M mlir/test/mlir-tblgen/op-format-invalid.td
M mlir/test/mlir-tblgen/op-format.mlir
M mlir/test/mlir-tblgen/op-format.td
M mlir/test/mlir-tblgen/pattern.mlir
M mlir/test/python/dialects/python_test.py
M mlir/test/python/python_test_ops.td
Log Message:
-----------
[mlir] Remove remaining strict property assembly opt-outs (#226702)
Migrate Toy, test, and Python dialect formats to use prop-dict for
inherent properties. Update assembly fixtures and expected output for
strict property printing.
Assisted-by: Codex
Commit: 688a1498b3ce9011ee58c214086e3cd408e86f5e
https://github.com/llvm/llvm-project/commit/688a1498b3ce9011ee58c214086e3cd408e86f5e
Author: Amit Tiwari <Amit.Tiwari at amd.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M clang/lib/Sema/SemaOpenMP.cpp
A clang/test/OpenMP/collapse_iv_width_codegen.cpp
Log Message:
-----------
[Clang][OpenMP] Optimize `collapse` IV bit-width precision expression (#225612)
`collapse` used to build both a 32-bit and a 64-bit trip-count, then
keep one.
This patch does the same in `checkOpenMPLoop`:
If we know 32-bit is enough, build only 32-bit.
Else build 64-bit first.
Build 32-bit only when the product is a compile-time constant and fits.
Origin: `flatten` already builds only the width it keeps.
Commit: e217205575ac65acd6d301b036bea8875f5eaa16
https://github.com/llvm/llvm-project/commit/e217205575ac65acd6d301b036bea8875f5eaa16
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/conditional-scalar-assignment-fold-tail.ll
M llvm/test/Transforms/LoopVectorize/AArch64/conditional-scalar-assignment.ll
M llvm/test/Transforms/LoopVectorize/RISCV/conditional-scalar-assignment-fold-tail.ll
M llvm/test/Transforms/LoopVectorize/RISCV/conditional-scalar-assignment.ll
M llvm/test/Transforms/LoopVectorize/X86/conditional-scalar-assignment.ll
M llvm/test/Transforms/LoopVectorize/find-last-ptr-induction.ll
M llvm/test/Transforms/LoopVectorize/iv-select-cmp-non-const-iv-start.ll
M llvm/test/Transforms/LoopVectorize/iv-select-cmp-trunc.ll
M llvm/test/Transforms/LoopVectorize/iv-select-cmp.ll
Log Message:
-----------
[VPlan] Mark default value or ExtractLastActive as only first lane used. (#226153)
The default value (operand 0) of ExtractLastActive is the scalar value
of @llvm.experimental.vector.extract.last.active. Only the first lane is
used, mark accordingly.
PR: https://github.com/llvm/llvm-project/pull/226153
Commit: f950b04465ee6a198f3fa5644e4f70711041df8a
https://github.com/llvm/llvm-project/commit/f950b04465ee6a198f3fa5644e4f70711041df8a
Author: Kazu Hirata <kazu at google.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M llvm/include/llvm/Transforms/Utils/LoopUtils.h
M llvm/lib/Transforms/Utils/LoopUnroll.cpp
M llvm/lib/Transforms/Utils/LoopUtils.cpp
Log Message:
-----------
[Transforms] Remove unused functions (NFC) (#226655)
createAnyOfReduction:
The last caller was removed on January 18, 2026 in commit
ae1bd068db293c494c4c6314da3b9d138706460d.
canHaveUnrollRemainder:
The last caller, in an assert, was removed on May 1, 2026 in commit
316f0d3bfeaf7eee7b6d4ae60d357a8216ec5264.
Assisted-by: Antigravity
Commit: ab52e9f971d626346d70190df72636b477f6c089
https://github.com/llvm/llvm-project/commit/ab52e9f971d626346d70190df72636b477f6c089
Author: Yordan Vásquez <vyordangiovani at gmail.com>
Date: 2026-09-27 (Sun, 27 Sep 2026)
Changed paths:
M libcxx/include/complex
M libcxx/include/valarray
A libcxx/test/std/numerics/complex.number/complex/complex_requires_cv_unqualified_object.verify.cpp
A libcxx/test/std/numerics/numarray/template.valarray/valarray_requires_cv_unqualified_object.verify.cpp
Log Message:
-----------
[libc++] Add static_assert diagnostics for LWG3133 named requirements (#212360)
Add a static_assert to both std::complex<T> and std::valarray<T>
requiring that T be a cv-unqualified object type that satisfies the
Cpp17DefaultConstructible, Cpp17CopyConstructible, Cpp17CopyAssignable,
and Cpp17Destructible named requirements, per the revised wording in
[numeric.requirements]. This mirrors the existing pattern already used
by std::optional<T>.
Non-_v (class-style) trait forms are used throughout so that the
assertion is well-formed even when <complex>/<valarray> are included in
C++03/11/14 mode.
Test coverage:
- A .verify.cpp for complex<T> and one for valarray<T>, each covering
six failure modes: cv-qualified types, and one type violating each of
the four named requirements individually.
Follows-up e062a29cf865bb7cadea6cb605c9f3515e5b883f.
Commit: 5302d361339066363854a4e12e16e413af9ce1ce
https://github.com/llvm/llvm-project/commit/5302d361339066363854a4e12e16e413af9ce1ce
Author: geoffreygaren <ggaren at apple.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M clang/docs/analyzer/checkers.md
M clang/lib/StaticAnalyzer/Checkers/WebKit/ASTUtils.cpp
M clang/lib/StaticAnalyzer/Checkers/WebKit/PtrTypesSemantics.cpp
M clang/lib/StaticAnalyzer/Checkers/WebKit/PtrTypesSemantics.h
M clang/test/Analysis/Checkers/WebKit/mock-canborrow.h
M clang/test/Analysis/Checkers/WebKit/unborrowed-call-args.cpp
M clang/test/Analysis/Checkers/WebKit/unborrowed-local-vars-cxx23.cpp
M clang/test/Analysis/Checkers/WebKit/unborrowed-local-vars.cpp
Log Message:
-----------
[WebKit Checkers] Add built-in recognition for standard view types (#226350)
libc++ doesn't fully annotate `[[clang::lifetimebound]]` for all view
types. This results in false negatives in borrow checking.
Ultimately we need to fix this in libc++, but for now we can work around
the most common / most important false negatives. For example, borrow
checking can now check
for (auto& x : vector | std::views::reverse) { ... }
Assisted-by: Claude
Commit: 207f7f00ced9adf54e79f2bbf2c59a485a608495
https://github.com/llvm/llvm-project/commit/207f7f00ced9adf54e79f2bbf2c59a485a608495
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M llvm/test/Analysis/CostModel/X86/arith-fp.ll
Log Message:
-----------
[CostModel][X86] arith-fp.ll - test AVX512DQ instead of AVX512BW (#226519)
AVX512DQ has instructions relevant to fp arithmetic (vXi64 fp2int in particular)
Commit: d297af3b3d7a086d64f1477cfa682a16fcfa3260
https://github.com/llvm/llvm-project/commit/d297af3b3d7a086d64f1477cfa682a16fcfa3260
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
A llvm/test/Transforms/LoopVectorize/AArch64/sve-induction-wrapflags.ll
M llvm/test/Transforms/LoopVectorize/induction-wrapflags.ll
Log Message:
-----------
[LV] Add tests for wide induction wrap flags (NFC). (#226715)
Add tests for:
* inductions where the lane offsets may signed-overflow, even if the
scalar induction values do not,
* inductions whose increment does not directly update the phi, where the
increment's wrap flags do not apply to the induction,
* narrow inductions where the VF may exceed the signed maximum of the
induction type.
Commit: 555d8a58b85f0cfcbad0fc7cf7b13bbef4d4ca30
https://github.com/llvm/llvm-project/commit/555d8a58b85f0cfcbad0fc7cf7b13bbef4d4ca30
Author: David Green <david.green at arm.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64PerfectShuffle.h
Log Message:
-----------
[AArch64] Reorganise perfect shuffle generation. NFC (#224526)
This adds a generatePerfectShuffle implementation for parsing through
the perfect shuffle tables, generating a list of ShuffleEntry's that
represent the sequence of shuffles that need to be performed. This is
intended to be a NFC as-is, allowing it to be reused in global isel and
extended in the future to handle shuffles that are not part of the
shuffle table. The number of instructions generated can also be used for
costing shuffles, as we do for immediate generation.
Commit: 0ead65c731fa09596fbcc9b5109e504e9e7adb7e
https://github.com/llvm/llvm-project/commit/0ead65c731fa09596fbcc9b5109e504e9e7adb7e
Author: Michael G. Kazakov <mike.kazakov at gmail.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
A libcxx/test/benchmarks/algorithms/nonmodifying/pstl.find.bench.cpp
A libcxx/test/benchmarks/algorithms/sorting/pstl.sort.bench.cpp
A libcxx/test/benchmarks/numeric/pstl.transform_reduce.bench.cpp
Log Message:
-----------
[libc++][pstl] Add more benchmarks of the parallel algorithms (#225908)
This PR adds benchmarks of these 3 parallel algorithms:
- `std::find(policy, ...)`
- `std::sort(policy, ...)`
- `std::transform_reduce(policy, ...)`
---------
Co-authored-by: Louis Dionne <ldionne.2 at gmail.com>
Commit: 6aefa9a60eb523ca3d8601ab69509e057730ac8d
https://github.com/llvm/llvm-project/commit/6aefa9a60eb523ca3d8601ab69509e057730ac8d
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M llvm/lib/Target/ARM/ARMTargetMachine.cpp
M llvm/lib/Target/ARM/ARMTargetMachine.h
M llvm/lib/Target/ARM/ARMTargetObjectFile.cpp
M llvm/lib/Target/ARM/ARMTargetObjectFile.h
M llvm/test/CodeGen/ARM/module-target-abi.ll
Log Message:
-----------
ARM: Remove cached TargetABI from ARMBaseTargetMachine (#226482)
This cannot account for the "target-abi" module flag, so
let the uses query that. ARMElfTargetObjectFile was the one user of
this value, so this failed to respect the module flag.
Co-Authored-By: Claude Opus 5 <noreply at anthropic.com>
Commit: fc99ddb168769dd732f40b74c09f9d800c30e7e3
https://github.com/llvm/llvm-project/commit/fc99ddb168769dd732f40b74c09f9d800c30e7e3
Author: Alan Zhao <ayzhao at google.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M llvm/cmake/modules/GetLibraryName.cmake
Log Message:
-----------
[cmake][Windows] Do not strip library prefixes on Windows (#226635)
Commit: 808c726db2fe24f7ba2901f5701ae19cfe602f0a
https://github.com/llvm/llvm-project/commit/808c726db2fe24f7ba2901f5701ae19cfe602f0a
Author: Prajit Rahul <prajitrahul05 at gmail.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M llvm/docs/Lexicon.md
Log Message:
-----------
[LLVM][Docs] Define IR in the lexicon (#221388)
Define IR in the LLVM lexicon using terminology from the LLVM Language
Reference Manual, including its SSA-based structure and three equivalent
representations.
Fixes #139867
AI Usage: ChatGPT
Commit: 315a38a1ef3825e4e7ebe188353b4c5329751453
https://github.com/llvm/llvm-project/commit/315a38a1ef3825e4e7ebe188353b4c5329751453
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
M llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
M llvm/lib/Transforms/Vectorize/VPlanUtils.h
M llvm/test/Transforms/LoopVectorize/AArch64/epilog-vectorization-widen-inductions.ll
M llvm/test/Transforms/LoopVectorize/X86/pr36524.ll
M llvm/test/Transforms/LoopVectorize/induction-wrapflags.ll
M llvm/test/Transforms/LoopVectorize/induction.ll
M llvm/test/Transforms/LoopVectorize/pr30654-phiscev-sext-trunc.ll
M llvm/test/Transforms/LoopVectorize/pr35773.ll
M llvm/test/Transforms/LoopVectorize/predicated-inductions.ll
M llvm/test/Transforms/LoopVectorize/single-value-blend-phis.ll
Log Message:
-----------
[VPlan] Take wide induction wrap flags from the increment of the phi. (#226726)
The binary operator of an integer InductionDescriptor is the incoming
value from the latch, which is not required to have the phi as operand.
E.g. for
%x = add i32 %iv, 5
%iv.next = add nuw nsw i32 %x, 1
the flags only apply to %x + 1, while the induction step is 6, and %iv +
6 may wrap even though %iv.next does not. Determine the wrap flags from
the increment of the header phi instead, and only if it adds to or
subtracts from the phi directly.
Commit: 899d817c7950c997402cd229935cd822acf45b08
https://github.com/llvm/llvm-project/commit/899d817c7950c997402cd229935cd822acf45b08
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/sve-low-trip-count.ll
M llvm/test/Transforms/LoopVectorize/RISCV/countable-early-exit-no-epilogue.ll
Log Message:
-----------
[LV] Skip low-trip count logic there is no scalar tail. (#225633)
https://github.com/llvm/llvm-project/pull/195823 added logic consider
vectorization of low trip count loops if there was no or a single
iteration remaining.
This causes loops to be vectorized with a VF where no scalar tail
remains, even if it is required for legality (loop with multiple
countable exits require scalar epilogue to pick the exit).
For now, limit to cases where there's a scalar iteration remaining.
PR: https://github.com/llvm/llvm-project/pull/225633
Commit: e0b3e4c82911376fcb2dfcbc4a3dd3f4f5891aba
https://github.com/llvm/llvm-project/commit/e0b3e4c82911376fcb2dfcbc4a3dd3f4f5891aba
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M llvm/include/llvm/Analysis/LoopAccessAnalysis.h
M llvm/lib/Analysis/LoopAccessAnalysis.cpp
Log Message:
-----------
[LAA] Remove unused functions (NFC) (#226733)
Remove RuntimePointerChecking::empty and LoopAccessInfo::getNumLoads /
getNumStores, which have no callers, together with the NumLoads and
NumStores counters that were only read by the latter.
Commit: 8c153f78f7c0a842edfee3f1601dee1776c941d6
https://github.com/llvm/llvm-project/commit/8c153f78f7c0a842edfee3f1601dee1776c941d6
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M llvm/include/llvm/Analysis/ScalarEvolutionExpressions.h
Log Message:
-----------
[SCEV] Remove unused classof(const SCEVUse *) overloads (NFC) (#226734)
isa/cast/dyn_cast on SCEVUse go through simplify_type or CastInfo.
classof(SCEVUse) is unused.
Commit: 7615da10b75c57286a4032eac8bb43c1b8d2ba46
https://github.com/llvm/llvm-project/commit/7615da10b75c57286a4032eac8bb43c1b8d2ba46
Author: Dan Salvato <dan at teamsalvato.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M llvm/lib/Target/M68k/M68kExpandPseudo.cpp
M llvm/lib/Target/M68k/M68kInstrArithmetic.td
M llvm/lib/Target/M68k/M68kInstrData.td
M llvm/lib/Target/M68k/M68kInstrInfo.cpp
M llvm/lib/Target/M68k/M68kInstrInfo.h
M llvm/test/CodeGen/M68k/Arith/divide-by-constant.ll
M llvm/test/CodeGen/M68k/Arith/smul-with-overflow.ll
M llvm/test/CodeGen/M68k/Arith/umul-with-overflow.ll
M llvm/test/CodeGen/M68k/Bits/btst.ll
M llvm/test/CodeGen/M68k/Control/cmp.ll
M llvm/test/CodeGen/M68k/Control/non-cmov-switch.ll
M llvm/test/CodeGen/M68k/Control/setcc.ll
M llvm/test/CodeGen/M68k/Data/load-extend.ll
M llvm/test/CodeGen/M68k/Data/sext-i1.ll
M llvm/test/CodeGen/M68k/register-spills.ll
Log Message:
-----------
[M68k] Finish implementation of `MOVX` (move and extend) pseudo-instructions and fix related errors (#218938)
This patch adds remaining addressing modes to the "move and extend"
pseudo-instructions, and fixes a few errors and inconsistencies in the
logic that caused inefficient code generation.
- Remaining addressing modes were implemented to match non-pseudo `MOVE`
instructions.
- Names of the pseudos now correctly reflect the register classes they
operate on, e.g. `MOVZXd32r16` for XR16 -> DR32.
- Fixed an issue where `MOVZX` could be allocated to an address
register, which has no way to zero-extend the result. (There were even
some of these in the test `register-spills.ll`, emitted as illegal
instructions, but the test doesn't have instruction verification
enabled, so it wasn't caught.)
- Fixed some `extload` patterns where the register was unnecessarily
extended to 32 bits before being truncated to its final size, causing
redundant instructions to be omitted.
- Fixed `anyext` patterns lowering to `MOVZX` instead of `MOVX`, causing
unnecessary zero-extensions.
- An inconsistency was fixed where the expansion logic would perform a
source-sized move when loading from memory, but a destination-sized move
when moving between registers. They now always perform a source-sized
move, which improves clarity in the assembly output and has more
opportunity for future optimizations.
Commit: bf529329b5ce85d42a5c793951ec9b31100cd84e
https://github.com/llvm/llvm-project/commit/bf529329b5ce85d42a5c793951ec9b31100cd84e
Author: Alexander Richardson <alexrichardson at google.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
A clang/test/CodeGen/RISCV/lto-module-asm-abi.c
A cross-project-tests/.clang-format
A cross-project-tests/riscv/lit.local.cfg
A cross-project-tests/riscv/lto-inline-asm-abi.c
M lld/test/ELF/lto/riscv-target-abi.ll
M llvm/test/CodeGen/RISCV/module-asm-features.ll
M llvm/test/CodeGen/RISCV/riscv-func-target-feature.ll
M llvm/test/LTO/RISCV/module-asm.ll
M llvm/test/MC/RISCV/mapping-across-sections.s
Log Message:
-----------
[RISC-V][LTO] Add baseline tests for LTO inline assembly and mapping symbols (#225129)
No functional change intended here, just adding test coverage for RISC-V LTO
inline assembly ABI handling (following up on
https://github.com/llvm/llvm-project/pull/223606) and for the `$x<arch>` ELF
mapping symbols emitted for module and function target features.
The `TODO`s for `.lto_discard` dropping module inline asm target features and
for the missing/duplicate `$x<arch>` mapping symbols will be addressed in the
following commits.
This commit was created with the help of AI tools
Pull-Request: https://github.com/llvm/llvm-project/pull/225129
Commit: 22d3cccd0beaf7d2c7728d0bc6fa347283b0bc13
https://github.com/llvm/llvm-project/commit/22d3cccd0beaf7d2c7728d0bc6fa347283b0bc13
Author: Alexander Richardson <alexrichardson at google.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M cross-project-tests/riscv/lto-inline-asm-abi.c
M llvm/lib/LTO/LTO.cpp
M llvm/lib/Linker/IRMover.cpp
M llvm/test/LTO/RISCV/module-asm.ll
Log Message:
-----------
[LTO] Preserve module inline asm target properties for .lto_discard and symvers (#225130)
Previously, LTO::addRegularLTO() and IRLinker::run() called
prependModuleInlineAsm() and appendModuleInlineAsm() with a plain string when
synthesizing `.lto_discard` and imported `.symver` directives, creating a new
GlobalAsmFragment with empty TargetCPU and TargetFeatures instead of preserving
the existing module inline asm's properties. Copy the front fragment's Props so
these synthesized directives are merged into the module's inline asm with the
same target features.
This commit was created with the help of AI tools
Pull-Request: https://github.com/llvm/llvm-project/pull/225130
Commit: 0ab3502ec56a5d8330c79849945b9fefd2668f01
https://github.com/llvm/llvm-project/commit/0ab3502ec56a5d8330c79849945b9fefd2668f01
Author: Alexander Richardson <alexrichardson at google.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp
M llvm/test/MC/RISCV/mapping-across-sections.s
Log Message:
-----------
[RISC-V][MC] Fix mapping symbol section tracking on popSection() (#225131)
Previously, RISCVELFStreamer::changeSection() saved LastEMS and LastEmittedArch
under getPreviousSection().first instead of getCurrentSection().first. When
MCStreamer::popSection() switches back to a previous section,
getPreviousSection() already points to the destination section being restored
rather than the section being exited. This clobbered the destination section's
saved mapping symbol state and caused duplicate `$x<arch>` mapping symbols to
be emitted whenever returning to `.text`.
Use getCurrentSection().first instead, matching AArch64ELFStreamer and
ARMELFStreamer.
This commit was created with the help of AI tools
Pull-Request: https://github.com/llvm/llvm-project/pull/225131
Commit: 6eeb3b4ebdae20cd5f1e0fe5e74df3b418b654e2
https://github.com/llvm/llvm-project/commit/6eeb3b4ebdae20cd5f1e0fe5e74df3b418b654e2
Author: Alexander Richardson <alexrichardson at google.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M cross-project-tests/riscv/lto-inline-asm-abi.c
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.h
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.h
Log Message:
-----------
[RISC-V][MC] Update ELF streamer ArchString in setFlagsFromFeatures() (#225140)
During LTO, the TargetMachine subtarget is initialized with the linker's
default CPU (e.g. `generic-rv64`, `rv64i2p1`), while
RISCVAsmPrinter::emitStartOfAsmFile() reconstructs the module's actual ISA from
the `riscv-isa` module flag and calls RISCVTargetStreamer::setFlagsFromFeatures()
and RISCVTargetStreamer::emitTargetAttributes(). Because
RISCVTargetELFStreamer previously only initialized InitialArchString and
ArchString in its constructor rather than in setFlagsFromFeatures(), direct
object emission bypassed the update and tagged `.text` with `$xrv64i2p1`
instead of the module's full architecture string.
Move the InitialArchString and ArchString initialization into
RISCVTargetELFStreamer::setFlagsFromFeatures() and also call setArchString()
alongside emitTextAttribute(RISCVAttrs::ARCH, ...) in
RISCVTargetStreamer::emitTargetAttributes().
This commit was created with the help of AI tools
Pull-Request: https://github.com/llvm/llvm-project/pull/225140
Commit: 0e2ebe79f5c4ea36d7daecb76fb4867452d6973e
https://github.com/llvm/llvm-project/commit/0e2ebe79f5c4ea36d7daecb76fb4867452d6973e
Author: Alexander Richardson <alexrichardson at google.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
M llvm/test/CodeGen/RISCV/module-asm-features.ll
M llvm/test/CodeGen/RISCV/riscv-func-target-feature.ll
Log Message:
-----------
[RISC-V] Update streamer ArchString in emitTargetFeaturePush() (#225133)
Previously, RISCVAsmPrinter::emitTargetFeaturePush() only emitted `.option push`
and `.option arch` without updating the streamer's active ArchString. When
emitting an ELF object file directly (`-filetype=obj`),
RISCVTargetELFStreamer::emitDirectiveOptionArch() is a no-op while
emitTargetFeaturePop() resets ArchString back to the pushed ArchString, so
module-level inline assembly and functions with custom `target-features` failed
to emit updated `$x<arch>` mapping symbols.
Call RTS.setArchString() with the parsed ISA string in emitTargetFeaturePush()
so `-filetype=obj` records the active `$x<arch>` mapping symbol alongside
`.option arch`.
This commit was created with the help of AI tools
Pull-Request: https://github.com/llvm/llvm-project/pull/225133
Commit: b380036c75b82ab16aa988331b65cea6323091e7
https://github.com/llvm/llvm-project/commit/b380036c75b82ab16aa988331b65cea6323091e7
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M .github/workflows/docs.yml
Log Message:
-----------
[Github] Build BOLT docs on changes (#226747)
We were already set up to build the BOLT docs, but the workflow did not
actually trigger on changes to the BOLT docs specifically. This change
fixes that.
Commit: fb9596b7117dac3a1bc680b1041464944d0caa24
https://github.com/llvm/llvm-project/commit/fb9596b7117dac3a1bc680b1041464944d0caa24
Author: Letu Ren <fantasquex at gmail.com>
Date: 2026-09-27 (Sun, 27 Sep 2026)
Changed paths:
M mlir/lib/Target/LLVMIR/Dialect/LLVMIR/LLVMToLLVMIRTranslation.cpp
M mlir/test/Target/LLVMIR/llvmir.mlir
Log Message:
-----------
[MLIR][LLVM] Produce canonical const GEP in convertGEPOp (#226699)
The DataLayout overload of ConstantExpr::getGetElementPtr is the form
that replaces typed constant GEPs. Use it for inrange GEPs and fail
translation when the indices cannot be reduced to a byte offset.
This resolves
https://github.com/llvm/llvm-project/pull/220424#discussion_r4092337505
Assisted-by: grok-4.7
Signed-off-by: Letu Ren <fantasquex at gmail.com>
Commit: e54a8d183eda0097771b422399ee929a334fb0af
https://github.com/llvm/llvm-project/commit/e54a8d183eda0097771b422399ee929a334fb0af
Author: Alan Zhao <ayzhao at google.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M llvm/cmake/modules/GetLibraryName.cmake
Log Message:
-----------
[cmake][Windows] Fix CMake variable (#226745)
As a follow-up fix to #226635, the variable is `WIN32` not `Win32`.
Commit: 32ee4f7ed0ba2f169d22416c73360146153c9711
https://github.com/llvm/llvm-project/commit/32ee4f7ed0ba2f169d22416c73360146153c9711
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M llvm/include/llvm/CodeGen/SDPatternMatch.h
Log Message:
-----------
[SDPatternMatch] Simplify EffectiveOperands and drop the template specialization. NFC (#226036)
The chain and glue operands are in fixed locations, we don't need a loop
to find them.
Use the template parameter to skip the constructor body instead of using
template specialization.
Commit: 50f802581bd16b82bd68a9a4682cdbdc560368df
https://github.com/llvm/llvm-project/commit/50f802581bd16b82bd68a9a4682cdbdc560368df
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-09-27 (Sun, 27 Sep 2026)
Changed paths:
M clang/include/clang/AST/APValue.h
M clang/lib/AST/ExprConstant.cpp
Log Message:
-----------
[clang][AST] Mark APValue as LLVM_ATTRIBUTE_WARN_UNUSED (#226632)
Commit: 4c85cbebc59d62d6845ea31f649d8519813b55ff
https://github.com/llvm/llvm-project/commit/4c85cbebc59d62d6845ea31f649d8519813b55ff
Author: Reid Kleckner <rkleckner at nvidia.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M clang/docs/AllocToken.md
M clang/docs/ClangLinkerWrapper.md
M clang/docs/ClangOffloadBundler.md
M clang/docs/ClangTransformerTutorial.md
M clang/docs/ControlFlowIntegrity.md
M clang/docs/ControlFlowIntegrityDesign.md
M clang/docs/InternalsManual.md
M clang/docs/IntroductionToTheClangAST.md
M clang/docs/LanguageExtensions.md
M clang/docs/LibASTImporter.md
M clang/docs/LifetimeSafety.md
M clang/docs/SafeBuffers.md
M clang/docs/ScalableStaticAnalysis/user-docs/SummaryExtraction.md
M clang/docs/WarningSuppressionMappings.md
M clang/docs/analyzer/checkers.md
M clang/docs/analyzer/user-docs/Annotations.md
M clang/docs/conf.py
M clang/include/clang/Basic/AttrDocs.td
M llvm/docs/SphinxQuickstartTemplate.md
M utils/docs/llvm_sphinx/ext/absolute_links.py
M utils/docs/llvm_sphinx/ext/absolute_links_test/markdown.md
Log Message:
-----------
[docs] Replace clang.llvm.org/docs links with Sphinx links (#222507)
Use Sphinx document and option roles or project-relative links for links
within the Clang documentation. Repair stale generated-document
fragments found while validating the replacements. This ensures that
standalone documentation builds are self-contained, although
cross-project links (Clang->LLVM) typically go via absolute llvm.org
hrefs.
Part of #214861
Assisted-by: Codex
Commit: dbea9bd01b3ffec3ff35bfacb628257db8655ee5
https://github.com/llvm/llvm-project/commit/dbea9bd01b3ffec3ff35bfacb628257db8655ee5
Author: Amilendra Kodithuwakku <amilendra.kodithuwakku at arm.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M bolt/docs/conf.py
Log Message:
-----------
[docs][bolt] Remove Markdown enum (#226411)
Remove use of Markdown enum from the bolt docs. Related to #223829.
This should fix our ATfL build
[failure](https://github.com/arm/arm-toolchain/actions/runs/36103090912/job/107969633028#step:7:22533)
```
Traceback (most recent call last):
File "/workspace/python/.venv/lib/python3.12/site-packages/sphinx/config.py", line 529, in eval_config_file
exec(code, namespace) # NoQA: S102
^^^^^^^^^^^^^^^^^^^^^
File "/workspace/src/bolt/docs/conf.py", line 18, in <module>
globals().update(common_conf(tags, markdown=Markdown.NEVER))
^^^^^^^^
NameError: name 'Markdown' is not defined
```
Commit: 126dbd97fc5d33edf43a1fce12fb5d3ea46e5be7
https://github.com/llvm/llvm-project/commit/126dbd97fc5d33edf43a1fce12fb5d3ea46e5be7
Author: Alexander Richardson <alexrichardson at google.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M clang/test/CodeGen/RISCV/lto-module-asm-abi.c
Log Message:
-----------
[Clang][RISC-V] Fix lto-module-asm-abi.c on non-asserts/no-lld builds (#226752)
Pass `-fno-discard-value-names` so the `entry:` label is preserved in
non-asserts builds, and drop `-fuse-ld=lld` so the driver check succeeds
on bots that do not have `ld.lld` installed.
Fixes: bf529329b5ce ("[RISC-V][LTO] Add baseline tests for LTO inline assembly and mapping symbols (#225129)")
Pull-Request: https://github.com/llvm/llvm-project/pull/226752
Commit: 57721b7c631b3dacc8f59b2467992e3ff4866cc6
https://github.com/llvm/llvm-project/commit/57721b7c631b3dacc8f59b2467992e3ff4866cc6
Author: Lang Hames <lhames at gmail.com>
Date: 2026-09-27 (Sun, 27 Sep 2026)
Changed paths:
M orc-rt/include/CMakeLists.txt
M orc-rt/include/orc-rt-c/config.h.in
A orc-rt/include/orc-rt-c/support/LogLevel.h
M orc-rt/include/orc-rt-c/support/Logging.h
M orc-rt/include/orc-rt/bedrock/Session.h
Log Message:
-----------
[orc-rt] Move ORC_RT_LOG_ENABLED out of config.h; catch typos. (#226751)
Move ORC_RT_LOG_ENABLED to orc-rt-c/support/LogLevel.h so that config.h
is kept for build options only.
Switch to using function-like macros so that typos in level-names become
compilation errors.
Commit: 689040ca0cb30b3f93edb5e51f64333b23e4610f
https://github.com/llvm/llvm-project/commit/689040ca0cb30b3f93edb5e51f64333b23e4610f
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-27 (Sun, 27 Sep 2026)
Changed paths:
M llvm/include/llvm/CodeGen/TargetLoweringObjectFileImpl.h
M llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
M llvm/lib/Target/M68k/M68kTargetObjectFile.cpp
M llvm/lib/Target/M68k/M68kTargetObjectFile.h
Log Message:
-----------
CodeGen: Remove shadowing TargetMachine members from COFF and M68k TLOFs (#226769)
TargetLoweringObjectFile::Initialize already records the TargetMachine
in a base class field.
Co-authored-by: Claude Opus 5 <noreply at anthropic.com>
Commit: 9bf0c497dceba0c7eb882c0f2a96c8151ce74ae3
https://github.com/llvm/llvm-project/commit/9bf0c497dceba0c7eb882c0f2a96c8151ce74ae3
Author: Lang Hames <lhames at gmail.com>
Date: 2026-09-27 (Sun, 27 Sep 2026)
Changed paths:
M orc-rt/include/orc-rt/bedrock/ConnectorRegistry.h
M orc-rt/lib/bedrock/ConnectorRegistry.cpp
M orc-rt/lib/bedrock/sys/posix/SocketConnector.cpp
M orc-rt/test/unit/bedrock/sys/posix/SocketConnectorTest.cpp
M orc-rt/tools/ogre/ogre.cpp
Log Message:
-----------
[orc-rt] Simplify ConnectorRegistry::connect and ogre setup. (#226772)
ConnectorRegistry::connect and ConnectorFn now take the Session and
BootstrapInfo directly, replacing the GetAttachInfo callback and the
AttachInfo struct. The callback let the Session be built lazily, after
the connector had validated its spec, but a connection can fail after
validation anyway, so callers already had to handle discarding a Session
built for a failed connection. Build the Session first, then connect.
ogre's setup is restructured to match: makeSession detects the process
info, builds a thread-pool dispatcher and the Session, adds the host
services, then connects; runOgre waits for the detach. Errors are
reported via Session::logErrors when logging is enabled.
SocketConnectorTest now connects a real Session. Its ownership test
adopts a non-stream socket, which the connector accepts and
createSimpleRemoteCAOverSocket then rejects, rather than relying on a
failing GetAttachInfo.
Commit: 80b46c9d74a868cd20720cc7932a2f88bda43d25
https://github.com/llvm/llvm-project/commit/80b46c9d74a868cd20720cc7932a2f88bda43d25
Author: Letu Ren <fantasquex at gmail.com>
Date: 2026-09-27 (Sun, 27 Sep 2026)
Changed paths:
M clang/test/CIR/CodeGenBuiltins/builtin-nondeterministic-value.c
Log Message:
-----------
[CIR][NFC] Add vector of boolean test to __builtin_nondeterministic_value (#219550)
Assisted-by: grok-4.6
Signed-off-by: Letu Ren <fantasquex at gmail.com>
Commit: dfde6ac69e6e0c5a717042de3fa7f118eea7d830
https://github.com/llvm/llvm-project/commit/dfde6ac69e6e0c5a717042de3fa7f118eea7d830
Author: Mamadou Wane <mamadouswane at gmail.com>
Date: 2026-09-27 (Sun, 27 Sep 2026)
Changed paths:
M clang-tools-extra/clang-tidy/bugprone/RedundantBranchConditionCheck.cpp
M clang-tools-extra/docs/ReleaseNotes.md
M clang-tools-extra/test/clang-tidy/checkers/bugprone/redundant-branch-condition.cpp
Log Message:
-----------
[clang-tidy] Fix redundant-branch-condition false positive in loops (#225827)
Fixes #205685.
`bugprone-redundant-branch-condition` decides whether the condition
variable changes between the outer and inner `if` by comparing source
positions. When a loop sits between the two, a mutation that comes after
the inner `if` in the source still runs before the inner condition is
evaluated again on the next iteration, so the check reports a redundant
condition that isn't, and the fix-it changes behavior.
The fix walks the parents of the inner `if` up to the outer `if` and
finds the outermost enclosing loop. If the variable is mutated anywhere
in that loop, the check does not warn. This follows NagyDonat's
suggestion in the issue: the existing check already covers mutations
between the outer condition and the loop, so only the loop itself needs
the extra query. The walk passes through declarations, so an inner `if`
inside a lambda stored in a variable is handled too, and it stops at the
enclosing function. I chose a syntactic walk instead of the CFG
(`utils::ExprSequence`), since it covers the range the issue asks for
without building a CFG on every match.
Tests cover `for`, `while`, `do`, and range-based `for`, a mutation in a
`do`/`while` condition, a lambda stored in a variable inside the loop,
and an inner loop whose enclosing loop does the mutation. Each of these
warns without the patch. Three positive cases confirm the warning is
kept when the loop never mutates the variable, when the mutation comes
after the loop, and when the loop encloses both `if` statements.
Limitations:
- Any mutation in the loop suppresses the warning, including one
followed by an exit from the loop (`break`, `return`, `throw`) or one
that cannot make the condition false. The inner condition is still
redundant in those cases; telling them apart needs the CFG. I added the
`break` case under Unhandled Cases. The change only removes warnings, so
it adds no new false positives.
- Loops built with `goto` and Objective-C `for ... in` loops are not
recognized, so the false positive remains there.
I used Claude to help write the code. I tested and reviewed all of it
myself, and worked through the approach and suggestions with Claude.
Commit: 719341a64c02261b7b43e4aa6a25f597cca8626d
https://github.com/llvm/llvm-project/commit/719341a64c02261b7b43e4aa6a25f597cca8626d
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-09-27 (Sun, 27 Sep 2026)
Changed paths:
M llvm/include/llvm/Analysis/TargetTransformInfo.h
M llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
M llvm/include/llvm/CodeGen/BasicTTIImpl.h
M llvm/lib/Analysis/TargetTransformInfo.cpp
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
M llvm/test/Analysis/CostModel/AArch64/speculative-load.ll
M llvm/test/Analysis/CostModel/X86/speculative-load.ll
Log Message:
-----------
[TTI] Provide conservative legality + costs for @llvm.speculative.load. (#180036)
Add TTI support for @llvm.speculative.load, including cost and legaltiy
checking support.
The initial implementation for AArch64 checks if the loaded type is
<= 16 bytes, and only considers such cases legal due to MTE.
PR:
https://github.com/llvm/llvm-project/pull/180036
Depends on https://github.com/llvm/llvm-project/pull/179642
Commit: 6909c17f14683203621f5a3d8fbf04dfd5d9c623
https://github.com/llvm/llvm-project/commit/6909c17f14683203621f5a3d8fbf04dfd5d9c623
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-09-27 (Sun, 27 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
M llvm/test/Transforms/ConstraintElimination/analysis-invalidation.ll
Log Message:
-----------
[ConstraintElim] Don't request SCEV if there are no loops. (NFC) (#226736)
ConstraintElimination only uses SCEV when there are any loops. Don't
request the analysis if there are no loops.
This reduces compile-time a bit (more for workloads with large number of
functions w/o loops):
stage1-O3: -0.03%
stage1-ReleaseThinLTO: -0.04%
stage1-ReleaseLTO-g: -0.02%
stage1-aarch64-O3: -0.03%
stage2-O3: -0.04%
stage2-clang: -0.09%
https://llvm-compile-time-tracker.com/compare.php?from=899d817c7950c997402cd229935cd822acf45b08&to=c4453240417d8705b0752c3feda8d02365f8175c&stat=instructions:u
PR: https://github.com/llvm/llvm-project/pull/226736
Commit: 57630fd809ca4964f887dd531e1a09618d962b10
https://github.com/llvm/llvm-project/commit/57630fd809ca4964f887dd531e1a09618d962b10
Author: Chibuoyim (Wilson) Ogbonna <chibuoyim.faith.ogbonna at huawei.com>
Date: 2026-09-27 (Sun, 27 Sep 2026)
Changed paths:
R clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_addv.c
A clang/test/CodeGen/AArch64/sve/addv.c
Log Message:
-----------
[clang][CIR] Add tests for SVE ADDV intrinsics (#225648)
This adds CIR tests for `svaddv` (plain SVE) intrinsics following the
task description in
[223963](https://github.com/llvm/llvm-project/issues/223963).
Moves and adapts `sve-intrinsics/acle_sve_addv.c` to `sve/addv.c`.
Commit: 68fddbbe019b63698e9c4a898b313b9112019cab
https://github.com/llvm/llvm-project/commit/68fddbbe019b63698e9c4a898b313b9112019cab
Author: David Green <david.green at arm.com>
Date: 2026-09-27 (Sun, 27 Sep 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
M llvm/test/CodeGen/AArch64/lowmaskedlanes.ll
Log Message:
-----------
[DAG] Scalarise trivial splat operations (#226257)
This fixes an issue reported on #224255, where a single active lane
masked store is converted to a v1f16 extract_subvector, which becomes a
v1f16 splat, which fails to scalarize. Add the necessary trivial
scalarisation of the splat by using the f16 input operand.
(I was originally going to fix this by generating a scalar f16 extract
directly (which would have the benefit of treating f16 as legal), but
that seems to cause a regression in 2 x86 tests).
Commit: 6b51046ae30cd78fc4b26605e2dcf3b70c282f4c
https://github.com/llvm/llvm-project/commit/6b51046ae30cd78fc4b26605e2dcf3b70c282f4c
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-09-27 (Sun, 27 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
A llvm/test/Transforms/SLPVectorizer/X86/narrowed-reduction-gathered-leftover-leaf.ll
Log Message:
-----------
[SLP]Fix erasing gathered leftover narrowed reduction leaves
A leftover narrowed reduction leaf, only gathered in the tree, loses all
users once the tree scalars are erased and is swept as a dead operand,
though the reduction epilogue still uses it. Keep such values alive.
Fixes https://github.com/llvm/llvm-project/pull/224919#issuecomment-5855368565
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/226782
Commit: a9407d59c4abfb8bf49da7dfcec6775707288b9e
https://github.com/llvm/llvm-project/commit/a9407d59c4abfb8bf49da7dfcec6775707288b9e
Author: Nico Weber <thakis at chromium.org>
Date: 2026-09-27 (Sun, 27 Sep 2026)
Changed paths:
M libcxx/include/__ostream/print.h
Log Message:
-----------
[libc++] Port #200996 to ostream (#226372)
Reduces the time to compile a TU with just `#include <ostream>` from
254.7 ms ± 3.0 ms to 227.7 ms ± 2.1 ms on my system (-std=c++23, -O2,
arm64 macOS).
See #195466 for details. Without this, the call is evaluated when the
template is parsed, which evaluates format_string's consteval
constructor for "\n" in every translation unit that includes <ostream>,
even if nothing calls println().
No behavior change.
Commit: 14df65f5db67d0096ef2360abb1e30891dae66b5
https://github.com/llvm/llvm-project/commit/14df65f5db67d0096ef2360abb1e30891dae66b5
Author: Leonidas Spyropoulos <artafinde at gmail.com>
Date: 2026-09-27 (Sun, 27 Sep 2026)
Changed paths:
M libcxx/include/__chrono/duration.h
M libcxx/test/std/time/months.pass.cpp
M libcxx/test/std/time/years.pass.cpp
Log Message:
-----------
[libc++][chrono] Fix years/months periods on GCC/i386 (#223669)
`static_cast<int>(365.2425 * 60 * 60 * 24)`, added in
f537b4e51822b19780386e0575ff95e82f8ec445, isn't exactly 31556952 on
every host: GCC targeting i386 folds it in x87 extended precision and
gets 31556951, making `years::period` and `months::period` coprime and
breaking `year_month` arithmetic.
Use the literal values instead, there's no readability to lose since
they were only there to avoid a template instantiation in the first
place.
Signed-off-by: Leonidas Spyropoulos <artafinde at archlinux.org>
Commit: 0b401e859b9fec54231b11ffb39085ea02e053c0
https://github.com/llvm/llvm-project/commit/0b401e859b9fec54231b11ffb39085ea02e053c0
Author: Kazu Hirata <kazu at google.com>
Date: 2026-09-27 (Sun, 27 Sep 2026)
Changed paths:
M llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp
M llvm/lib/Target/PowerPC/PPC.h
M llvm/tools/dsymutil/DwarfLinkerForBinary.h
M llvm/tools/llvm-cov/CodeCoverage.cpp
M llvm/tools/llvm-objdump/COFFDump.h
M llvm/tools/llvm-objdump/ELFDump.h
M llvm/tools/llvm-objdump/OffloadDump.cpp
M llvm/tools/llvm-objdump/WasmDump.h
M llvm/tools/llvm-profgen/PerfReader.h
Log Message:
-----------
[llvm] Remove declarations without definitions (NFC) (#226764)
HexagonConstEvaluator::evaluateHexVector2: Added on July 28, 2016 in
commit 167d918225ecd05a63f6b8d449c317feda741e18 without a definition or
any callers.
initializePPCExpandISELPass: The definition and caller were removed on
August 27, 2024 in commit 8e901c255df45e38cb1d69a576804029e20868bf.
dsymutil::DwarfLinkerForBinary::createStreamer: The definition and
caller were removed on April 1, 2023 in commit
36f351098cd50809658493d9b2e22a795874bab0 (when the non-template
declaration in DwarfLinkerForBinary.h was replaced with a template
declaration without a definition).
exportCoverageDataToJson: The definition and caller were replaced with
CoverageExporterJson on January 4, 2018 in commit
1ef3a778ac47564aa5a7f04bbf572d22d1c616fb.
objdump::printCOFFFileHeader, objdump::printELFFileHeader, and
objdump::printWasmFileHeader: The definitions and callers were replaced
with Dumper::printPrivateHeaders on July 14, 2023 in commit
0af663f80da0009f6fd879cf4d41743d4c88a2db.
disassembleObject: Added on May 23, 2025 in commit
51a03ed27282166d418399f2ade9814ea5be9944 without a definition or any
callers.
sampleprof::VirtualUnwinder::recordRangeCount: The definition and
callers were removed on January 11, 2021 in commit
3869309a0c92735228afaa5663d1c10bb372bb54.
Assisted-by: Antigravity
Commit: 1345a4fa8d60bdd33d59b7a1c0613eaef7d8e01f
https://github.com/llvm/llvm-project/commit/1345a4fa8d60bdd33d59b7a1c0613eaef7d8e01f
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-09-27 (Sun, 27 Sep 2026)
Changed paths:
A llvm/test/Transforms/SLPVectorizer/X86/extracted-subfields-shifted-trunc.ll
Log Message:
-----------
[SLP][NFC]Add an extra test witj missing vectorization, NFC
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/226802
Commit: 0f5a125bad555b6bf4bb2318b9f1ea7936adf19d
https://github.com/llvm/llvm-project/commit/0f5a125bad555b6bf4bb2318b9f1ea7936adf19d
Author: Reid Kleckner <rkleckner at nvidia.com>
Date: 2026-09-27 (Sun, 27 Sep 2026)
Changed paths:
A libcxx/docs/ABIGuarantees.md
R libcxx/docs/ABIGuarantees.rst
A libcxx/docs/AddingNewCIJobs.md
R libcxx/docs/AddingNewCIJobs.rst
A libcxx/docs/CodingGuidelines.md
R libcxx/docs/CodingGuidelines.rst
A libcxx/docs/Contributing.md
R libcxx/docs/Contributing.rst
A libcxx/docs/Contributing/NewStandardProcedure.md
R libcxx/docs/Contributing/NewStandardProcedure.rst
A libcxx/docs/Contributing/PostMeetingProcedure.md
R libcxx/docs/Contributing/PostMeetingProcedure.rst
A libcxx/docs/Contributing/ReleaseProcedure.md
R libcxx/docs/Contributing/ReleaseProcedure.rst
A libcxx/docs/DesignDocs/ABIVersioning.md
R libcxx/docs/DesignDocs/ABIVersioning.rst
A libcxx/docs/DesignDocs/AtomicDesign.md
R libcxx/docs/DesignDocs/AtomicDesign.rst
A libcxx/docs/DesignDocs/CapturingConfigInfo.md
R libcxx/docs/DesignDocs/CapturingConfigInfo.rst
A libcxx/docs/DesignDocs/ExperimentalFeatures.md
R libcxx/docs/DesignDocs/ExperimentalFeatures.rst
A libcxx/docs/DesignDocs/ExtendedCXX03Support.md
R libcxx/docs/DesignDocs/ExtendedCXX03Support.rst
A libcxx/docs/DesignDocs/FeatureTestMacros.md
R libcxx/docs/DesignDocs/FeatureTestMacros.rst
A libcxx/docs/DesignDocs/FileTimeType.md
R libcxx/docs/DesignDocs/FileTimeType.rst
A libcxx/docs/DesignDocs/HeaderRemovalPolicy.md
R libcxx/docs/DesignDocs/HeaderRemovalPolicy.rst
M libcxx/include/__configuration/abi.h
Log Message:
-----------
[libc++][docs] Rename documentation files to Markdown (batch 1) (#221512)
Tracking issue: #201242
See the [migration guide] for more information.
[migration guide]:
https://llvm.org/docs/SphinxQuickstartTemplate.html#markdown-migration-guidelines
This is the initial straight rename commit. It will probably break the
docs build, but it has to be a separate PR for blame preservation
purposes.
Commit: 61b428e0edfe674b84d77f7b55aa687fce3b501e
https://github.com/llvm/llvm-project/commit/61b428e0edfe674b84d77f7b55aa687fce3b501e
Author: Reid Kleckner <rkleckner at nvidia.com>
Date: 2026-09-27 (Sun, 27 Sep 2026)
Changed paths:
M libcxx/docs/ABIGuarantees.md
M libcxx/docs/AddingNewCIJobs.md
M libcxx/docs/CodingGuidelines.md
M libcxx/docs/Contributing.md
M libcxx/docs/Contributing/NewStandardProcedure.md
M libcxx/docs/Contributing/PostMeetingProcedure.md
M libcxx/docs/Contributing/ReleaseProcedure.md
M libcxx/docs/DesignDocs/ABIVersioning.md
M libcxx/docs/DesignDocs/AtomicDesign.md
M libcxx/docs/DesignDocs/CapturingConfigInfo.md
M libcxx/docs/DesignDocs/ExperimentalFeatures.md
M libcxx/docs/DesignDocs/ExtendedCXX03Support.md
M libcxx/docs/DesignDocs/FeatureTestMacros.md
M libcxx/docs/DesignDocs/FileTimeType.md
M libcxx/docs/DesignDocs/HeaderRemovalPolicy.md
M libcxx/docs/conf.py
Log Message:
-----------
[libc++][docs] Convert documentation from reST to Markdown (batch 1) (#221513)
This is the first batch of changes to migrate libc++ documentation from
rst to markdown.
I use a local pixel diff tool to compare the rendered HTML, and all
diffs seem like fixes. They tend to fall into the following categories:
- dashed bullet lists were previously not rendered, but now they are
- extra indentation interpreted as blockquotes has been removed
- single backticks are now codefont spans, not italic spans
Tracking issue: #201242
See the [migration guide] for more information.
[migration guide]:
https://llvm.org/docs/SphinxQuickstartTemplate.html#markdown-migration-guidelines
This is a stacked PR based on #221512, which will be a standalone commit
that
renames *.rst -> *.md before this PR lands for history preservation
purposes.
-----
Before/after validation links:
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| --- | --- | --- |
| `libcxx/docs/ABIGuarantees.md` |
[before](https://llvmdocs.staging.reidkleckner.dev/before/libcxx/docs/ABIGuarantees.html)
|
[after](https://llvmdocs.staging.reidkleckner.dev/after/libcxx/docs/ABIGuarantees.html)
|
| `libcxx/docs/AddingNewCIJobs.md` |
[before](https://llvmdocs.staging.reidkleckner.dev/before/libcxx/docs/AddingNewCIJobs.html)
|
[after](https://llvmdocs.staging.reidkleckner.dev/after/libcxx/docs/AddingNewCIJobs.html)
|
| `libcxx/docs/CodingGuidelines.md` |
[before](https://llvmdocs.staging.reidkleckner.dev/before/libcxx/docs/CodingGuidelines.html)
|
[after](https://llvmdocs.staging.reidkleckner.dev/after/libcxx/docs/CodingGuidelines.html)
|
| `libcxx/docs/Contributing/NewStandardProcedure.md` |
[before](https://llvmdocs.staging.reidkleckner.dev/before/libcxx/docs/Contributing/NewStandardProcedure.html)
|
[after](https://llvmdocs.staging.reidkleckner.dev/after/libcxx/docs/Contributing/NewStandardProcedure.html)
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| `libcxx/docs/Contributing/PostMeetingProcedure.md` |
[before](https://llvmdocs.staging.reidkleckner.dev/before/libcxx/docs/Contributing/PostMeetingProcedure.html)
|
[after](https://llvmdocs.staging.reidkleckner.dev/after/libcxx/docs/Contributing/PostMeetingProcedure.html)
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| `libcxx/docs/Contributing/ReleaseProcedure.md` |
[before](https://llvmdocs.staging.reidkleckner.dev/before/libcxx/docs/Contributing/ReleaseProcedure.html)
|
[after](https://llvmdocs.staging.reidkleckner.dev/after/libcxx/docs/Contributing/ReleaseProcedure.html)
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| `libcxx/docs/Contributing.md` |
[before](https://llvmdocs.staging.reidkleckner.dev/before/libcxx/docs/Contributing.html)
|
[after](https://llvmdocs.staging.reidkleckner.dev/after/libcxx/docs/Contributing.html)
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| `libcxx/docs/DesignDocs/ABIVersioning.md` |
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|
[after](https://llvmdocs.staging.reidkleckner.dev/after/libcxx/docs/DesignDocs/ABIVersioning.html)
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[before](https://llvmdocs.staging.reidkleckner.dev/before/libcxx/docs/DesignDocs/AtomicDesign.html)
|
[after](https://llvmdocs.staging.reidkleckner.dev/after/libcxx/docs/DesignDocs/AtomicDesign.html)
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[before](https://llvmdocs.staging.reidkleckner.dev/before/libcxx/docs/DesignDocs/ExperimentalFeatures.html)
|
[after](https://llvmdocs.staging.reidkleckner.dev/after/libcxx/docs/DesignDocs/ExperimentalFeatures.html)
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[before](https://llvmdocs.staging.reidkleckner.dev/before/libcxx/docs/DesignDocs/ExtendedCXX03Support.html)
|
[after](https://llvmdocs.staging.reidkleckner.dev/after/libcxx/docs/DesignDocs/ExtendedCXX03Support.html)
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| `libcxx/docs/DesignDocs/FeatureTestMacros.md` |
[before](https://llvmdocs.staging.reidkleckner.dev/before/libcxx/docs/DesignDocs/FeatureTestMacros.html)
|
[after](https://llvmdocs.staging.reidkleckner.dev/after/libcxx/docs/DesignDocs/FeatureTestMacros.html)
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| `libcxx/docs/DesignDocs/FileTimeType.md` |
[before](https://llvmdocs.staging.reidkleckner.dev/before/libcxx/docs/DesignDocs/FileTimeType.html)
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Commit: 6cff1c56d1678e3d7eb70650d1fe138eac80c05e
https://github.com/llvm/llvm-project/commit/6cff1c56d1678e3d7eb70650d1fe138eac80c05e
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-09-27 (Sun, 27 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPUtils.cpp
M llvm/test/Transforms/SLPVectorizer/X86/extracted-subfields-shifted-trunc.ll
Log Message:
-----------
[SLP]Look through truncation of shifted extracted sub-fields
The masked sub-field of the shifted truncation of a wider scalar was
matched with the truncation as its source, while the other fields
matched the scalar itself, so the gather of the fields was rejected.
The field is within the truncated bits, look through the truncation.
Fixes #74380
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/226803
Commit: 20bbd88cf9e7be286b25c29c877c2d0564da9ecf
https://github.com/llvm/llvm-project/commit/20bbd88cf9e7be286b25c29c877c2d0564da9ecf
Author: Guy David <guyda96 at gmail.com>
Date: 2026-09-27 (Sun, 27 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Utils/SimplifyCFG.cpp
A llvm/test/Transforms/SimplifyCFG/AArch64/speculate-vector-phi-select-cost.ll
A llvm/test/Transforms/SimplifyCFG/ARM/speculate-vector-phi-select-cost.ll
A llvm/test/Transforms/SimplifyCFG/RISCV/speculate-mask-phi-select-cost.ll
A llvm/test/Transforms/SimplifyCFG/X86/speculate-mask-phi-select-cost.ll
Log Message:
-----------
[SimplifyCFG] Cost speculated selects with their real scalar condition (#217664)
`validateAndCostRequiredSelects()` priced the selects that
`speculativelyExecuteBB()` would create using
`CmpInst::makeCmpResultType(PN->getType())` as the condition type. For a
vector phi, that asks the target for the cost of a per-lane vector
select, but the select actually created uses the branch condition, which
is always a scalar `i1`.
This only changes behaviour where a target's cost model distinguishes
the two condition types. Of the targets checked, only AArch64 does.
This may worsen the compiler's output in RISC-V, X86, ARM, so no
intention to merge soon before collecting more feedback on how the
different targets should communicate this property.
Commit: 1b5693cb6b91df009d8f32dad206d3e15f0203ad
https://github.com/llvm/llvm-project/commit/1b5693cb6b91df009d8f32dad206d3e15f0203ad
Author: Chinmay Deshpande <chdeshpa at amd.com>
Date: 2026-09-27 (Sun, 27 Sep 2026)
Changed paths:
M .github/workflows/docs.yml
M .github/workflows/libcxx-benchmark-commit.yml
M .github/workflows/libcxx-benchmark-cron.yml
M .github/workflows/libcxx-pr-benchmark.yml
M .github/workflows/libcxx/build-at-commit/action.yml
M .github/workflows/sycl-tests.yml
M bolt/docs/conf.py
M bolt/lib/Passes/BinaryPasses.cpp
M bolt/lib/Passes/ReorderFunctions.cpp
M bolt/lib/Profile/DataAggregator.cpp
M bolt/test/X86/dwarf5-debug-names-skip-forward-decl.s
M clang-tools-extra/clang-tidy/bugprone/RedundantBranchConditionCheck.cpp
M clang-tools-extra/clangd/tool/ClangdMain.cpp
M clang-tools-extra/docs/ReleaseNotes.md
M clang-tools-extra/test/clang-tidy/checkers/bugprone/redundant-branch-condition.cpp
M clang/CMakeLists.txt
M clang/docs/AllocToken.md
M clang/docs/ClangLinkerWrapper.md
M clang/docs/ClangOffloadBundler.md
M clang/docs/ClangTransformerTutorial.md
M clang/docs/ControlFlowIntegrity.md
M clang/docs/ControlFlowIntegrityDesign.md
A clang/docs/HLSL/DynamicResources.md
M clang/docs/HLSL/HLSLDocs.md
M clang/docs/InternalsManual.md
M clang/docs/IntroductionToTheClangAST.md
M clang/docs/LanguageExtensions.md
M clang/docs/LibASTImporter.md
M clang/docs/LifetimeSafety.md
M clang/docs/ReleaseNotes.md
M clang/docs/SafeBuffers.md
M clang/docs/ScalableStaticAnalysis/user-docs/SummaryExtraction.md
M clang/docs/SourceBasedCodeCoverage.md
M clang/docs/WarningSuppressionMappings.md
M clang/docs/analyzer/checkers.md
M clang/docs/analyzer/user-docs/Annotations.md
M clang/docs/conf.py
M clang/include/clang/AST/APValue.h
M clang/include/clang/AST/OpenMPClause.h
M clang/include/clang/Basic/AttrDocs.td
M clang/include/clang/Basic/Builtins.td
M clang/include/clang/Basic/BuiltinsRISCV.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Basic/HLSLIntrinsics.td
M clang/include/clang/Basic/LangOptions.def
M clang/include/clang/CIR/Dialect/Builder/CIRBaseBuilder.h
M clang/include/clang/CIR/Dialect/IR/CIRAttrs.td
M clang/include/clang/CIR/Dialect/IR/CIRCUDAAttrs.td
M clang/include/clang/CIR/Dialect/IR/CIRDialect.td
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/include/clang/Interpreter/Interpreter.h
M clang/include/clang/Options/Options.td
A clang/include/clang/ScalableStaticAnalysis/Analyses/VirtualMethodFamily/VirtualMethodFamily.h
M clang/include/clang/ScalableStaticAnalysis/BuiltinAnchorSources.def
M clang/include/clang/Sema/HLSLExternalSemaSource.h
M clang/include/clang/StaticAnalyzer/Checkers/Checkers.td
M clang/lib/AST/APValue.cpp
M clang/lib/AST/ASTImporter.cpp
M clang/lib/AST/ExprConstant.cpp
M clang/lib/Basic/Targets/WebAssembly.cpp
M clang/lib/Basic/Targets/WebAssembly.h
M clang/lib/CIR/CMakeLists.txt
M clang/lib/CIR/CodeGen/CIRGenAtomic.cpp
M clang/lib/CIR/CodeGen/CIRGenBuilder.h
M clang/lib/CIR/CodeGen/CIRGenBuiltin.cpp
M clang/lib/CIR/CodeGen/CIRGenCUDANV.cpp
M clang/lib/CIR/CodeGen/CIRGenDecl.cpp
M clang/lib/CIR/CodeGen/CIRGenExprAggregate.cpp
M clang/lib/CIR/CodeGen/CIRGenModule.cpp
M clang/lib/CIR/Dialect/IR/CIRDialect.cpp
M clang/lib/CIR/Dialect/Transforms/LoweringPrepare.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
M clang/lib/CodeGen/CGBlocks.cpp
M clang/lib/CodeGen/CGHLSLBuiltins.cpp
M clang/lib/CodeGen/CGHLSLRuntime.h
M clang/lib/CodeGen/CGLoopInfo.cpp
M clang/lib/CodeGen/CGStmtOpenMP.cpp
M clang/lib/CodeGen/TargetBuiltins/ARM.cpp
M clang/lib/CodeGen/TargetBuiltins/RISCV.cpp
M clang/lib/DependencyScanning/DependencyScanningWorker.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Format/ContinuationIndenter.cpp
M clang/lib/Headers/CMakeLists.txt
M clang/lib/Headers/hlsl.h
M clang/lib/Headers/hlsl/hlsl_detail.h
A clang/lib/Headers/hlsl/hlsl_resources.h
M clang/lib/Headers/riscv_packed_simd.h
M clang/lib/Interpreter/IncrementalAction.cpp
M clang/lib/Interpreter/Interpreter.cpp
M clang/lib/Lex/HeaderSearch.cpp
M clang/lib/ScalableStaticAnalysis/Analyses/CMakeLists.txt
A clang/lib/ScalableStaticAnalysis/Analyses/VirtualMethodFamily/VirtualMethodEntityExtractor.cpp
M clang/lib/Sema/HLSLBuiltinTypeDeclBuilder.cpp
M clang/lib/Sema/HLSLBuiltinTypeDeclBuilder.h
M clang/lib/Sema/HLSLExternalSemaSource.cpp
M clang/lib/Sema/SemaARM.cpp
M clang/lib/Sema/SemaHLSL.cpp
M clang/lib/Sema/SemaOpenMP.cpp
M clang/lib/Sema/SemaType.cpp
M clang/lib/Serialization/ASTWriterStmt.cpp
M clang/lib/StaticAnalyzer/Checkers/WebKit/ASTUtils.cpp
M clang/lib/StaticAnalyzer/Checkers/WebKit/PtrTypesSemantics.cpp
M clang/lib/StaticAnalyzer/Checkers/WebKit/PtrTypesSemantics.h
M clang/lib/StaticAnalyzer/Checkers/WebKit/RawPtrRefLambdaCapturesChecker.cpp
M clang/lib/StaticAnalyzer/Checkers/WebKit/RawPtrRefSafetyModel.cpp
M clang/test/AST/HLSL/ByteAddressBuffers-AST.hlsl
A clang/test/AST/HLSL/DynamicResources-AST.hlsl
M clang/test/AST/HLSL/StructuredBuffers-AST.hlsl
M clang/test/AST/HLSL/TypedBuffers-AST.hlsl
M clang/test/AST/HLSL/matrix-alias.hlsl
M clang/test/Analysis/Checkers/WebKit/mock-canborrow.h
M clang/test/Analysis/Checkers/WebKit/unborrowed-call-args.cpp
A clang/test/Analysis/Checkers/WebKit/unborrowed-lambda-captures.cpp
M clang/test/Analysis/Checkers/WebKit/unborrowed-local-vars-cxx23.cpp
M clang/test/Analysis/Checkers/WebKit/unborrowed-local-vars.cpp
M clang/test/Analysis/Scalable/ssaf-src-edit-merge/conflict-preserves-unrelated-zero-length-insert.test
M clang/test/Analysis/Scalable/ssaf-src-edit-merge/conflict-stderr-without-sarif.test
M clang/test/Analysis/Scalable/ssaf-src-edit-merge/empty-input.test
M clang/test/Analysis/Scalable/ssaf-src-edit-merge/identical-overlap.test
M clang/test/Analysis/Scalable/ssaf-src-edit-merge/no-conflict-sarif-empty.test
M clang/test/Analysis/Scalable/ssaf-src-edit-merge/non-overlapping.test
M clang/test/Analysis/Scalable/ssaf-src-edit-merge/order-invariance.test
M clang/test/Analysis/Scalable/ssaf-src-edit-merge/parent-dir-missing.test
M clang/test/Analysis/Scalable/ssaf-src-edit-merge/pre-dedup-identical-non-zero-length.test
M clang/test/Analysis/Scalable/ssaf-src-edit-merge/pre-dedup-zero-length-insert.test
M clang/test/Analysis/Scalable/ssaf-src-edit-merge/range-overlap-cluster-of-three-sarif.test
M clang/test/Analysis/Scalable/ssaf-src-edit-merge/range-overlap-conflict-sarif.test
M clang/test/Analysis/Scalable/ssaf-src-edit-merge/sarif-out-parent-dir-missing.test
M clang/test/Analysis/Scalable/ssaf-src-edit-merge/single-input-internal-conflict.test
M clang/test/Analysis/Scalable/ssaf-src-edit-merge/single-input.test
M clang/test/Analysis/Scalable/ssaf-src-edit-merge/three-input-all-conflict.test
M clang/test/Analysis/Scalable/ssaf-src-edit-merge/three-input-conflict-sarif.test
M clang/test/Analysis/Scalable/ssaf-src-edit-merge/two-conflicts-different-offsets-sarif.test
M clang/test/Analysis/Scalable/ssaf-src-edit-merge/two-input-conflict-sarif.test
M clang/test/Analysis/Scalable/ssaf-src-edit-merge/two-input-conflict.test
M clang/test/CIR/CodeGen/assign-operator.cpp
M clang/test/CIR/CodeGen/atomic.c
A clang/test/CIR/CodeGen/builtin-memcpy.c
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M clang/test/CIR/CodeGen/union-copy-move-assignment.cpp
M clang/test/CIR/CodeGenBuiltins/builtin-bit-cast.cpp
M clang/test/CIR/CodeGenBuiltins/builtin-nondeterministic-value.c
M clang/test/CIR/CodeGenCUDA/address-spaces.cu
M clang/test/CIR/CodeGenCUDA/device-stub.cu
A clang/test/CIR/CodeGenCUDA/missing-gpubinary.cu
A clang/test/CIR/Diagnostics/mlir-error-routing.cpp
R clang/test/CIR/Diagnostics/mlir-error-routing.cu
M clang/test/CIR/IR/enum-attrs.cir
A clang/test/CIR/IR/invalid-cuda-device-binary.cir
M clang/test/CIR/Lowering/call-llvm-intrinsic.cir
R clang/test/ClangScanDeps/build-session-validation-relocated-modules.c
A clang/test/ClangScanDeps/modules-context-hash-case-sensitive-vfs-paths.c
M clang/test/ClangScanDeps/modules-context-hash-module-map-path.c
M clang/test/ClangScanDeps/modules-relocated-mm-macro.c
R clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_addv.c
R clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_len.c
A clang/test/CodeGen/AArch64/sve/addv.c
M clang/test/CodeGen/AArch64/sve/len.c
A clang/test/CodeGen/RISCV/lto-module-asm-abi.c
M clang/test/CodeGen/RISCV/rvp-intrinsics.c
M clang/test/CodeGen/align-loops.c
M clang/test/CodeGen/thread-model.c
M clang/test/CodeGenCXX/static-init-wasm.cpp
M clang/test/CodeGenHLSL/builtins/InterlockedExchange.hlsl
M clang/test/CodeGenHLSL/builtins/RWByteAddressBuffer-InterlockedExchange.hlsl
M clang/test/CodeGenHLSL/builtins/RWTexture-Interlocked.hlsl
A clang/test/CodeGenHLSL/builtins/WaveReadLaneFirst.hlsl
A clang/test/CodeGenHLSL/resources/dynamic-resources.hlsl
A clang/test/Driver/flifetime-safety-c.c
A clang/test/Driver/print-enabled-extensions/riscv-gaisler-gr765.c
M clang/test/Driver/riscv-cpus.c
A clang/test/Interpreter/HIP/hip-environment.hip
A clang/test/Interpreter/HIP/lit.local.cfg
A clang/test/Interpreter/nonexistent-xcc-file.cpp
M clang/test/Misc/target-invalid-cpu-note/riscv.c
A clang/test/Modules/implicit-module-map-path-case-sensitive.c
A clang/test/OpenMP/collapse_iv_width_codegen.cpp
R clang/test/OpenMP/error_message.c
M clang/test/OpenMP/error_message.cpp
A clang/test/OpenMP/for_loop_bitint_messages.c
M clang/test/OpenMP/parallel_message_messages.cpp
A clang/test/OpenMP/target_map_address_space_codegen.c
M clang/test/Preprocessor/init.c
M clang/test/Sema/LifetimeSafety/annotation-suggestions-fixits.c
M clang/test/Sema/LifetimeSafety/safety-c.c
M clang/test/Sema/large-bit-int.c
M clang/test/Sema/types.c
M clang/test/SemaCXX/vector.cpp
A clang/test/SemaHLSL/BuiltIns/ByteAddressBuffer-InterlockedExchangeFloat-sm60.hlsl
M clang/test/SemaHLSL/BuiltIns/InterlockedExchange-errors.hlsl
A clang/test/SemaHLSL/BuiltIns/WaveReadLaneFirst-errors.hlsl
M clang/test/SemaHLSL/Language/InitLists.hlsl
M clang/test/SemaHLSL/Resources/Textures-SampleCmpLevelZero.hlsl
A clang/test/SemaHLSL/Resources/dynamic-resources-availability.hlsl
A clang/test/SemaHLSL/Resources/dynamic-resources.hlsl
M clang/test/SemaHLSL/WaveBuiltinAvailability.hlsl
M clang/test/lit.cfg.py
M clang/tools/cir-opt/CMakeLists.txt
M clang/tools/clang-format/ClangFormat.cpp
M clang/tools/clang-repl/ClangRepl.cpp
M clang/unittests/Format/FormatTest.cpp
M clang/unittests/Lex/LexerTest.cpp
A clang/unittests/ScalableStaticAnalysis/Analyses/VirtualMethodFamily/VirtualMethodFamilyExtractorTest.cpp
A clang/unittests/ScalableStaticAnalysis/Analyses/VirtualMethodFamily/VirtualMethodFamilyTestSupport.h
M clang/unittests/ScalableStaticAnalysis/CMakeLists.txt
A clang/unittests/ScalableStaticAnalysis/ParsedAST.h
M compiler-rt/include/profile/instr_prof_interface.h
M compiler-rt/lib/profile/InstrProfiling.h
M compiler-rt/test/profile/instrprof-api.c
A cross-project-tests/.clang-format
A cross-project-tests/riscv/lit.local.cfg
A cross-project-tests/riscv/lto-inline-asm-abi.c
M flang/include/flang/Optimizer/Dialect/CUF/CUFDialect.td
M flang/include/flang/Optimizer/Dialect/FIRCG/CGOps.td
M flang/include/flang/Optimizer/Dialect/FIRDialect.td
M flang/include/flang/Optimizer/Dialect/FIROps.td
M flang/include/flang/Optimizer/Dialect/FIROpsSupport.h
M flang/include/flang/Optimizer/Dialect/MIF/MIFDialect.td
M flang/include/flang/Optimizer/HLFIR/HLFIROpBase.td
M flang/lib/Lower/Bridge.cpp
M flang/lib/Lower/OpenMP/ClauseProcessor.cpp
M flang/lib/Lower/OpenMP/Utils.cpp
M flang/lib/Lower/OpenMP/Utils.h
M flang/lib/Optimizer/Transforms/AddDebugInfo.cpp
M flang/lib/Optimizer/Transforms/CUDA/CUFDeviceFuncTransform.cpp
M flang/lib/Parser/openacc-parsers.cpp
M flang/lib/Semantics/check-omp-structure.cpp
M flang/lib/Semantics/check-omp-structure.h
M flang/lib/Semantics/check-omp-syntax.cpp
M flang/lib/Semantics/check-omp-variant.cpp
M flang/test/Fir/fir-ops.fir
A flang/test/Integration/debug-submodule-ancestor.F90
A flang/test/Integration/debug-submodule-nested.F90
M flang/test/Integration/debug-submodule-procedure.F90
M flang/test/Lower/OpenMP/declare-mapper.f90
A flang/test/Lower/OpenMP/target-map-nested-dtype-allocatable-member.f90
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M flang/test/Parser/acc-label-do.f90
M flang/test/Transforms/debug-module-submodule-procedure.fir
A flang/test/Transforms/debug-submodule.fir
M libc/config/linux/aarch64/entrypoints.txt
M libc/config/linux/riscv/entrypoints.txt
M libc/config/linux/x86_64/entrypoints.txt
M libc/include/arpa/inet.yaml
M libc/include/sys/select.yaml
M libc/src/__support/FPUtil/FEnvImpl.h
M libc/src/__support/OSUtil/linux/syscall_wrappers/CMakeLists.txt
M libc/src/__support/OSUtil/linux/syscall_wrappers/chmod.h
A libc/src/__support/OSUtil/linux/syscall_wrappers/pselect6.h
M libc/src/__support/math/bf16sub.h
M libc/src/__support/math/bf16subf.h
M libc/src/__support/math/bf16subf128.h
M libc/src/__support/math/lgammaf.h
M libc/src/__support/net/CMakeLists.txt
M libc/src/__support/net/address.cpp
M libc/src/__support/net/address.h
M libc/src/arpa/inet/CMakeLists.txt
A libc/src/arpa/inet/inet_pton.cpp
A libc/src/arpa/inet/inet_pton.h
M libc/src/sys/select/CMakeLists.txt
M libc/src/sys/select/linux/CMakeLists.txt
A libc/src/sys/select/linux/pselect.cpp
M libc/src/sys/select/linux/select.cpp
A libc/src/sys/select/pselect.h
M libc/src/sys/stat/linux/CMakeLists.txt
M libc/test/shared/shared_math_constexpr_test.cpp
M libc/test/src/arpa/inet/CMakeLists.txt
A libc/test/src/arpa/inet/inet_pton_test.cpp
M libc/test/src/sys/select/CMakeLists.txt
A libc/test/src/sys/select/pselect_test.cpp
M libc/test/src/sys/stat/CMakeLists.txt
M libc/test/src/sys/stat/chmod_test.cpp
A libcxx/docs/ABIGuarantees.md
R libcxx/docs/ABIGuarantees.rst
A libcxx/docs/AddingNewCIJobs.md
R libcxx/docs/AddingNewCIJobs.rst
A libcxx/docs/CodingGuidelines.md
R libcxx/docs/CodingGuidelines.rst
A libcxx/docs/Contributing.md
R libcxx/docs/Contributing.rst
A libcxx/docs/Contributing/NewStandardProcedure.md
R libcxx/docs/Contributing/NewStandardProcedure.rst
A libcxx/docs/Contributing/PostMeetingProcedure.md
R libcxx/docs/Contributing/PostMeetingProcedure.rst
A libcxx/docs/Contributing/ReleaseProcedure.md
R libcxx/docs/Contributing/ReleaseProcedure.rst
A libcxx/docs/DesignDocs/ABIVersioning.md
R libcxx/docs/DesignDocs/ABIVersioning.rst
A libcxx/docs/DesignDocs/AtomicDesign.md
R libcxx/docs/DesignDocs/AtomicDesign.rst
A libcxx/docs/DesignDocs/CapturingConfigInfo.md
R libcxx/docs/DesignDocs/CapturingConfigInfo.rst
A libcxx/docs/DesignDocs/ExperimentalFeatures.md
R libcxx/docs/DesignDocs/ExperimentalFeatures.rst
A libcxx/docs/DesignDocs/ExtendedCXX03Support.md
R libcxx/docs/DesignDocs/ExtendedCXX03Support.rst
A libcxx/docs/DesignDocs/FeatureTestMacros.md
R libcxx/docs/DesignDocs/FeatureTestMacros.rst
A libcxx/docs/DesignDocs/FileTimeType.md
R libcxx/docs/DesignDocs/FileTimeType.rst
A libcxx/docs/DesignDocs/HeaderRemovalPolicy.md
R libcxx/docs/DesignDocs/HeaderRemovalPolicy.rst
M libcxx/docs/conf.py
M libcxx/include/CMakeLists.txt
M libcxx/include/__algorithm/pstl.h
M libcxx/include/__chrono/duration.h
M libcxx/include/__configuration/abi.h
M libcxx/include/__locale_dir/locale_base_api.h
M libcxx/include/__locale_dir/locale_base_api/bsd_locale_fallbacks.h
M libcxx/include/__locale_dir/num.h
M libcxx/include/__locale_dir/support/aix.h
M libcxx/include/__locale_dir/support/bsd_like.h
M libcxx/include/__locale_dir/support/fuchsia.h
M libcxx/include/__locale_dir/support/linux.h
M libcxx/include/__locale_dir/support/newlib.h
M libcxx/include/__locale_dir/support/no_locale/strtonum.h
M libcxx/include/__locale_dir/support/openbsd.h
M libcxx/include/__locale_dir/support/windows.h
M libcxx/include/__ostream/print.h
M libcxx/include/__pstl/backend_fwd.h
M libcxx/include/__pstl/backends/default.h
M libcxx/include/__pstl/backends/libdispatch.h
M libcxx/include/__pstl/backends/serial.h
M libcxx/include/__pstl/backends/std_thread.h
A libcxx/include/__pstl/cpu_algos/swap_ranges.h
M libcxx/include/__ranges/adjacent_transform_view.h
M libcxx/include/__ranges/adjacent_view.h
M libcxx/include/__ranges/chunk_by_view.h
M libcxx/include/__ranges/common_view.h
M libcxx/include/__ranges/concat_view.h
M libcxx/include/__ranges/counted.h
M libcxx/include/__ranges/drop_view.h
M libcxx/include/__ranges/drop_while_view.h
M libcxx/include/__ranges/elements_view.h
M libcxx/include/__ranges/empty_view.h
M libcxx/include/__ranges/enumerate_view.h
M libcxx/include/__ranges/filter_view.h
M libcxx/include/__ranges/iota_view.h
M libcxx/include/__ranges/join_view.h
M libcxx/include/__ranges/join_with_view.h
M libcxx/include/__ranges/lazy_split_view.h
M libcxx/include/__ranges/movable_box.h
M libcxx/include/__ranges/non_propagating_cache.h
M libcxx/include/__ranges/rbegin.h
M libcxx/include/__ranges/rend.h
M libcxx/include/__ranges/reverse_view.h
M libcxx/include/__ranges/single_view.h
M libcxx/include/__ranges/split_view.h
M libcxx/include/__ranges/stride_view.h
M libcxx/include/__ranges/take_view.h
M libcxx/include/__ranges/take_while_view.h
M libcxx/include/__ranges/to.h
M libcxx/include/__ranges/transform_view.h
M libcxx/include/__ranges/views.h
M libcxx/include/__ranges/zip_transform_view.h
M libcxx/include/__ranges/zip_view.h
M libcxx/include/complex
M libcxx/include/module.modulemap.in
M libcxx/include/valarray
M libcxx/src/support/win32/locale_win32.cpp
A libcxx/test/benchmarks/algorithms/nonmodifying/pstl.find.bench.cpp
A libcxx/test/benchmarks/algorithms/sorting/pstl.sort.bench.cpp
M libcxx/test/benchmarks/containers/string.bench.cpp
A libcxx/test/benchmarks/numeric/pstl.transform_reduce.bench.cpp
M libcxx/test/libcxx/algorithms/pstl.iterator-requirements.verify.cpp
A libcxx/test/std/algorithms/alg.modifying.operations/alg.swap/pstl.swap_ranges.pass.cpp
M libcxx/test/std/algorithms/pstl.exception_handling.pass.cpp
A libcxx/test/std/numerics/complex.number/complex/complex_requires_cv_unqualified_object.verify.cpp
A libcxx/test/std/numerics/numarray/template.valarray/valarray_requires_cv_unqualified_object.verify.cpp
M libcxx/test/std/time/months.pass.cpp
M libcxx/test/std/time/years.pass.cpp
M libcxx/utils/ci/lnt/README.md
M libcxx/utils/ci/lnt/machines.json
M libcxx/utils/ci/lnt/run-benchmarks
M libcxx/utils/ci/run-buildbot
M libcxx/utils/test-at-commit
M lld/ELF/MarkLive.cpp
M lld/test/ELF/lto/riscv-target-abi.ll
M lld/test/ELF/why-live.test
M lld/test/Unit/lit.cfg.py
M lld/unittests/AsLibELF/CMakeLists.txt
M lld/unittests/AsLibELF/OutputStream.cpp
M lld/unittests/AsLibELF/ROCm.cpp
M lldb/include/lldb/Target/DynamicRegisterInfo.h
M lldb/include/lldb/Target/Process.h
M lldb/include/lldb/Utility/StructuredData.h
M lldb/packages/Python/lldbsuite/test/tools/lldb_dap/session_helpers.py
M lldb/source/API/SBProcess.cpp
M lldb/source/Commands/CommandObjectVersion.cpp
M lldb/source/Interpreter/CommandInterpreter.cpp
M lldb/source/Plugins/ObjectFile/wasm/ObjectFileWasm.cpp
M lldb/source/Plugins/Process/FreeBSD/NativeProcessFreeBSD.cpp
M lldb/source/Target/DynamicRegisterInfo.cpp
M lldb/source/Target/Process.cpp
M lldb/source/Utility/StructuredData.cpp
M lldb/test/API/python_api/process/address-masks/TestAddressMasks.py
M lldb/test/API/python_api/value/TestValueAPI.py
A lldb/test/Shell/ObjectFile/wasm/data-segment-names.yaml
A lldb/test/Shell/ScriptInterpreter/Python/nested_command_selected_target.test
M lldb/tools/lldb-dap/DAP.cpp
M lldb/tools/lldb-dap/Handler/ThreadsRequestHandler.cpp
M lldb/tools/lldb-dap/LLDBUtils.h
M llvm/cmake/modules/GetLibraryName.cmake
M llvm/docs/CommandLine.md
M llvm/docs/LFI.md
M llvm/docs/LangRef.md
M llvm/docs/Lexicon.md
M llvm/docs/ReleaseNotes.md
M llvm/docs/SphinxQuickstartTemplate.md
M llvm/docs/UndefinedBehavior.md
M llvm/include/llvm-c/Core.h
M llvm/include/llvm/Analysis/BranchProbabilityInfo.h
M llvm/include/llvm/Analysis/ConstantFolding.h
M llvm/include/llvm/Analysis/InstSimplifyFolder.h
M llvm/include/llvm/Analysis/InstructionSimplify.h
M llvm/include/llvm/Analysis/LazyValueInfo.h
M llvm/include/llvm/Analysis/Loads.h
M llvm/include/llvm/Analysis/LoopAccessAnalysis.h
M llvm/include/llvm/Analysis/ScalarEvolutionExpressions.h
M llvm/include/llvm/Analysis/SimplifyQuery.h
M llvm/include/llvm/Analysis/TargetFolder.h
M llvm/include/llvm/Analysis/TargetTransformInfo.h
M llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
M llvm/include/llvm/Analysis/ValueTracking.h
M llvm/include/llvm/AsmParser/LLParser.h
M llvm/include/llvm/AsmParser/LLToken.h
M llvm/include/llvm/Bitcode/LLVMBitCodes.h
M llvm/include/llvm/CodeGen/BasicTTIImpl.h
M llvm/include/llvm/CodeGen/ISDOpcodes.h
M llvm/include/llvm/CodeGen/MIRParser/MIParser.h
M llvm/include/llvm/CodeGen/MIRYamlMapping.h
M llvm/include/llvm/CodeGen/MachineRegisterInfo.h
M llvm/include/llvm/CodeGen/SDPatternMatch.h
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/include/llvm/CodeGen/TargetLoweringObjectFileImpl.h
M llvm/include/llvm/CodeGen/TargetRegisterInfo.h
M llvm/include/llvm/DebugInfo/GSYM/GsymCreator.h
M llvm/include/llvm/ExecutionEngine/Orc/JITTargetMachineBuilder.h
M llvm/include/llvm/IR/AutoUpgrade.h
M llvm/include/llvm/IR/ConstantFolder.h
M llvm/include/llvm/IR/IRBuilder.h
M llvm/include/llvm/IR/IRBuilderFolder.h
M llvm/include/llvm/IR/InstVisitor.h
M llvm/include/llvm/IR/Instruction.def
M llvm/include/llvm/IR/Instructions.h
M llvm/include/llvm/IR/Intrinsics.td
M llvm/include/llvm/IR/IntrinsicsDirectX.td
M llvm/include/llvm/IR/IntrinsicsRISCV.td
M llvm/include/llvm/IR/IntrinsicsSPIRV.td
M llvm/include/llvm/IR/NoFolder.h
M llvm/include/llvm/Support/AArch64MemoryHints.h
M llvm/include/llvm/Support/CommandLine.h
M llvm/include/llvm/Target/TargetSelectionDAG.td
M llvm/include/llvm/Transforms/IPO/InstrumentorUtils.h
M llvm/include/llvm/Transforms/InstCombine/InstCombiner.h
M llvm/include/llvm/Transforms/Scalar/JumpThreading.h
M llvm/include/llvm/Transforms/Utils/Local.h
M llvm/include/llvm/Transforms/Utils/LoopUtils.h
M llvm/include/llvm/Transforms/Utils/ScalarEvolutionExpander.h
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/Passes/LoadStoreVec.h
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/VecUtils.h
M llvm/lib/Analysis/BasicAliasAnalysis.cpp
M llvm/lib/Analysis/BranchProbabilityInfo.cpp
M llvm/lib/Analysis/ConstantFolding.cpp
M llvm/lib/Analysis/InstructionSimplify.cpp
M llvm/lib/Analysis/LazyValueInfo.cpp
M llvm/lib/Analysis/Loads.cpp
M llvm/lib/Analysis/LoopAccessAnalysis.cpp
M llvm/lib/Analysis/ScalarEvolution.cpp
M llvm/lib/Analysis/TargetTransformInfo.cpp
M llvm/lib/Analysis/TypeBasedAliasAnalysis.cpp
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/lib/AsmParser/LLLexer.cpp
M llvm/lib/AsmParser/LLParser.cpp
M llvm/lib/Bitcode/Reader/BitcodeReader.cpp
M llvm/lib/Bitcode/Reader/MetadataLoader.cpp
M llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
M llvm/lib/CodeGen/AllocationOrder.cpp
M llvm/lib/CodeGen/AllocationOrder.h
M llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
M llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
M llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
M llvm/lib/CodeGen/MIRParser/MIRParser.cpp
M llvm/lib/CodeGen/MIRPrinter.cpp
M llvm/lib/CodeGen/MachineRegisterInfo.cpp
M llvm/lib/CodeGen/RegAllocFast.cpp
M llvm/lib/CodeGen/RegAllocGreedy.cpp
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/lib/CodeGen/TargetLoweringBase.cpp
M llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
M llvm/lib/CodeGen/TargetRegisterInfo.cpp
M llvm/lib/DebugInfo/GSYM/GsymCreator.cpp
M llvm/lib/ExecutionEngine/Orc/ELFNixPlatform.cpp
M llvm/lib/ExecutionEngine/Orc/JITTargetMachineBuilder.cpp
M llvm/lib/ExecutionEngine/Orc/MachOPlatform.cpp
M llvm/lib/IR/AsmWriter.cpp
M llvm/lib/IR/AutoUpgrade.cpp
M llvm/lib/IR/Core.cpp
M llvm/lib/IR/Instruction.cpp
M llvm/lib/IR/Instructions.cpp
M llvm/lib/IR/RuntimeLibcalls.cpp
M llvm/lib/IR/Verifier.cpp
M llvm/lib/LTO/LTO.cpp
M llvm/lib/Linker/IRMover.cpp
M llvm/lib/MC/GOFFObjectWriter.cpp
M llvm/lib/MC/MCPseudoProbe.cpp
M llvm/lib/MC/WasmObjectWriter.cpp
M llvm/lib/Support/CommandLine.cpp
M llvm/lib/Support/StringRef.cpp
M llvm/lib/Target/AArch64/AArch64CodeLayoutOpt.cpp
M llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.h
M llvm/lib/Target/AArch64/AArch64PTrueCoalescing.cpp
M llvm/lib/Target/AArch64/AArch64PerfectShuffle.h
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
M llvm/lib/Target/AArch64/SVEInstrFormats.td
M llvm/lib/Target/AMDGPU/AMDGPU.h
M llvm/lib/Target/AMDGPU/AMDGPUGlobalISelDivergenceLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
M llvm/lib/Target/AMDGPU/AMDGPULateCodeGenPrepare.cpp
M llvm/lib/Target/AMDGPU/AMDGPUMachineFunctionInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h
M llvm/lib/Target/AMDGPU/CMakeLists.txt
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp
M llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp
A llvm/lib/Target/AMDGPU/SIPostRA16BitMovFolding.cpp
M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
M llvm/lib/Target/AMDGPU/SIRegisterInfo.h
M llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp
M llvm/lib/Target/ARM/ARMISelLowering.cpp
M llvm/lib/Target/ARM/ARMTargetMachine.cpp
M llvm/lib/Target/ARM/ARMTargetMachine.h
M llvm/lib/Target/ARM/ARMTargetObjectFile.cpp
M llvm/lib/Target/ARM/ARMTargetObjectFile.h
M llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
M llvm/lib/Target/ARM/ARMTargetTransformInfo.h
M llvm/lib/Target/AVR/AVRAsmPrinter.cpp
M llvm/lib/Target/AVR/AVRDevices.td
M llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp
M llvm/lib/Target/AVR/AVRISelLowering.cpp
M llvm/lib/Target/AVR/AVRInstrInfo.cpp
M llvm/lib/Target/AVR/AVRInstrInfo.td
M llvm/lib/Target/AVR/AVRRegisterInfo.cpp
M llvm/lib/Target/AVR/MCTargetDesc/AVRMCAsmInfo.cpp
M llvm/lib/Target/AVR/MCTargetDesc/AVRMCTargetDesc.h
R llvm/lib/Target/AVR/TODO.md
M llvm/lib/Target/BPF/BPFTargetTransformInfo.h
M llvm/lib/Target/DirectX/DXIL.td
M llvm/lib/Target/DirectX/DXILLegalizePass.cpp
M llvm/lib/Target/DirectX/DXILOpBuilder.cpp
M llvm/lib/Target/DirectX/DXILResourceAccess.cpp
M llvm/lib/Target/DirectX/DXILShaderFlags.cpp
M llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp
M llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp
M llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.h
M llvm/lib/Target/Lanai/LanaiTargetTransformInfo.h
M llvm/lib/Target/M68k/M68kExpandPseudo.cpp
M llvm/lib/Target/M68k/M68kInstrArithmetic.td
M llvm/lib/Target/M68k/M68kInstrData.td
M llvm/lib/Target/M68k/M68kInstrInfo.cpp
M llvm/lib/Target/M68k/M68kInstrInfo.h
M llvm/lib/Target/M68k/M68kTargetObjectFile.cpp
M llvm/lib/Target/M68k/M68kTargetObjectFile.h
M llvm/lib/Target/Mips/MipsAsmPrinter.cpp
M llvm/lib/Target/Mips/MipsAsmPrinter.h
M llvm/lib/Target/Mips/MipsBranchExpansion.cpp
M llvm/lib/Target/Mips/MipsCallLowering.cpp
M llvm/lib/Target/Mips/MipsFastISel.cpp
M llvm/lib/Target/Mips/MipsISelLowering.cpp
M llvm/lib/Target/Mips/MipsMachineFunction.cpp
M llvm/lib/Target/Mips/MipsRegisterInfo.cpp
M llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
M llvm/lib/Target/Mips/MipsSERegisterInfo.cpp
M llvm/lib/Target/Mips/MipsSubtarget.cpp
M llvm/lib/Target/Mips/MipsSubtarget.h
M llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.cpp
M llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.h
M llvm/lib/Target/PowerPC/PPC.h
M llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
M llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.h
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.h
M llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
M llvm/lib/Target/RISCV/RISCVExpandPseudoPostRA.cpp
M llvm/lib/Target/RISCV/RISCVExpandPseudoPreEmit.cpp
M llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.h
M llvm/lib/Target/RISCV/RISCVInstrInfoP.td
M llvm/lib/Target/RISCV/RISCVLoadStoreOptimizer.cpp
M llvm/lib/Target/RISCV/RISCVProcessors.td
M llvm/lib/Target/RISCV/RISCVSubtarget.cpp
M llvm/lib/Target/RISCV/RISCVSubtarget.h
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
M llvm/lib/Target/RISCV/RISCVZilsdOptimizer.cpp
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
M llvm/lib/Target/SystemZ/SystemZFrameLowering.cpp
M llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
M llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp
M llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.h
M llvm/lib/Target/WebAssembly/WebAssemblyCoalesceFeaturesAndStripAtomics.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.h
M llvm/lib/Target/X86/CMakeLists.txt
M llvm/lib/Target/X86/MCTargetDesc/X86MCLFIRewriter.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86MCLFIRewriter.h
M llvm/lib/Target/X86/X86.h
M llvm/lib/Target/X86/X86CodeGenPassBuilder.cpp
A llvm/lib/Target/X86/X86LFIRewritePass.cpp
M llvm/lib/Target/X86/X86PassRegistry.def
M llvm/lib/Target/X86/X86TargetMachine.cpp
M llvm/lib/Target/X86/X86TargetTransformInfo.cpp
M llvm/lib/Target/X86/X86TargetTransformInfo.h
M llvm/lib/TargetParser/AArch64TargetParser.cpp
M llvm/lib/TargetParser/Triple.cpp
M llvm/lib/Transforms/AggressiveInstCombine/TruncInstCombine.cpp
M llvm/lib/Transforms/IPO/AttributorAttributes.cpp
M llvm/lib/Transforms/IPO/Instrumentor.cpp
M llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
M llvm/lib/Transforms/InstCombine/InstCombineInternal.h
M llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp
M llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
M llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp
M llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
M llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
M llvm/lib/Transforms/Scalar/CorrelatedValuePropagation.cpp
M llvm/lib/Transforms/Scalar/JumpThreading.cpp
M llvm/lib/Transforms/Scalar/LoopFuse.cpp
M llvm/lib/Transforms/Scalar/MergeICmps.cpp
M llvm/lib/Transforms/Scalar/SROA.cpp
M llvm/lib/Transforms/Utils/Local.cpp
M llvm/lib/Transforms/Utils/LoopUnroll.cpp
M llvm/lib/Transforms/Utils/LoopUtils.cpp
M llvm/lib/Transforms/Utils/ScalarEvolutionExpander.cpp
M llvm/lib/Transforms/Utils/SimplifyCFG.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPCostAnalysis.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPCostAnalysis.h
M llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPTypeUtils.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPTypeUtils.h
M llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPUtils.cpp
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/Passes/LoadStoreVec.cpp
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/VecUtils.cpp
M llvm/lib/Transforms/Vectorize/VPlan.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
M llvm/lib/Transforms/Vectorize/VPlanHelpers.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.h
M llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
M llvm/lib/Transforms/Vectorize/VPlanUtils.h
M llvm/lib/Transforms/Vectorize/VPlanValue.h
M llvm/lib/Transforms/Vectorize/VPlanVerifier.cpp
M llvm/lib/Transforms/Vectorize/VectorCombine.cpp
M llvm/runtimes/CMakeLists.txt
M llvm/test/Analysis/CostModel/AArch64/speculative-load.ll
M llvm/test/Analysis/CostModel/RISCV/rvv-expandload-compressstore.ll
M llvm/test/Analysis/CostModel/RISCV/vp-intrinsics.ll
M llvm/test/Analysis/CostModel/X86/arith-fp.ll
M llvm/test/Analysis/CostModel/X86/speculative-load.ll
M llvm/test/Analysis/IR2Vec/Inputs/reference_default_vocab_print.txt
M llvm/test/Analysis/IR2Vec/Inputs/reference_wtd1_vocab_print.txt
M llvm/test/Analysis/IR2Vec/Inputs/reference_wtd2_vocab_print.txt
M llvm/test/Analysis/ScalarEvolution/trip-count13.ll
A llvm/test/Analysis/TypeBasedAliasAnalysis/merge-immutable.ll
A llvm/test/Assembler/bitinsert-bitextract-invalid.ll
A llvm/test/Assembler/bitinsert-bitextract.ll
M llvm/test/Bitcode/compatibility.ll
A llvm/test/Bitcode/upgrade-tbaa-struct.ll
A llvm/test/Bitcode/upgrade-tbaa-struct.ll.bc
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-undef.mir
A llvm/test/CodeGen/AArch64/bitinsert-bitextract-common-offsets.ll
A llvm/test/CodeGen/AArch64/bitinsert-bitextract-fp.ll
A llvm/test/CodeGen/AArch64/bitinsert-bitextract.ll
M llvm/test/CodeGen/AArch64/insert-subvector-res-legalization.ll
M llvm/test/CodeGen/AArch64/llvm-ir-to-intrinsic.ll
M llvm/test/CodeGen/AArch64/lowmaskedlanes.ll
M llvm/test/CodeGen/AArch64/masked-srem-scalable.ll
M llvm/test/CodeGen/AArch64/masked-urem-scalable.ll
M llvm/test/CodeGen/AArch64/sve-bf16-combines.ll
M llvm/test/CodeGen/AArch64/sve-bf16-int-converts.ll
M llvm/test/CodeGen/AArch64/sve-bitcast.ll
A llvm/test/CodeGen/AArch64/sve-fixed-length-shuffle-reverse.ll
M llvm/test/CodeGen/AArch64/sve-fpext-load.ll
M llvm/test/CodeGen/AArch64/sve-ld1-addressing-mode-reg-imm.ll
M llvm/test/CodeGen/AArch64/sve-load-store-legalisation.ll
M llvm/test/CodeGen/AArch64/sve-lsrchain.ll
M llvm/test/CodeGen/AArch64/sve-partial-reduce-dot-product.ll
M llvm/test/CodeGen/AArch64/sve-partial-reduce-wide-add.ll
M llvm/test/CodeGen/AArch64/sve-pred-selectop2.ll
M llvm/test/CodeGen/AArch64/sve-shift-trunc-combine.ll
M llvm/test/CodeGen/AArch64/sve-st1-addressing-mode-reg-imm.ll
A llvm/test/CodeGen/AArch64/sve-vector-repeat.ll
M llvm/test/CodeGen/AArch64/vec-combine-compare-to-bitmask.ll
M llvm/test/CodeGen/AArch64/vector-absolute-difference.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-phis-no-lane-mask-merging.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-phis-no-lane-mask-merging.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-used-outside-loop.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-used-outside-loop.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-structurizer.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-structurizer.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-i1.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-i1.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/merge-values-s16-true16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/usubsat.ll
M llvm/test/CodeGen/AMDGPU/add.v2i16.ll
M llvm/test/CodeGen/AMDGPU/add_sub_u64_pseudos.mir
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.32bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.48bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.64bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-non-kernel-declaration.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-dynamic-indirect-access-asan.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-dynamic-indirect-access.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-indirect-access-asan.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-indirect-access-lower-all.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-indirect-access-nested-asan.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-indirect-access-nested.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-indirect-access-no-kernel-lds-id.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-indirect-access.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_mul_one.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_pixelshader.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_raw_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_struct_buffer.ll
A llvm/test/CodeGen/AMDGPU/bitinsert-bitextract-common-offsets.ll
A llvm/test/CodeGen/AMDGPU/bitinsert-bitextract-fp.ll
A llvm/test/CodeGen/AMDGPU/bitinsert-bitextract.ll
M llvm/test/CodeGen/AMDGPU/block-should-not-be-in-alive-blocks.mir
M llvm/test/CodeGen/AMDGPU/branch-folding-implicit-def-subreg.ll
M llvm/test/CodeGen/AMDGPU/call-constant.ll
M llvm/test/CodeGen/AMDGPU/collapse-endcf.mir
M llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
M llvm/test/CodeGen/AMDGPU/divergent-branch-uniform-condition.ll
M llvm/test/CodeGen/AMDGPU/flat-saddr-load.ll
M llvm/test/CodeGen/AMDGPU/i1-copy-from-loop.ll
M llvm/test/CodeGen/AMDGPU/i1-divergent-phi-fix-sgpr-copies-assert.mir
M llvm/test/CodeGen/AMDGPU/insert-waitcnts-merge.ll
M llvm/test/CodeGen/AMDGPU/insert_waitcnt_for_precise_memory.ll
M llvm/test/CodeGen/AMDGPU/invalid-addrspacecast.ll
A llvm/test/CodeGen/AMDGPU/lds-dynamic-direct-and-indirect-use.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.buffer.load.format.f16.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.buffer.load.format.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.buffer.store.format.f16.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.buffer.store.format.f32.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.buffer.load.format.f16.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.buffer.load.format.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.buffer.store.format.f16.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.buffer.store.format.f32.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.tbuffer.load.f16.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.tbuffer.load.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.tbuffer.store.f16.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.tbuffer.store.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.tbuffer.load.f16.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.tbuffer.load.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.tbuffer.store.f16.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.tbuffer.store.ll
M llvm/test/CodeGen/AMDGPU/legalize-soffset-mbuf.ll
M llvm/test/CodeGen/AMDGPU/lirp.mir
M llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll
M llvm/test/CodeGen/AMDGPU/llc-pipeline.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.gather4.a16.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.msaa.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.a16.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.g16.encode.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.g16.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.anti-hints.mir
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.waitcnt.out.order.ll
M llvm/test/CodeGen/AMDGPU/loop_break.ll
M llvm/test/CodeGen/AMDGPU/lower-control-flow-live-intervals.mir
M llvm/test/CodeGen/AMDGPU/lower-control-flow-live-variables-update.mir
M llvm/test/CodeGen/AMDGPU/lower-control-flow-other-terminators.mir
M llvm/test/CodeGen/AMDGPU/lower-i1-copies-clear-kills.mir
M llvm/test/CodeGen/AMDGPU/lower-i1-copies-implicit-def-unstructured-loop.mir
M llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-pal.ll
M llvm/test/CodeGen/AMDGPU/mad-mix-hi-bf16.ll
M llvm/test/CodeGen/AMDGPU/mmra.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-vimage-vsample.ll
M llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands.mir
M llvm/test/CodeGen/AMDGPU/repeated-divisor.ll
M llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll
A llvm/test/CodeGen/AMDGPU/scalar_to_vector_v2bf16.ll
M llvm/test/CodeGen/AMDGPU/sgpr-scavenge-fi-stack-id.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3bf16.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3f16.v2f16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3i16.v2i16.ll
M llvm/test/CodeGen/AMDGPU/si-annotate-nested-control-flows.ll
M llvm/test/CodeGen/AMDGPU/si-init-whole-wave.mir
M llvm/test/CodeGen/AMDGPU/si-lower-control-flow-remove-redundant-block-liveintervals.mir
M llvm/test/CodeGen/AMDGPU/si-lower-control-flow.mir
M llvm/test/CodeGen/AMDGPU/si-lower-i1-copies-order-of-phi-incomings.mir
M llvm/test/CodeGen/AMDGPU/si-lower-i1-copies.mir
A llvm/test/CodeGen/AMDGPU/si-post-ra-merge-v-mov-b16.mir
M llvm/test/CodeGen/AMDGPU/sub.v2i16.ll
M llvm/test/CodeGen/AMDGPU/transform-block-with-return-to-epilog.ll
M llvm/test/CodeGen/AMDGPU/v_swap_b16.ll
M llvm/test/CodeGen/AMDGPU/vector_shuffle.packed.ll
A llvm/test/CodeGen/ARM/bitinsert-bitextract-common-offsets.ll
A llvm/test/CodeGen/ARM/bitinsert-bitextract-fp.ll
A llvm/test/CodeGen/ARM/bitinsert-bitextract.ll
M llvm/test/CodeGen/ARM/module-target-abi.ll
A llvm/test/CodeGen/DirectX/LegalizeAtomicExchangeFloat-unsupported-width.ll
A llvm/test/CodeGen/DirectX/LegalizeAtomicExchangeFloat.ll
M llvm/test/CodeGen/DirectX/LoadInput.ll
A llvm/test/CodeGen/DirectX/LongVector/wave-readlane-first.ll
M llvm/test/CodeGen/DirectX/ResourceAtomicBinOp-texture-nonscalar.ll
A llvm/test/CodeGen/DirectX/ResourceAtomicExchangeFloat.ll
M llvm/test/CodeGen/DirectX/ShaderFlags/wave-ops.ll
M llvm/test/CodeGen/DirectX/StoreOutput.ll
A llvm/test/CodeGen/DirectX/WaveReadLaneFirst.ll
A llvm/test/CodeGen/DirectX/WaveReadLaneFirst_mat.ll
M llvm/test/CodeGen/LoongArch/pr177863.ll
M llvm/test/CodeGen/M68k/Arith/divide-by-constant.ll
M llvm/test/CodeGen/M68k/Arith/smul-with-overflow.ll
M llvm/test/CodeGen/M68k/Arith/umul-with-overflow.ll
M llvm/test/CodeGen/M68k/Bits/btst.ll
M llvm/test/CodeGen/M68k/Control/cmp.ll
M llvm/test/CodeGen/M68k/Control/non-cmov-switch.ll
M llvm/test/CodeGen/M68k/Control/setcc.ll
M llvm/test/CodeGen/M68k/Data/load-extend.ll
M llvm/test/CodeGen/M68k/Data/sext-i1.ll
M llvm/test/CodeGen/M68k/register-spills.ll
A llvm/test/CodeGen/MIR/AMDGPU/register-allocation-antihints-mir-print-parse.mir
M llvm/test/CodeGen/Mips/extins.ll
A llvm/test/CodeGen/PowerPC/bitinsert-bitextract-common-offsets.ll
A llvm/test/CodeGen/PowerPC/bitinsert-bitextract-fp.ll
A llvm/test/CodeGen/PowerPC/bitinsert-bitextract.ll
A llvm/test/CodeGen/RISCV/bitinsert-bitextract-common-offsets.ll
A llvm/test/CodeGen/RISCV/bitinsert-bitextract-fp.ll
A llvm/test/CodeGen/RISCV/bitinsert-bitextract.ll
M llvm/test/CodeGen/RISCV/module-asm-features.ll
M llvm/test/CodeGen/RISCV/riscv-func-target-feature.ll
M llvm/test/CodeGen/RISCV/rvp-simd-32.ll
M llvm/test/CodeGen/RISCV/rvp-simd-64.ll
M llvm/test/CodeGen/RISCV/rvv/compressstore.ll
M llvm/test/CodeGen/RISCV/rvv/expandload.ll
M llvm/test/CodeGen/RISCV/rvv/trunc-select-to-max-usat.ll
R llvm/test/CodeGen/RISCV/sifive-interrupt-attr-err.ll
M llvm/test/CodeGen/RISCV/sifive-interrupt-attr.ll
M llvm/test/CodeGen/RISCV/sifive-interrupt-frame-flags.ll
A llvm/test/CodeGen/RISCV/sifive-interrupt-frame-pointer.ll
A llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_long_vector/wave-readlane-first.ll
A llvm/test/CodeGen/SPIRV/hlsl-intrinsics/WaveReadLaneFirst.ll
A llvm/test/CodeGen/SPIRV/hlsl-intrinsics/WaveReadLaneFirst_mat.ll
M llvm/test/CodeGen/SystemZ/atomicrmw-fadd-04.ll
M llvm/test/CodeGen/SystemZ/cmpxchg-01.ll
M llvm/test/CodeGen/SystemZ/cmpxchg-02.ll
A llvm/test/CodeGen/SystemZ/dead-cc-defs.ll
M llvm/test/CodeGen/SystemZ/zos-section-1.ll
M llvm/test/CodeGen/SystemZ/zos-section-2.ll
M llvm/test/CodeGen/SystemZ/zos-symbol-2.ll
R llvm/test/CodeGen/WebAssembly/coalesce-features-thread-model.ll
A llvm/test/CodeGen/X86/GlobalISel/bitinsert-bitextract.ll
M llvm/test/CodeGen/X86/bfloat.ll
A llvm/test/CodeGen/X86/bitinsert-bitextract-common-offsets.ll
A llvm/test/CodeGen/X86/bitinsert-bitextract-fp.ll
A llvm/test/CodeGen/X86/bitinsert-bitextract.ll
M llvm/test/CodeGen/X86/dag-topological-sort.ll
A llvm/test/CodeGen/X86/lfi-align.ll
M llvm/test/CodeGen/X86/llvm.frexp.ll
M llvm/test/CodeGen/X86/load-partial-dot-product.ll
A llvm/test/CodeGen/X86/regallocfast-implicit-def-live-out.mir
A llvm/test/CodeGen/X86/vec_setcc-3.ll
M llvm/test/Instrumentation/DataFlowSanitizer/origin_load.ll
M llvm/test/Instrumentation/DataFlowSanitizer/origin_select.ll
M llvm/test/Instrumentation/DataFlowSanitizer/origin_store.ll
M llvm/test/Instrumentation/InstrProfiling/conditional-counter-updates.ll
M llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-vmax.ll
M llvm/test/Instrumentation/SanitizerCoverage/missing_dbg.ll
A llvm/test/Instrumentation/SanitizerCoverage/missing_dbg_stack_depth.ll
M llvm/test/LTO/RISCV/module-asm.ll
M llvm/test/MC/RISCV/mapping-across-sections.s
M llvm/test/MC/WebAssembly/reloc-pic64.s
A llvm/test/MC/X86/LFI/control-flow-errors.s
A llvm/test/MC/X86/LFI/control-flow.s
M llvm/test/Transforms/AggressiveInstCombine/trunc_unreachable_bb.ll
A llvm/test/Transforms/Attributor/callback-noalias.ll
M llvm/test/Transforms/Attributor/callbacks.ll
M llvm/test/Transforms/ConstraintElimination/analysis-invalidation.ll
M llvm/test/Transforms/InstCombine/AMDGPU/llvm.amdgcn.sudot.ll
M llvm/test/Transforms/InstCombine/struct-assign-tbaa.ll
A llvm/test/Transforms/LoopFusion/guard_skip_empty_block.ll
M llvm/test/Transforms/LoopStrengthReduce/AArch64/vscale-fixups.ll
M llvm/test/Transforms/LoopVectorize/AArch64/conditional-scalar-assignment-fold-tail.ll
M llvm/test/Transforms/LoopVectorize/AArch64/conditional-scalar-assignment.ll
A llvm/test/Transforms/LoopVectorize/AArch64/diff-checks-force-interleave-count.ll
M llvm/test/Transforms/LoopVectorize/AArch64/early_exit_costs.ll
M llvm/test/Transforms/LoopVectorize/AArch64/epilog-vectorization-widen-inductions.ll
A llvm/test/Transforms/LoopVectorize/AArch64/low-trip-count-fixed-vf-no-epilogue.ll
M llvm/test/Transforms/LoopVectorize/AArch64/simple_early_exit.ll
M llvm/test/Transforms/LoopVectorize/AArch64/single-early-exit-interleave.ll
A llvm/test/Transforms/LoopVectorize/AArch64/sve-induction-wrapflags.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-low-trip-count.ll
M llvm/test/Transforms/LoopVectorize/RISCV/conditional-scalar-assignment-fold-tail.ll
M llvm/test/Transforms/LoopVectorize/RISCV/conditional-scalar-assignment.ll
M llvm/test/Transforms/LoopVectorize/RISCV/countable-early-exit-no-epilogue.ll
M llvm/test/Transforms/LoopVectorize/RISCV/early-exit-live-out.ll
M llvm/test/Transforms/LoopVectorize/RISCV/short-trip-count.ll
M llvm/test/Transforms/LoopVectorize/RISCV/sink-to-early-exit.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-complex-mask.ll
M llvm/test/Transforms/LoopVectorize/VPlan/execution-frequencies-match-bfi.ll
M llvm/test/Transforms/LoopVectorize/VPlan/uncountable-early-exit-vplan.ll
M llvm/test/Transforms/LoopVectorize/X86/conditional-scalar-assignment.ll
M llvm/test/Transforms/LoopVectorize/X86/pr36524.ll
M llvm/test/Transforms/LoopVectorize/X86/predicated-instruction-cost.ll
M llvm/test/Transforms/LoopVectorize/X86/x86-interleaved-accesses-masked-group.ll
M llvm/test/Transforms/LoopVectorize/dereferenceable-info-from-assumption-constant-size.ll
M llvm/test/Transforms/LoopVectorize/early-exit-calls.ll
M llvm/test/Transforms/LoopVectorize/early-exit-live-out-extract-lane.ll
M llvm/test/Transforms/LoopVectorize/early-exit-load-live-out.ll
M llvm/test/Transforms/LoopVectorize/early-exit-unary-ops.ll
M llvm/test/Transforms/LoopVectorize/find-last-ptr-induction.ll
M llvm/test/Transforms/LoopVectorize/induction-wrapflags.ll
M llvm/test/Transforms/LoopVectorize/induction.ll
M llvm/test/Transforms/LoopVectorize/iv-select-cmp-non-const-iv-start.ll
M llvm/test/Transforms/LoopVectorize/iv-select-cmp-trunc.ll
M llvm/test/Transforms/LoopVectorize/iv-select-cmp.ll
M llvm/test/Transforms/LoopVectorize/multiple-early-exits.ll
M llvm/test/Transforms/LoopVectorize/pr30654-phiscev-sext-trunc.ll
M llvm/test/Transforms/LoopVectorize/pr35773.ll
M llvm/test/Transforms/LoopVectorize/predicated-early-exits-interleave.ll
M llvm/test/Transforms/LoopVectorize/predicated-inductions.ll
M llvm/test/Transforms/LoopVectorize/predicated-multiple-exits.ll
M llvm/test/Transforms/LoopVectorize/predicated-single-exit.ll
M llvm/test/Transforms/LoopVectorize/replicate-region-branch-weights.ll
M llvm/test/Transforms/LoopVectorize/single-early-exit-cond-poison.ll
M llvm/test/Transforms/LoopVectorize/single-early-exit-deref-assumptions.ll
M llvm/test/Transforms/LoopVectorize/single-early-exit-interleave-only.ll
M llvm/test/Transforms/LoopVectorize/single-early-exit-interleave.ll
M llvm/test/Transforms/LoopVectorize/single-value-blend-phis.ll
M llvm/test/Transforms/LoopVectorize/single_early_exit.ll
M llvm/test/Transforms/LoopVectorize/single_early_exit_live_outs.ll
M llvm/test/Transforms/LoopVectorize/sink-to-early-exit.ll
M llvm/test/Transforms/LoopVectorize/vector-loop-backedge-elimination-early-exit.ll
M llvm/test/Transforms/LoopVectorize/vector-loop-backedge-elimination-predicated-early-exit.ll
M llvm/test/Transforms/MemCpyOpt/vscale-crashes.ll
M llvm/test/Transforms/OpenMP/parallel_deletion.ll
R llvm/test/Transforms/PGOProfile/Inputs/indirect_call.proftext
M llvm/test/Transforms/PGOProfile/indirect_call_annotation.ll
M llvm/test/Transforms/PhaseOrdering/X86/avg.ll
M llvm/test/Transforms/PhaseOrdering/X86/vector-reductions.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/abs-mul-buildvector-in-loop.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/div.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/fma-reduce-regression.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/gather-buildvector-with-minbitwidth-user.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/lcssa-phi-extract-scale.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/loop-accumulator-reduction.ll
A llvm/test/Transforms/SLPVectorizer/AArch64/ordered-reduction-of-loads.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/recalc-copyable-deps-on-reorder.ll
A llvm/test/Transforms/SLPVectorizer/AArch64/reduced-value-next-to-fused-fmul.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/splat-gather-subtree-cost.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/splat-gather-subtree-drop-schedule.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/splat-gather-subtree-drop.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/splat-gather-subtree-keep-drop.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/splat-gather-subtree-loop-extracts.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/splat-gather-subtree-reuse.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/splat-gather-subtree-satd.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/splat-gather-subtree-store-chain.ll
A llvm/test/Transforms/SLPVectorizer/AMDGPU/cross-block-fmul-fadd.ll
A llvm/test/Transforms/SLPVectorizer/AMDGPU/fmul-sunk-into-fadd-block.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/buildvector-all-external-scalars.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/complex-loads.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/ordered-reduction.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/partial-vec-invalid-cost.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/reordered-buildvector-scalars.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/splat-gather-extracts.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/splat-gather-trim-combined.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/splat-gather-trim.ll
A llvm/test/Transforms/SLPVectorizer/RISCV/trimmed-node-matching-gather.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/wide-load-reduction.ll
M llvm/test/Transforms/SLPVectorizer/X86/deleted-instructions-clear.ll
M llvm/test/Transforms/SLPVectorizer/X86/div-possibly-extended-with-poisons.ll
M llvm/test/Transforms/SLPVectorizer/X86/external-bin-op-user.ll
A llvm/test/Transforms/SLPVectorizer/X86/extracted-subfields-shifted-trunc.ll
M llvm/test/Transforms/SLPVectorizer/X86/extracted-subfields.ll
M llvm/test/Transforms/SLPVectorizer/X86/gathered-loads-non-full-reg.ll
M llvm/test/Transforms/SLPVectorizer/X86/lookahead.ll
A llvm/test/Transforms/SLPVectorizer/X86/narrowed-reduction-gathered-leftover-leaf.ll
M llvm/test/Transforms/SLPVectorizer/X86/original-inst-scheduled-after-copyable.ll
M llvm/test/Transforms/SLPVectorizer/X86/reassoc-copyable-in-another-entry.ll
M llvm/test/Transforms/SLPVectorizer/X86/reassoc-flattened-copyable-operand.ll
M llvm/test/Transforms/SLPVectorizer/X86/reorder_phi.ll
M llvm/test/Transforms/SLPVectorizer/X86/select-copyable-cmp-poison.ll
M llvm/test/Transforms/SLPVectorizer/X86/split-node-reorder-node-with-ops.ll
M llvm/test/Transforms/SLPVectorizer/X86/subvector-minbitwidth-unsigned-value.ll
A llvm/test/Transforms/SLPVectorizer/X86/trimmed-node-matching-gather-emitted-first.ll
M llvm/test/Transforms/SLPVectorizer/X86/trimmed-subtree-schedule.ll
A llvm/test/Transforms/SROA/load-store-overlap.ll
A llvm/test/Transforms/SimplifyCFG/AArch64/speculate-vector-phi-select-cost.ll
A llvm/test/Transforms/SimplifyCFG/ARM/speculate-vector-phi-select-cost.ll
A llvm/test/Transforms/SimplifyCFG/RISCV/speculate-mask-phi-select-cost.ll
A llvm/test/Transforms/SimplifyCFG/X86/speculate-mask-phi-select-cost.ll
A llvm/test/Transforms/SimplifyCFG/fold-branch-to-common-dest-call-debugloc.ll
A llvm/test/Transforms/Util/DeclareRuntimeLibcalls/divmod.ll
A llvm/test/Verifier/bitextract-bitinsert-invalid-verifier.ll
A llvm/test/Verifier/byval-scalable.ll
A llvm/test/Verifier/vector-repeat-intrinsic-invalid.ll
A llvm/test/Verifier/vector-repeat-intrinsic-valid.ll
A llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/placeholder_escape.ll
A llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/placeholder_escape.ll.expected
A llvm/test/tools/UpdateTestChecks/update_test_checks/placeholder_escape.test
A llvm/test/tools/llubi/main_declaration.ll
A llvm/test/tools/llvm-gsymutil/X86/macho-last-symbol-section-end.yaml
M llvm/test/tools/llvm-ir2vec/entities.ll
M llvm/test/tools/llvm-ir2vec/triplets.ll
M llvm/test/tools/llvm-objdump/MachO/AArch64/macho-arm64-subtypes.test
M llvm/test/tools/llvm-objdump/MachO/universal-arm64.test
A llvm/test/tools/llvm-readobj/ELF/RISCV/eflags-abi.test
M llvm/tools/dsymutil/DwarfLinkerForBinary.h
M llvm/tools/llubi/llubi.cpp
M llvm/tools/llvm-c-test/echo.cpp
M llvm/tools/llvm-cov/CodeCoverage.cpp
M llvm/tools/llvm-gsymutil/llvm-gsymutil.cpp
M llvm/tools/llvm-jitlink/llvm-jitlink.cpp
M llvm/tools/llvm-objdump/COFFDump.h
M llvm/tools/llvm-objdump/ELFDump.h
M llvm/tools/llvm-objdump/OffloadDump.cpp
M llvm/tools/llvm-objdump/WasmDump.h
M llvm/tools/llvm-profgen/PerfReader.h
M llvm/tools/llvm-readobj/ELFDumper.cpp
M llvm/unittests/ADT/StringRefTest.cpp
M llvm/unittests/Analysis/IR2VecTest.cpp
M llvm/unittests/Analysis/ValueTrackingTest.cpp
M llvm/unittests/CodeGen/AllocationOrderTest.cpp
M llvm/unittests/CodeGen/GlobalISel/LegalizerHelperTest.cpp
M llvm/unittests/CodeGen/SelectionDAGNodeConstructionTest.cpp
M llvm/unittests/CodeGen/SelectionDAGPatternMatchTest.cpp
M llvm/unittests/FileCheck/FileCheckTest.cpp
M llvm/unittests/Support/CommandLineTest.cpp
M llvm/unittests/Transforms/Vectorize/VPlanVerifierTest.cpp
M llvm/utils/UpdateTestChecks/common.py
M llvm/utils/gn/secondary/clang/lib/Headers/BUILD.gn
M llvm/utils/gn/secondary/clang/tools/driver/BUILD.gn
M llvm/utils/gn/secondary/clang/unittests/offload-arch/BUILD.gn
M llvm/utils/gn/secondary/lld/unittests/AsLibELF/BUILD.gn
M llvm/utils/gn/secondary/lldb/source/Target/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/ABI/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/Target/AMDGPU/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/Target/X86/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/TargetParser/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/DebugInfo/LogicalView/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/DebugInfo/PDB/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/TargetParser/BUILD.gn
M llvm/utils/lit/lit/main.py
M llvm/utils/lit/lit/util.py
A llvm/utils/lit/tests/unit/Histogram.py
M mlir/docs/DefiningDialects/Operations.md
M mlir/docs/DefiningDialects/_index.md
M mlir/docs/Interfaces.md
M mlir/docs/ReleaseNotes.md
M mlir/examples/toy/Ch4/include/toy/Ops.td
M mlir/examples/toy/Ch5/include/toy/Ops.td
M mlir/examples/toy/Ch6/include/toy/Ops.td
M mlir/examples/toy/Ch7/include/toy/Ops.td
M mlir/include/mlir-c/Rewrite.h
M mlir/include/mlir/Dialect/AMDGPU/IR/AMDGPUBase.td
M mlir/include/mlir/Dialect/Affine/IR/AffineOps.td
M mlir/include/mlir/Dialect/Arith/IR/ArithBase.td
M mlir/include/mlir/Dialect/ArmNeon/ArmNeon.td
M mlir/include/mlir/Dialect/ArmSME/IR/ArmSME.td
M mlir/include/mlir/Dialect/ArmSVE/IR/ArmSVE.td
M mlir/include/mlir/Dialect/Async/IR/AsyncDialect.td
M mlir/include/mlir/Dialect/Bufferization/IR/BufferizationBase.td
M mlir/include/mlir/Dialect/Complex/IR/ComplexBase.td
M mlir/include/mlir/Dialect/ControlFlow/IR/ControlFlowOps.td
M mlir/include/mlir/Dialect/DLTI/DLTIBase.td
M mlir/include/mlir/Dialect/EmitC/IR/EmitCBase.td
M mlir/include/mlir/Dialect/Func/IR/FuncOps.td
M mlir/include/mlir/Dialect/GPU/IR/GPUBase.td
M mlir/include/mlir/Dialect/IRDL/IR/IRDL.td
M mlir/include/mlir/Dialect/Index/IR/IndexDialect.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMDialect.td
M mlir/include/mlir/Dialect/LLVMIR/NVVMDialect.td
M mlir/include/mlir/Dialect/LLVMIR/ROCDLDialect.td
M mlir/include/mlir/Dialect/LLVMIR/VCIXOps.td
M mlir/include/mlir/Dialect/LLVMIR/XeVMOps.td
M mlir/include/mlir/Dialect/Linalg/IR/LinalgBase.td
M mlir/include/mlir/Dialect/Linalg/IR/LinalgInterfaces.td
M mlir/include/mlir/Dialect/MLProgram/IR/MLProgramBase.td
M mlir/include/mlir/Dialect/MPI/IR/MPI.td
M mlir/include/mlir/Dialect/Math/IR/MathBase.td
M mlir/include/mlir/Dialect/MemRef/IR/MemRefBase.td
M mlir/include/mlir/Dialect/NVGPU/IR/NVGPU.td
M mlir/include/mlir/Dialect/OpenACC/OpenACCBase.td
M mlir/include/mlir/Dialect/OpenACC/OpenACCOpsInterfaces.td
M mlir/include/mlir/Dialect/OpenMP/OpenMPDialect.td
M mlir/include/mlir/Dialect/OpenMP/OpenMPOpsInterfaces.td
M mlir/include/mlir/Dialect/PDL/IR/PDLDialect.td
M mlir/include/mlir/Dialect/PDLInterp/IR/PDLInterpOps.td
M mlir/include/mlir/Dialect/Ptr/IR/PtrDialect.td
M mlir/include/mlir/Dialect/Quant/IR/QuantBase.td
M mlir/include/mlir/Dialect/SCF/IR/SCFOps.td
M mlir/include/mlir/Dialect/SMT/IR/SMTDialect.td
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBase.td
M mlir/include/mlir/Dialect/Shape/IR/ShapeBase.td
M mlir/include/mlir/Dialect/Shard/IR/ShardBase.td
M mlir/include/mlir/Dialect/SparseTensor/IR/SparseTensorBase.td
M mlir/include/mlir/Dialect/SparseTensor/IR/SparseTensorInterfaces.td
M mlir/include/mlir/Dialect/Tensor/IR/TensorBase.td
M mlir/include/mlir/Dialect/Tosa/IR/TosaOpBase.td
M mlir/include/mlir/Dialect/Transform/IR/TransformDialect.td
M mlir/include/mlir/Dialect/UB/IR/UBOps.td
M mlir/include/mlir/Dialect/Vector/IR/Vector.td
M mlir/include/mlir/Dialect/Vector/Transforms/VectorTransforms.h
M mlir/include/mlir/Dialect/WasmSSA/IR/WasmSSABase.td
M mlir/include/mlir/Dialect/WasmSSA/IR/WasmSSAInterfaces.td
M mlir/include/mlir/Dialect/X86/X86.td
M mlir/include/mlir/Dialect/XeGPU/IR/XeGPUDialect.td
M mlir/include/mlir/IR/BuiltinOps.td
M mlir/include/mlir/IR/DialectBase.td
M mlir/include/mlir/IR/OpDefinition.h
M mlir/include/mlir/IR/OpImplementation.h
M mlir/include/mlir/IR/OperationSupport.h
M mlir/include/mlir/Interfaces/ControlFlowInterfaces.td
M mlir/lib/CAPI/Transforms/Rewrite.cpp
M mlir/lib/Conversion/XeVMToLLVM/XeVMToLLVM.cpp
M mlir/lib/Dialect/Bufferization/Transforms/OneShotAnalysis.cpp
M mlir/lib/Dialect/IRDL/IR/IRDL.cpp
M mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
M mlir/lib/Dialect/Linalg/Transforms/BufferizableOpInterfaceImpl.cpp
M mlir/lib/Dialect/OpenACC/Transforms/ACCRoutineLowering.cpp
M mlir/lib/Dialect/Quant/Transforms/NormalizeQuantTypes.cpp
M mlir/lib/Dialect/Tensor/Transforms/ScalarizeFunctionResult.cpp
M mlir/lib/Dialect/Tosa/Transforms/TosaProfileCompliance.cpp
M mlir/lib/Dialect/Vector/Transforms/VectorMaskElimination.cpp
M mlir/lib/IR/AsmPrinter.cpp
M mlir/lib/IR/OperationSupport.cpp
M mlir/lib/Target/IRDLToCpp/IRDLToCpp.cpp
M mlir/lib/Target/LLVMIR/Dialect/LLVMIR/LLVMToLLVMIRTranslation.cpp
M mlir/python/mlir/dialects/ext.py
M mlir/test/Analysis/DataFlow/test-last-modified-callgraph.mlir
M mlir/test/Analysis/DataFlow/test-last-modified.mlir
M mlir/test/Analysis/DataFlow/test-next-access.mlir
M mlir/test/Analysis/DataFlow/test-strided-metadata-range-analysis.mlir
M mlir/test/CAPI/CMakeLists.txt
M mlir/test/CAPI/rewrite.c
M mlir/test/Dialect/Affine/affine-loop-normalize.mlir
M mlir/test/Dialect/Affine/int-range-interface.mlir
M mlir/test/Dialect/Affine/simplify-min-max-ops.mlir
M mlir/test/Dialect/Affine/simplify-with-bounds.mlir
M mlir/test/Dialect/Affine/transform-op-simplify-min-max-ops.mlir
M mlir/test/Dialect/Arith/int-range-analysis-convergence.mlir
M mlir/test/Dialect/Arith/int-range-interface.mlir
M mlir/test/Dialect/Arith/int-range-loop-iter-args.mlir
M mlir/test/Dialect/Arith/int-range-narrowing.mlir
M mlir/test/Dialect/Arith/int-range-opts-bug-119045.mlir
M mlir/test/Dialect/Arith/int-range-opts.mlir
M mlir/test/Dialect/GPU/int-range-interface-cluster.mlir
M mlir/test/Dialect/GPU/int-range-interface.mlir
M mlir/test/Dialect/Linalg/one-shot-bufferize-analysis.mlir
M mlir/test/Dialect/Linalg/one-shot-bufferize.mlir
M mlir/test/Dialect/MLProgram/pipeline-globals.mlir
M mlir/test/Dialect/MemRef/int-range-inference.mlir
M mlir/test/Dialect/NVGPU/invalid.mlir
M mlir/test/Dialect/OpenACC/acc-implicit-routine.mlir
M mlir/test/Dialect/Tensor/int-range-inference.mlir
M mlir/test/Dialect/Tensor/one-shot-bufferize.mlir
M mlir/test/Dialect/Vector/eliminate-masks.mlir
M mlir/test/Dialect/Vector/int-range-interface.mlir
M mlir/test/Dialect/Vector/one-shot-bufferize.mlir
M mlir/test/IR/attribute.mlir
M mlir/test/IR/module-op.mlir
A mlir/test/Integration/Dialect/XeGPU/WG/simple_gemm_bf16.mlir
R mlir/test/Integration/Dialect/XeGPU/WG/simple_mxfp_gemm.mlir
A mlir/test/Integration/Dialect/XeGPU/WG/simple_mxfp_gemm_F4.mlir
A mlir/test/Integration/Dialect/XeGPU/WG/simple_mxfp_gemm_F8.mlir
M mlir/test/Integration/Dialect/XeGPU/WG/simple_mxfp_gemm_dequantizeB_F4.mlir
A mlir/test/Integration/Dialect/XeGPU/WG/simple_mxfp_gemm_dequantizeB_F8.mlir
M mlir/test/Integration/Dialect/XeGPU/WG/simple_mxfp_gemm_quantizeA_F4.mlir
A mlir/test/Integration/Dialect/XeGPU/WG/simple_mxfp_gemm_quantizeA_F8.mlir
M mlir/test/Interfaces/InferIntRangeInterface/infer-int-range-test-ops-invalid.mlir
M mlir/test/Interfaces/InferIntRangeInterface/infer-int-range-test-ops.mlir
M mlir/test/Target/LLVMIR/llvmir.mlir
M mlir/test/Transforms/loop-invariant-code-motion.mlir
M mlir/test/Transforms/make-composed-folded-affine-apply.mlir
M mlir/test/Transforms/sccp-callgraph.mlir
M mlir/test/Transforms/test-symbol-dce.mlir
M mlir/test/lib/Dialect/Test/TestOps.td
M mlir/test/lib/Dialect/Test/TestOpsSyntax.td
M mlir/test/lib/Dialect/TestIRDLToCpp/test_irdl_to_cpp.irdl.mlir
M mlir/test/lib/Dialect/Vector/TestVectorTransforms.cpp
M mlir/test/mlir-tblgen/constant-str-attr-invalid.mlir
M mlir/test/mlir-tblgen/op-decl-and-defs.td
M mlir/test/mlir-tblgen/op-format-invalid.td
M mlir/test/mlir-tblgen/op-format.mlir
M mlir/test/mlir-tblgen/op-format.td
M mlir/test/mlir-tblgen/op-interface.td
M mlir/test/mlir-tblgen/pattern.mlir
M mlir/test/python/dialects/ext.py
M mlir/test/python/dialects/ml_program.py
M mlir/test/python/dialects/python_test.py
M mlir/test/python/python_test_ops.td
M mlir/tools/mlir-tblgen/OpDefinitionsGen.cpp
M mlir/tools/mlir-tblgen/OpFormatGen.cpp
M mlir/tools/mlir-tblgen/OpInterfacesGen.cpp
M offload/include/OpenMP/OMPT/Callback.h
M offload/include/OpenMP/OMPT/Interface.h
M offload/include/Shared/SourceInfo.h
M offload/include/device.h
M offload/liboffload/src/OffloadImpl.cpp
M offload/libompaccsupport/PluginManager.cpp
M offload/libompaccsupport/device.cpp
M offload/libomptarget/OffloadRTL.cpp
M offload/libomptarget/OpenMP/OMPT/Callback.cpp
M offload/plugins-nextgen/amdgpu/src/rtl.cpp
M offload/plugins-nextgen/common/include/PluginInterface.h
M offload/plugins-nextgen/common/src/PluginInterface.cpp
M offload/plugins-nextgen/cuda/src/rtl.cpp
M offload/plugins-nextgen/host/src/rtl.cpp
M offload/test/offloading/info.c
M openmp/docs/ReleaseNotes.md
M orc-rt/cmake/OrcRTTesting.cmake
M orc-rt/include/CMakeLists.txt
A orc-rt/include/orc-rt-c/support/LogLevel.h
M orc-rt/include/orc-rt-c/support/Logging.h
M orc-rt/include/orc-rt/bedrock/BootstrapInfo.h
M orc-rt/include/orc-rt/bedrock/ConnectorRegistry.h
M orc-rt/include/orc-rt/bedrock/Session.h
M orc-rt/include/orc-rt/bedrock/SocketConnector.h
M orc-rt/include/orc-rt/bedrock/sps/SimpleRemoteCAOverSocket.h
M orc-rt/include/orc-rt/support/Error.h
M orc-rt/include/orc-rt/support/bind.h
M orc-rt/include/orc-rt/support/move_only_function.h
M orc-rt/lib/bedrock/BootstrapInfo.cpp
M orc-rt/lib/bedrock/ConnectorRegistry.cpp
M orc-rt/lib/bedrock/NativeDylibManager.cpp
M orc-rt/lib/bedrock/Session.cpp
M orc-rt/lib/bedrock/sys/posix/SocketConnector.cpp
M orc-rt/lib/bedrock/sys/posix/sps/SimpleRemoteCAOverSocket.cpp
A orc-rt/test/regression/README.md
R orc-rt/test/regression/check-rt-process-info.test
R orc-rt/test/regression/darwin/lit.local.cfg
R orc-rt/test/regression/init.test
A orc-rt/test/regression/jit-free-foundations/check-rt-process-info.test
A orc-rt/test/regression/jit-free-foundations/lit.local.cfg
A orc-rt/test/regression/jit-free-foundations/logging/lit.local.cfg
A orc-rt/test/regression/jit-free-foundations/logging/os_log/delivery.test
A orc-rt/test/regression/jit-free-foundations/logging/os_log/lit.local.cfg
A orc-rt/test/regression/jit-free-foundations/logging/os_log/no-printf-output.test
A orc-rt/test/regression/jit-free-foundations/logging/printf-backend/bad-level.test
A orc-rt/test/regression/jit-free-foundations/logging/printf-backend/debug-compiled-out.test
A orc-rt/test/regression/jit-free-foundations/logging/printf-backend/debug-level.test
A orc-rt/test/regression/jit-free-foundations/logging/printf-backend/format.test
A orc-rt/test/regression/jit-free-foundations/logging/printf-backend/level-off.test
A orc-rt/test/regression/jit-free-foundations/logging/printf-backend/lit.local.cfg
A orc-rt/test/regression/jit-free-foundations/logging/printf-backend/output-redirect.test
A orc-rt/test/regression/jit-free-foundations/logging/printf-backend/runtime-level.test
A orc-rt/test/regression/jit-free-foundations/ogre-help.test
A orc-rt/test/regression/jit-free-foundations/smoke-check.test
A orc-rt/test/regression/languages/c/lit.local.cfg
A orc-rt/test/regression/languages/c/return-zero.c
R orc-rt/test/regression/linux/lit.local.cfg
M orc-rt/test/regression/lit.cfg.py
R orc-rt/test/regression/logging/lit.local.cfg
R orc-rt/test/regression/logging/os_log/delivery.test
R orc-rt/test/regression/logging/os_log/lit.local.cfg
R orc-rt/test/regression/logging/os_log/no-printf-output.test
R orc-rt/test/regression/logging/printf-backend/bad-level.test
R orc-rt/test/regression/logging/printf-backend/debug-compiled-out.test
R orc-rt/test/regression/logging/printf-backend/debug-level.test
R orc-rt/test/regression/logging/printf-backend/format.test
R orc-rt/test/regression/logging/printf-backend/level-off.test
R orc-rt/test/regression/logging/printf-backend/lit.local.cfg
R orc-rt/test/regression/logging/printf-backend/output-redirect.test
R orc-rt/test/regression/logging/printf-backend/runtime-level.test
A orc-rt/test/regression/object-formats/lit.local.cfg
A orc-rt/test/regression/object-formats/mach-o/arm64/lit.local.cfg
A orc-rt/test/regression/object-formats/mach-o/arm64/return-zero.s
A orc-rt/test/regression/object-formats/mach-o/lit.local.cfg
R orc-rt/test/regression/smoke-check.test
M orc-rt/test/unit/CMakeLists.txt
M orc-rt/test/unit/CommonTestUtils.h
M orc-rt/test/unit/bedrock/InProcessControllerAccessTest.cpp
M orc-rt/test/unit/bedrock/SessionTest.cpp
M orc-rt/test/unit/bedrock/SocketTestUtils.h
M orc-rt/test/unit/bedrock/sps/SimpleRemoteCAOverSocketTest.cpp
M orc-rt/test/unit/bedrock/sps/SimpleRemoteCATest.cpp
A orc-rt/test/unit/bedrock/sys/posix/SocketConnectorTest.cpp
M orc-rt/test/unit/bedrock/sys/posix/SocketTestUtils.cpp
M orc-rt/test/unit/support/ErrorTest.cpp
M orc-rt/test/unit/support/LoggingTest.cpp
M orc-rt/test/unit/support/bind-test.cpp
M orc-rt/test/unit/support/move_only_function-test.cpp
M orc-rt/tools/ogre/ogre.cpp
M polly/lib/Analysis/ScopBuilder.cpp
M polly/test/ScopInfo/issue190128.ll
M polly/test/ScopInfo/simple_loop_unsigned.ll
A polly/test/ScopInfo/user-assumption-cached-precondition.ll
A polly/test/ScopInfo/zext-loop-bound-unbounded.ll
M utils/bazel/MODULE.bazel.lock
M utils/bazel/linux_uapi.bzl
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
M utils/bazel/llvm-project-overlay/lldb/BUILD.bazel
M utils/docs/llvm_sphinx/ext/absolute_links.py
M utils/docs/llvm_sphinx/ext/absolute_links_test/markdown.md
Log Message:
-----------
Merge branch 'main' into users/chinmaydd/lld-elf-vfs
Compare: https://github.com/llvm/llvm-project/compare/2f8fdbee36e1...1b5693cb6b91
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