[all-commits] [llvm/llvm-project] 68fddb: [DAG] Scalarise trivial splat operations (#226257)

[David Green via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 68fddbbe019b63698e9c4a898b313b9112019cab
      https://github.com/llvm/llvm-project/commit/68fddbbe019b63698e9c4a898b313b9112019cab
  Author: David Green <david.green at arm.com>
  Date:   2026-09-27 (Sun, 27 Sep 2026)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
    M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
    M llvm/test/CodeGen/AArch64/lowmaskedlanes.ll

  Log Message:
  -----------
  [DAG] Scalarise trivial splat operations (#226257)

This fixes an issue reported on #224255, where a single active lane
masked store is converted to a v1f16 extract_subvector, which becomes a
v1f16 splat, which fails to scalarize. Add the necessary trivial
scalarisation of the splat by using the f16 input operand.

(I was originally going to fix this by generating a scalar f16 extract
directly (which would have the benefit of treating f16 as legal), but
that seems to cause a regression in 2 x86 tests).



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