[all-commits] [llvm/llvm-project] 7ff128: [CodeGen] Keep wave-profiled spill frequencies pos...

[Yaxun (Sam) Liu via All-commits]

  Branch: refs/heads/users/yxsamliu/pgo-wave-profiled-spill
  Home:   https://github.com/llvm/llvm-project
  Commit: 7ff1282de0ce18f050cae2e008b52aa503c71617
      https://github.com/llvm/llvm-project/commit/7ff1282de0ce18f050cae2e008b52aa503c71617
  Author: Yaxun (Sam) Liu <yaxun.liu at amd.com>
  Date:   2026-09-26 (Sat, 26 Sep 2026)

  Changed paths:
    M llvm/lib/CodeGen/SpillPlacement.cpp
    A llvm/test/CodeGen/AMDGPU/wave-profile-spill-zero-cost.mir

  Log Message:
  -----------
  [CodeGen] Keep wave-profiled spill frequencies positive

SpillPlacement expects positive block weights, but a valid wave profile can
record zero executions for a CFG-reachable block. Giving such a block zero
spill cost can make the allocator choose a very different placement.

Clamp every accepted wave-derived frequency to at least one, as we already
do for nonzero counts that round down to zero. Unmeasured or rejected blocks
still use their existing MBFI frequency. Add a focused MIR test for a valid
zero-wave record.

This pattern arose in a profiled Composable Kernel convolution case. With
the separate spill correctness fixes and partial spilling enabled, the
zero-cost policy failed two CPU-reference checks; the positive floor passed
both. The test checks the cost directly; the application result was checked
separately on gfx950.



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