[all-commits] [llvm/llvm-project] 9214c0: clang: Emit llvm.loop.align metadata for -falign-l...
Alexey Bataev via All-commits
all-commits at lists.llvm.org
Sat Sep 26 05:30:50 PDT 2026
Branch: refs/heads/users/alexey-bataev/spr/slpfix-fmulfadd-fusion-costs-and-retry-fma-seeds-after-all-blocks
Home: https://github.com/llvm/llvm-project
Commit: 9214c04da2ea302b773797f50ad11636c7bab097
https://github.com/llvm/llvm-project/commit/9214c04da2ea302b773797f50ad11636c7bab097
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M clang/lib/CodeGen/CGLoopInfo.cpp
M clang/test/CodeGen/align-loops.c
Log Message:
-----------
clang: Emit llvm.loop.align metadata for -falign-loops (#223147)
Commit: 9dcb4291cea195b9f0941d39540a4f2ccb9ff6bd
https://github.com/llvm/llvm-project/commit/9dcb4291cea195b9f0941d39540a4f2ccb9ff6bd
Author: Charles Zablit <c_zablit at apple.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M lldb/test/API/python_api/value/TestValueAPI.py
Log Message:
-----------
[lldb][test] Skip the sp/rsp check in register sets that have no rsp (#226176)
The test asserts the ABI name `"sp"` resolves to `"rsp"` within the same
register set. However, on Windows the architectural 16-bit `"sp"` lives
in `"supplementary registers"` while `"rsp"` is in `"General Purpose
Registers"`, so there is nothing to compare against.
https://learn.microsoft.com/en-us/windows-hardware/drivers/debugger/x64-architecture
This fixes `python_api/value/TestValueAPI.py` (`test_register`) on
Windows in swiftlang.
Commit: 51ccdfeadcfe29b1d46f978e8582ada109aebb91
https://github.com/llvm/llvm-project/commit/51ccdfeadcfe29b1d46f978e8582ada109aebb91
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M libcxx/test/benchmarks/containers/string.bench.cpp
Log Message:
-----------
[libc++] Add benchmark for string::pop_back() (#223729)
Commit: 68d354f5795682ea1fe03304ac3e7b2a43a36b0d
https://github.com/llvm/llvm-project/commit/68d354f5795682ea1fe03304ac3e7b2a43a36b0d
Author: Jason Van Beusekom <jason.van-beusekom at hpe.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M offload/include/Shared/SourceInfo.h
M openmp/docs/ReleaseNotes.md
Log Message:
-----------
Revert "[Offload][OpenMP] remove SourceInfo::removePath (#226283)" (#226557)
This reverts commit 5b8e65685b4fe99191a217bfa0527c51cf36925c.
In https://github.com/llvm/llvm-project/pull/226283 I forgot to update
info.c to account for the full file paths in its output, will update
commit with fixed test and re open PR
Commit: d92a0c1e5eba51dbf9a4c2a61a709b6758f2e40d
https://github.com/llvm/llvm-project/commit/d92a0c1e5eba51dbf9a4c2a61a709b6758f2e40d
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M mlir/include/mlir/IR/BuiltinDialect.td
M mlir/include/mlir/IR/BuiltinOps.td
M mlir/test/IR/module-op.mlir
M mlir/test/Transforms/sccp-callgraph.mlir
M mlir/test/Transforms/test-symbol-dce.mlir
M mlir/test/python/dialects/ml_program.py
Log Message:
-----------
[MLIR] Enable strict assembly properties for the builtin dialect (#225750)
Commit: 48884d2ddba0718960f68eb01a5b8c42c089f27c
https://github.com/llvm/llvm-project/commit/48884d2ddba0718960f68eb01a5b8c42c089f27c
Author: Cyndy Ishida <cyndy_ishida at apple.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M clang/lib/Lex/HeaderSearch.cpp
A clang/test/ClangScanDeps/modules-context-hash-case-sensitive-vfs-paths.c
M clang/test/ClangScanDeps/modules-context-hash-module-map-path.c
A clang/test/Modules/implicit-module-map-path-case-sensitive.c
Log Message:
-----------
[clang][Modules] Respect case sensitivity when hashing implicit module map path (#226339)
Before this patch, the implicit module hash normalized the module map
path, but explicit modules always respected the case in paths. This
worked by depending on FileEntry caching and/or relocation checking to
resolve correctly. This behavior was both subtle and difficult to
understand. Instead, respect the casing in paths for hashing to match
explicitly built modules so they can never diverge.
This patch also updates `modules-context-hash-module-map-path.c` to
match a downstream version that already tested for the case where vfs
overlay entries differ by case but point to the same file.
`modules-context-hash-case-sensitive-vfs-paths.c` is the same but points
to different underlying files.
Commit: 36e7743d8ec9e743ae66485ddf2a6b27549c8833
https://github.com/llvm/llvm-project/commit/36e7743d8ec9e743ae66485ddf2a6b27549c8833
Author: Anshil Gandhi <95053726+gandhi56 at users.noreply.github.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/Passes/LoadStoreVec.h
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/VecUtils.h
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/Passes/LoadStoreVec.cpp
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/VecUtils.cpp
Log Message:
-----------
[SandboxVec][LoadStoreVec][NFC] Tighten bundle element types (#226348)
Use Instruction*/Constant* for LoadStoreVec APIs where that is what
callers hold, and template getCombinedVectorTypeFor so BndlRef is not
forced through a non-covariant Value* conversion.
Co-authored-by: Cursor <cursoragent at cursor.com>
Commit: 72674697a28c25467649c4993eb033dc4af65951
https://github.com/llvm/llvm-project/commit/72674697a28c25467649c4993eb033dc4af65951
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/test/Transforms/LoopVectorize/VPlan/execution-frequencies-match-bfi.ll
M llvm/test/Transforms/LoopVectorize/X86/predicated-instruction-cost.ll
M llvm/test/Transforms/LoopVectorize/replicate-region-branch-weights.ll
Log Message:
-----------
[LV] Add tests for zero branch weights and execution frequencies (NFC). (#226553)
Add missing test coverage for VPlan-based execution frequency
computation:
* blocks entered via an edge with zero branch weight,
* blocks whose sibling edge has zero weight,
* nested branches whose skipping edges have zero weight,
* a block executing on all paths through the loop after a switch whose
probabilities do not add up to 1,
* frequencies below the smallest representable non-zero one
* all-zero weights making a join's frequency unknown
* estimated frequencies propagating through a branch with weights.
Also updates
llvm/test/Transforms/LoopVectorize/VPlan/execution-frequencies-match-bfi.ll
to check frequencies directly after the frequencies have been recorded.
Commit: a9809116ca6130906f20c727464ba8e878b59aa5
https://github.com/llvm/llvm-project/commit/a9809116ca6130906f20c727464ba8e878b59aa5
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M .github/workflows/libcxx-benchmark-commit.yml
M .github/workflows/libcxx-benchmark-cron.yml
M .github/workflows/libcxx-pr-benchmark.yml
M libcxx/utils/ci/lnt/README.md
M libcxx/utils/ci/lnt/machines.json
M libcxx/utils/ci/lnt/run-benchmarks
M libcxx/utils/ci/run-buildbot
Log Message:
-----------
[libc++] Add a benchmark machine for libstdc++ (#226346)
Add a machine that benchmarks the libstdc++ shipped with GCC 16 on macOS
instead of a libc++ build. To enable that, generalize the scripts and
workflows to make more aspects of machines.json optional (e.g. support
machines that don't need to build libc++).
Commit: 8dc7b3d92cc6371d942dc7619a81faa1f56de938
https://github.com/llvm/llvm-project/commit/8dc7b3d92cc6371d942dc7619a81faa1f56de938
Author: Joshua Batista <jbatista at microsoft.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M clang/include/clang/Basic/Builtins.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Basic/HLSLIntrinsics.td
M clang/lib/CodeGen/CGHLSLBuiltins.cpp
M clang/lib/CodeGen/CGHLSLRuntime.h
M clang/lib/Sema/SemaHLSL.cpp
A clang/test/CodeGenHLSL/builtins/WaveReadLaneFirst.hlsl
A clang/test/SemaHLSL/BuiltIns/WaveReadLaneFirst-errors.hlsl
M clang/test/SemaHLSL/WaveBuiltinAvailability.hlsl
M llvm/include/llvm/IR/IntrinsicsDirectX.td
M llvm/include/llvm/IR/IntrinsicsSPIRV.td
M llvm/lib/Target/DirectX/DXIL.td
M llvm/lib/Target/DirectX/DXILShaderFlags.cpp
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
A llvm/test/CodeGen/DirectX/LongVector/wave-readlane-first.ll
M llvm/test/CodeGen/DirectX/ShaderFlags/wave-ops.ll
A llvm/test/CodeGen/DirectX/WaveReadLaneFirst.ll
A llvm/test/CodeGen/DirectX/WaveReadLaneFirst_mat.ll
A llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_long_vector/wave-readlane-first.ll
A llvm/test/CodeGen/SPIRV/hlsl-intrinsics/WaveReadLaneFirst.ll
A llvm/test/CodeGen/SPIRV/hlsl-intrinsics/WaveReadLaneFirst_mat.ll
Log Message:
-----------
Add WaveReadLaneFirst HLSL function (#220373)
This PR adds the `WaveReadLaneFirst` HLSL function.
Fixes https://github.com/llvm/llvm-project/issues/99164
Assisted by: Github Copilot
Commit: 7b42d2f9991c3680627878a49b1b323cb56176a0
https://github.com/llvm/llvm-project/commit/7b42d2f9991c3680627878a49b1b323cb56176a0
Author: Nico Weber <thakis at chromium.org>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/Target/AMDGPU/BUILD.gn
Log Message:
-----------
[gn build] Port 07aec21c88f4 (#226571)
Commit: cc527d5399997024a68be6241e3a70a6f05a338e
https://github.com/llvm/llvm-project/commit/cc527d5399997024a68be6241e3a70a6f05a338e
Author: Nico Weber <thakis at chromium.org>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/utils/gn/secondary/lld/unittests/AsLibELF/BUILD.gn
Log Message:
-----------
[gn] port b3ed324d42c04 (#226570)
Commit: bbd2e0f7ce13d2a1ff8336018d3b034eb3c698a0
https://github.com/llvm/llvm-project/commit/bbd2e0f7ce13d2a1ff8336018d3b034eb3c698a0
Author: Jiaxun Yang <jiaxun.yang at flygoat.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/Target/Mips/MipsISelLowering.cpp
M llvm/test/CodeGen/Mips/extins.ll
Log Message:
-----------
[Mips] Enable generic bitfield extract preparation (#226491)
Enable CodeGenPrepare's shift sinking when the subtarget supports
bitfield extract instructions. This exposes shift-and-mask patterns
across basic blocks to the existing MIPS extract combine.
Use hasExtractInsert() to keep this disabled for pre-r2 targets and
MIPS16. Add a minimal cross-block regression case to extins.ll.
Commit: 5bc083e278a59853fcfcf3649ba7a20457ead1e5
https://github.com/llvm/llvm-project/commit/5bc083e278a59853fcfcf3649ba7a20457ead1e5
Author: Nico Weber <thakis at chromium.org>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/utils/gn/secondary/lld/unittests/AsLibELF/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/DebugInfo/LogicalView/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/DebugInfo/PDB/BUILD.gn
Log Message:
-----------
[gn] port b3ed324d42c04 more (#226574)
Commit: 0a21a0712b800a3cc1af87e1d0ceb1a84f2b24bd
https://github.com/llvm/llvm-project/commit/0a21a0712b800a3cc1af87e1d0ceb1a84f2b24bd
Author: Patrick Rachford <pat at modular.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/MC/WasmObjectWriter.cpp
M llvm/test/MC/WebAssembly/reloc-pic64.s
Log Message:
-----------
[WebAssembly] Emit i64 GOT import globals on wasm64 (#226326)
WasmObjectWriter hardcodes the synthetic GOT import globals
(GOT.mem/GOT.func) to i32, but on wasm64 they hold 64-bit addresses, so
the object is type-invalid against the i64 global.get that consumes
them. wasm-ld already emits i64 GOT imports on wasm64, so this aligns
the object writer with the linker: the import type is gated on
is64Bit(), and the reloc-pic64 expectations are updated. The wasm32
checks are unchanged.
Commit: 229e7000493f118d49d23073d3bfa613b3798d85
https://github.com/llvm/llvm-project/commit/229e7000493f118d49d23073d3bfa613b3798d85
Author: Marcos Ramirez Joos <mramirezjoos.oss at proton.me>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M libc/src/__support/FPUtil/FEnvImpl.h
Log Message:
-----------
[libc] Avoid system fenv.h in FEnvImpl.h when LIBC_MATH_HAS_NO_EXCEPT is set (#224384)
The warning being added under #199009 triggers errors in subprojects
(e.g., flang) using libc headers that gate the use of `#pragma STDC
FENV_ACCESS ON` on the internal libc
`LIBC_COMPILER_HAS_STDC_FENV_ACCESS` flag, when building under
`-Wfenv-access -Werror`. As the idea is for these subprojects to not
access the libc FP environment (see
https://github.com/llvm/llvm-project/pull/199009#issuecomment-5299119396),
gating the use of system fenv.h functions on the
`LIBC_MATH_HAS_NO_EXCEPT` flag avoids having to specify the
`LIBC_COMPILER_HAS_STDC_FENV_ACCESS` flag when building them.
The three line removals are a clean-up related to
https://github.com/llvm/llvm-project/pull/200268. These uses are
redundant as the called functions already use the pragma when
appropriate.
Commit: 7ca0ce59bb82557a3052666562cc8f0d6d03ec41
https://github.com/llvm/llvm-project/commit/7ca0ce59bb82557a3052666562cc8f0d6d03ec41
Author: Finn Plummer <mail at inbelic.dev>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/Target/DirectX/DXILOpBuilder.cpp
M llvm/test/CodeGen/DirectX/LoadInput.ll
M llvm/test/CodeGen/DirectX/StoreOutput.ll
Log Message:
-----------
[DirectX] Preserve all shader-stage bits during DXIL op lowering (#225874)
The vertex-stage bit is above bit 15 and was lost when the mask was
narrowed to uint16_t. This would cause an incorrect lowering error:
https://godbolt.org/z/rEMj8ssK9.
Corrected by keeping it as a 32 bit value.
Assisted by: ChatGPT 6 Astra
Commit: 44c84768990686eb1e24b4d1dcbd13fff37442bb
https://github.com/llvm/llvm-project/commit/44c84768990686eb1e24b4d1dcbd13fff37442bb
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVExpandPseudoPostRA.cpp
M llvm/lib/Target/RISCV/RISCVExpandPseudoPreEmit.cpp
M llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
M llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
M llvm/lib/Target/RISCV/RISCVLoadStoreOptimizer.cpp
M llvm/lib/Target/RISCV/RISCVZilsdOptimizer.cpp
Log Message:
-----------
[RISCV] Replace uses of RegState::Define. NFC (#226569)
Either pass the destination register to the BuildMI call or use addDef
if there are multiple defs or other flags are set.
Commit: 19d72fd6deab2ea3addd8b945807abd02b1bbb70
https://github.com/llvm/llvm-project/commit/19d72fd6deab2ea3addd8b945807abd02b1bbb70
Author: Kerry McLaughlin <kerry.mclaughlin at arm.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M clang/lib/CodeGen/TargetBuiltins/ARM.cpp
M clang/lib/Sema/SemaARM.cpp
M llvm/include/llvm/Support/AArch64MemoryHints.h
M llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
Log Message:
-----------
[AArch64] Rename memory hints to avoid clash with arm_acle.h macros (#226432)
Renames the hints in AArch64MemoryHints.h, as HINT_STSHH_KEEP and
HINT_STSHH_STRM are already defined in arm_acle.h.
Commit: e76dd51398a8ceac33e9e5bf3253dd6b03b965dd
https://github.com/llvm/llvm-project/commit/e76dd51398a8ceac33e9e5bf3253dd6b03b965dd
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
A llvm/test/Transforms/SLPVectorizer/RISCV/trimmed-node-matching-gather.ll
Log Message:
-----------
[SLP][NFC]ADd a test with the missed vectorization, NFC
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/226581
Commit: d506ee743cdaef27448964890f813bd3b7da7953
https://github.com/llvm/llvm-project/commit/d506ee743cdaef27448964890f813bd3b7da7953
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/RISCV/trimmed-node-matching-gather.ll
Log Message:
-----------
[SLP]Reuse the trimmed nodes in the perfectly matched gathers of the same user
The gather node, perfectly matching the node of the same user
transformed to gather during throttling, did not treat this node as a
reuse source, and was costed and emitted as a separate buildvector.
Fixes #219030
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/226582
Commit: f57595ff59a0f012e0481c69613be907942c30b1
https://github.com/llvm/llvm-project/commit/f57595ff59a0f012e0481c69613be907942c30b1
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanVerifier.cpp
M llvm/unittests/Transforms/Vectorize/VPlanVerifierTest.cpp
Log Message:
-----------
[VPlan] Only exempt MaskedCond from cross-block dominance in verifier. (#226512)
Previously the verifier skipped all use-before-def checks for
MaskedCond, including uses in the same block before the definition.
Restrict the exemption to users in blocks not dominated by the
MaskedCond's block, so same-block use-before-def is still diagnosed.
Commit: 08af99fae9e079b448cd8877fc57376efe680cda
https://github.com/llvm/llvm-project/commit/08af99fae9e079b448cd8877fc57376efe680cda
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/include/llvm/CodeGen/SDPatternMatch.h
Log Message:
-----------
[SDPatternMatch] Implement m_True/False using SelectionDAG::isBoolConstant. (#226216)
Better than duplicating existing functionality.
Commit: e4af48bd3b330282f36f075d6fa7a4a0742376c1
https://github.com/llvm/llvm-project/commit/e4af48bd3b330282f36f075d6fa7a4a0742376c1
Author: Ehsan Amiri <ehsan.amiri at huawei.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Scalar/LoopFuse.cpp
A llvm/test/Transforms/LoopFusion/guard_skip_empty_block.ll
Log Message:
-----------
[LoopFusion] Cleanup control flow before Fusion (#226289)
Non-loop successor of loop guard is sometimes modified by JumpThreading
(and potentially some other passes) to jump to a new block, that doesn't
post dominate the exit block of the loop:
Guard: br %c, %Preheader, %Skip
Skip: br %Merge
...
Exit: br %Merge
Merge: ...
Later on, this block becomes empty, so it can be removed. Its presence
prevents Loop::getLoopGuardBranch() from detecting the loop guard which
results in missed fusion opportunities. SimplifyCFG will run when "Skip"
is still not optimzied, so it cannot resolve this issue.
Assisted by Claude Code
Commit: ee3b6b045bc37b156c3860481090d68367e961dc
https://github.com/llvm/llvm-project/commit/ee3b6b045bc37b156c3860481090d68367e961dc
Author: agozillon <Andrew.Gozillon at amd.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M flang/lib/Lower/OpenMP/ClauseProcessor.cpp
M flang/lib/Lower/OpenMP/Utils.cpp
M flang/lib/Lower/OpenMP/Utils.h
M flang/test/Lower/OpenMP/declare-mapper.f90
A flang/test/Lower/OpenMP/target-map-nested-dtype-allocatable-member.f90
Log Message:
-----------
[Flang][OpenMP] Fix broken offload test caused by MapInfoFinalization code movement (#226384)
This change addresses the breakage in
target-map-nested-dtype-allocatable-member.f90 I inadvertently broke it
by removing the excess bit of implicit mapping code in the
MapInfoFinalizaiton pass without correctly addressing it.
This PR tries to do so by allowing mappers to be generated for member
maps such as var1%b, var2%b, which were previously being blocked.
Currently (and conveniently for this patch) we do avoid duplicate maps
in the scenario where we specify something along the lines of:
map(tofrom: var1, var1%b, var2, var2%b)
But that is through the fact that we completely negate var1/var2's
mapper attachment in this scenario, which I do not believe is the
correct behavior. But it's the existing behavior and facilitates this
patch, but it is something I'll see if I can address in a follow up PR
in the near future, the logic might need a bit of debating. For now this
simply seeks to amend the existing test without rocking the boat more
than required (that's the hope at least).
Commit: ae614a9564425ab206940f2b91607b1d77826068
https://github.com/llvm/llvm-project/commit/ae614a9564425ab206940f2b91607b1d77826068
Author: Aaron <58265908+aaronsms at users.noreply.github.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M clang/lib/Format/ContinuationIndenter.cpp
M clang/unittests/Format/FormatTest.cpp
Log Message:
-----------
[clang-format] Preserve enum initializer continuation indentation (#223435)
Fixes #223011
Enum assignment operators are annotated as TT_EnumEqual so they can be
aligned independently in #194154. However, this means
ContinuationIndenter no longer recognizes a wrapped enum `=` as
TT_BinaryOperator. As a result, it may force unnecessary breaks within
the RHS binary expression.
Co-authored-by: Aaron Saw Min Sern <aaron at aaronsms.com>
Commit: 4db3dceb8d7bffa4b69042fe043652d616396237
https://github.com/llvm/llvm-project/commit/4db3dceb8d7bffa4b69042fe043652d616396237
Author: Jeremy Kun <jkun at google.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/Support/StringRef.cpp
M llvm/unittests/ADT/StringRefTest.cpp
Log Message:
-----------
[llvm] produce a more consistent estimates of bit width needed when parsing an integer (#205947)
A colleague of mine noticed that `"12535824225335233"` parses in MLIR's
integer attribute parser as a 68-bit integer, even though it is a 53-bit
constant. I traced this back to `StringRef::consumeInteger`'s heuristic
estimate of the bit size. This change replaces that heuristic with a
default 64-bit storage, doubling the storage as more digits are parsed.
This produces a potentially larger over-estimate of the total storage
required, but does so in a less arbitrary manner and reduces the
over-approximation for numbers close to the 64-bit boundary.
Nb., A first iteration of this change tightened that estimate to at most
a 1-bit overapproximation with a lookup-table.
Assisted by Gemini
Commit: 1b4e7f41268eb3db5300e79256764140e509e3f5
https://github.com/llvm/llvm-project/commit/1b4e7f41268eb3db5300e79256764140e509e3f5
Author: Akash Manna <akash.manna.mymail at gmail.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M clang/docs/ReleaseNotes.md
M clang/lib/Sema/SemaType.cpp
M clang/test/Sema/large-bit-int.c
M clang/test/Sema/types.c
M clang/test/SemaCXX/vector.cpp
Log Message:
-----------
[Clang] Enforce the same size limits for `vector_size` and `ext_vector_type` (#226375)
Fixes #165458
A `bool` vector declared with `ext_vector_type` isn't lowered as an LLVM
vector in memory: `ConvertTypeForMem` packs it into a single integer
with one bit per element. `BuildExtVectorType` only checked that the
element count fits in 32 bits, though, so a vector of 187,553,262 bools
got through Sema and the first consumer that needed its memory type (the
zero initializer of a tentative definition here) asked
`IntegerType::get` for far more than the 2^23 bits it supports. The
count matters for every element type, not just `bool`, because Sema also
forms bool vectors out of other vectors (`c ? true : false` with a
`char` vector condition), and `vector_size` was no better off with its
limits of 2^32 elements and 2^61 bytes.
Both attributes now go through the same two limits when the type is
built, reusing the existing "vector size too large" error: at most
`llvm::IntegerType::MAX_INT_BITS` (2^23) elements, and at most 2^28
bytes so that the natural alignment, the size rounded up to a power of
two, still fits in the `unsigned` alignment of `TypeInfo`. These replace
the old `isIntN(61)` and `UINT32_MAX` checks in `BuildVectorType`.
Commit: 210ecf77c9021941ee32c496df8b715615163df4
https://github.com/llvm/llvm-project/commit/210ecf77c9021941ee32c496df8b715615163df4
Author: Eli Friedman <efriedma at qti.qualcomm.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/Transforms/IPO/Instrumentor.cpp
Log Message:
-----------
[Instrumentor] Use CreateAllocationSize to compute size of alloca (#226330)
No significant functional change, but the IR might look slightly
different.
Commit: 14e819f14307fd85fe830cf9fe8d168a27b3db89
https://github.com/llvm/llvm-project/commit/14e819f14307fd85fe830cf9fe8d168a27b3db89
Author: Eli Friedman <efriedma at qti.qualcomm.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/include/llvm/Transforms/IPO/InstrumentorUtils.h
Log Message:
-----------
[Instrumentor] Delete dead code from getAlloca() (#226331)
Commit: 8af5ec67c2001eb379d53cc61ccce0ca521a6c3c
https://github.com/llvm/llvm-project/commit/8af5ec67c2001eb379d53cc61ccce0ca521a6c3c
Author: Abhay Kanhere <a_kanhere at apple.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/include/llvm/IR/AutoUpgrade.h
M llvm/lib/Bitcode/Reader/MetadataLoader.cpp
M llvm/lib/IR/AutoUpgrade.cpp
A llvm/test/Bitcode/upgrade-tbaa-struct.ll
A llvm/test/Bitcode/upgrade-tbaa-struct.ll.bc
Log Message:
-----------
[AutoUpgrade] Upgrade old-style !tbaa.struct field tags (#225967)
Extend the TBAA auto-upgrade to rewrite old-style scalar field tags
inside !tbaa.struct
to the struct-path aware format. bitcode (MetadataLoader) upgraded to
match the existing top-level !tbaa upgrade.
Commit: 35df00b0aa5d9f4deec215306dc24d247f5eb66c
https://github.com/llvm/llvm-project/commit/35df00b0aa5d9f4deec215306dc24d247f5eb66c
Author: Abhay Kanhere <a_kanhere at apple.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/Analysis/TypeBasedAliasAnalysis.cpp
M llvm/test/Transforms/InstCombine/struct-assign-tbaa.ll
Log Message:
-----------
[TBAA] Recover !tbaa for a memcpy of struct with same type fields (#214116)
When InstCombine widens a small same-typed aggregate copy into an
integer load/store, it derives no !tbaa, and !tbaa.struct is nulled out,
so the load/store are left untyped. An untyped access may-alias every
typed access and blocks optimization:
struct Coord { int x, y; };
void copy_if_inbounds(Coord *dst, const Coord *src, const long *bound,
int n) {
for (int i = 0; i < n; ++i)
if (i < *bound)
dst[i] = *src; // {int,int} copy -> memcpy + !tbaa.struct
}
compare this to field-by-field copy, which has typed field access
void copy_fields_if_inbounds(Coord *dst, const Coord *src, const long
*bound, int n) {
for (int i = 0; i < n; ++i)
if (i < *bound) { dst[i].x = src->x; dst[i].y = src->y; } // per-field,
typed
}
Commit: 1173687801b5ab1e996f1aef21b760318e5da8c9
https://github.com/llvm/llvm-project/commit/1173687801b5ab1e996f1aef21b760318e5da8c9
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlan.cpp
M llvm/lib/Transforms/Vectorize/VPlanHelpers.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
Log Message:
-----------
[VPlan] Use NeedsSingleScalar consistently for ::get (NFC). (#226494)
IsScalar/IsSingleScalar as used currently may be consfusing, as it could
be read as implying that the VPValue is a single-scalar, see
https://github.com/llvm/llvm-project/pull/226153.
But here it means that the caller only needs a single scalar. Update
wording.
PR: https://github.com/llvm/llvm-project/pull/226494
Commit: b4842bea58e6ca2a3de8692d5214b2441285513d
https://github.com/llvm/llvm-project/commit/b4842bea58e6ca2a3de8692d5214b2441285513d
Author: Alex MacLean <amaclean at nvidia.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-undef.mir
M llvm/test/CodeGen/AMDGPU/call-constant.ll
M llvm/test/CodeGen/AMDGPU/invalid-addrspacecast.ll
M llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-pal.ll
Log Message:
-----------
[GlobalISel] Preserve volatile and ordered atomic stores of undef (#226265)
Guard `erase_undef_store` with `isUnordered()`, matching InstCombine.
Ensures volatile and ordered atomic stores are preserved.
---------
Co-authored-by: Hongyu Chen <hongchen at nvidia.com>
Commit: f9f5ed22a7026261aec0075caa9862953a8a5fe6
https://github.com/llvm/llvm-project/commit/f9f5ed22a7026261aec0075caa9862953a8a5fe6
Author: Joseph Huber <huberjn at outlook.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/runtimes/CMakeLists.txt
Log Message:
-----------
[LLVM] Use complete runtime dependency list for multilibs (#226580)
Summary:
The current handling makes the multilib job depend on the base runtimes
job. This means that we will potentially depend on things that don't
necessarily need to be built to fulfil the multilibs job. Instead, just
depend on the individual targets for that multilib.
Commit: 91d0e2e91e2dc4c4729cbe911f67388453ee509d
https://github.com/llvm/llvm-project/commit/91d0e2e91e2dc4c4729cbe911f67388453ee509d
Author: Jason Van Beusekom <jason.van-beusekom at hpe.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M offload/include/Shared/SourceInfo.h
M offload/test/offloading/info.c
M openmp/docs/ReleaseNotes.md
Log Message:
-----------
[Offload][OpenMP] remove SourceInfo::removePath (#226586)
This Pr is the same as https://github.com/llvm/llvm-project/pull/226283
(which was reverted in https://github.com/llvm/llvm-project/pull/226557)
This Pr is the same as https://github.com/llvm/llvm-project/pull/226283
but with an update to info.c to account for the new full path output.
Commit: 5f3a611fa194ca76c91d3889adb68532cef44cee
https://github.com/llvm/llvm-project/commit/5f3a611fa194ca76c91d3889adb68532cef44cee
Author: Jackson Stogel <jtstogel at gmail.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M utils/bazel/MODULE.bazel.lock
M utils/bazel/linux_uapi.bzl
Log Message:
-----------
[bazel] Download linux UAPI headers when no local dir is set (#216868)
This PR defines a hermetic source for `@linux_api//:linux_uapi_headers`
that will be used in CI. If no `LINUX_UAPI_INCLUDE_DIR` value is
specified, then Bazel will download the linux-libc-dev debian package
and use its headers.
I originally wanted to pull from https://github.com/torvalds/linux and
build UAPI headers from source as it gives more control, but the repo is
rather large and took ~20s to download and ~10s to build. Using the
debian package's headers is closer to what the LLVM-libc fullbuild CI
[currently
does](https://github.com/llvm/llvm-project/blob/007551bacb899a409218574908d96b0633d52018/.github/workflows/containers/libc/Dockerfile#L38)
and is very fast.
Commit: c4195f63a560990bdb854357d66f759259bf1d3e
https://github.com/llvm/llvm-project/commit/c4195f63a560990bdb854357d66f759259bf1d3e
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M mlir/docs/Interfaces.md
M mlir/include/mlir/Dialect/OpenMP/OpenMPOpsInterfaces.td
M mlir/test/mlir-tblgen/op-interface.td
M mlir/tools/mlir-tblgen/OpInterfacesGen.cpp
Log Message:
-----------
[mlir][ODS] Share operation interface methods with raw-op bodies (NFC) (#226317)
Allow an operation interface method to use a shared callback when its
body only needs the raw Operation. Use it for OpenMP block-argument
indexing and slicing methods, avoiding per-operation wrappers while
preserving the existing fallback and external model paths.
Reduces the size of the OpenMP dialect text section by 1.68%.
Assisted-by: Codex
Commit: 7fbfd203131aa597c63d89e45392454280f89cfa
https://github.com/llvm/llvm-project/commit/7fbfd203131aa597c63d89e45392454280f89cfa
Author: Med Ismail Bennani <ismail at bennani.ma>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M lldb/include/lldb/Utility/StructuredData.h
M lldb/source/Commands/CommandObjectVersion.cpp
M lldb/source/Utility/StructuredData.cpp
Log Message:
-----------
[lldb] Add StructuredData::Dictionary::ForEachSorted (NFC) (#226597)
`Dictionary::Serialize`, `Dictionary::GetDescription` and the build
configuration dump in `CommandObjectVersion` each collect the
dictionary's keys and sort them before iterating, so that the output
doesn't depend on StringMap's ordering. Factor that into a new
`ForEachSorted` method.
Signed-off-by: Med Ismail Bennani <ismail at bennani.ma>
Commit: 5cab2963e13496c272a482145b11796e9e26eeb4
https://github.com/llvm/llvm-project/commit/5cab2963e13496c272a482145b11796e9e26eeb4
Author: Demetrios Chiuratto Agourakis <demetrios at agourakis.med.br>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
M llvm/test/CodeGen/X86/llvm.frexp.ll
Log Message:
-----------
[SelectionDAG] Fix result index and vector width in unrollExpandedOp (#225886)
Fixes #224127.
In `DAGTypeLegalizer::WidenVectorResult`, `unrollExpandedOp` computes
the unroll count and widened vector type from the result being legalized
(`ResNo`) rather than unconditionally using result 0. For multi-result
nodes where result types differ (e.g. `ISD::FFREXP`), this prevents
mismatched vector widths and preserves the correct result index from
`DAG.UnrollVectorOp`.
Assisted-by: Claude
---------
Co-authored-by: Demetrios Chiuratto Agourakis <agourakis82 at gmail.com>
Commit: 5aa8fcc29bc47056411b3d23b0e7acc981ec3934
https://github.com/llvm/llvm-project/commit/5aa8fcc29bc47056411b3d23b0e7acc981ec3934
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/rvv/trunc-select-to-max-usat.ll
Log Message:
-----------
[RISCV] Support swapped select operands in combineTruncSelectToSMaxUSat. (#226584)
Handle (trunc (vselect (setugt X, 2^N-1), (sext (setgt X, 0)), X)) in
addition to the existing (trunc (vselect (setult X, 2^N), X,
(sext (setgt X, 0)))) form.
Co-Authored-By: Claude Opus 5.5 (1M context) <noreply at anthropic.com>
Commit: 7e91ef5d6aeaa7191a9354ddcff67d84bd8aebaf
https://github.com/llvm/llvm-project/commit/7e91ef5d6aeaa7191a9354ddcff67d84bd8aebaf
Author: Michael G. Kazakov <mike.kazakov at gmail.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M libcxx/include/CMakeLists.txt
M libcxx/include/__algorithm/pstl.h
M libcxx/include/__pstl/backend_fwd.h
M libcxx/include/__pstl/backends/default.h
M libcxx/include/__pstl/backends/libdispatch.h
M libcxx/include/__pstl/backends/serial.h
M libcxx/include/__pstl/backends/std_thread.h
A libcxx/include/__pstl/cpu_algos/swap_ranges.h
M libcxx/include/module.modulemap.in
M libcxx/test/libcxx/algorithms/pstl.iterator-requirements.verify.cpp
A libcxx/test/std/algorithms/alg.modifying.operations/alg.swap/pstl.swap_ranges.pass.cpp
M libcxx/test/std/algorithms/pstl.exception_handling.pass.cpp
Log Message:
-----------
[libc++][pstl] Implementation of parallel std::swap_ranges() based on parallel __for_each (#224967)
This PR adds an implementation of parallel `std::swap_ranges()` based on
`__parallel_for_each_iter_pair()`.
The implementation is effectively a one-liner, but has to deal with
iterator ranges, thus is located in `cpu_algos`:
```c++
__pstl::__parallel_for_each_iter_pair<_Backend>(
first1, last1, first2,
[](ForwardIterator1 brick_first1, ForwardIterator1 brick_last1, ForwardIterator2 brick_first2) {
std::swap_ranges(std::move(brick_first1), std::move(brick_last1), std::move(brick_first2));
});
```
Part of #99938
Commit: 7fc4f276a4d0a4b1f968003d863ee50dc9ebcedd
https://github.com/llvm/llvm-project/commit/7fc4f276a4d0a4b1f968003d863ee50dc9ebcedd
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M flang/lib/Parser/openacc-parsers.cpp
M flang/test/Parser/acc-label-do.f90
Log Message:
-----------
[flang][openacc] Build full shared-label DO nests in AccNonBlockDoConstruct (#225997)
When an `!$acc loop` is associated with a labeled DO,
AccNonBlockDoConstruct
turned only that outer loop into a DoConstruct and left sibling
LabelDoStmts
that share the same terminator for later CanonicalizeDo. An inner `!$acc
loop`
then swallowed the shared terminator into its own DoConstruct, so
AnalyzeLabels (which runs before CanonicalizeDo) rejected the remaining
LabelDoStmts with "Label 'N' is not in DO loop scope".
Recurse on nested LabelDoStmts while parsing the associated loop so the
whole shared-label nest is a DoConstruct before label analysis. Add a
parser test where only the outer and innermost loops have LOOP
directives.
Commit: ce8e98386b89cf25065349c0e8147f839afda5dd
https://github.com/llvm/llvm-project/commit/ce8e98386b89cf25065349c0e8147f839afda5dd
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M mlir/include/mlir/Dialect/Linalg/IR/LinalgInterfaces.td
M mlir/include/mlir/Dialect/OpenACC/OpenACCOpsInterfaces.td
M mlir/include/mlir/Dialect/OpenMP/OpenMPOpsInterfaces.td
M mlir/include/mlir/Dialect/SparseTensor/IR/SparseTensorInterfaces.td
M mlir/include/mlir/Dialect/WasmSSA/IR/WasmSSAInterfaces.td
M mlir/include/mlir/Interfaces/ControlFlowInterfaces.td
Log Message:
-----------
[mlir][Interfaces] Share more operation interface bodies (NFC) (#226603)
Use raw operation access for methods that do not depend on the concrete
operation type. Keep typed access where operation-specific APIs are
needed.
This save a little bit of code size and improves build time.
Assisted-by: Codex
Commit: b5426c132f47b14874de7ce26a4e1bca80182e4c
https://github.com/llvm/llvm-project/commit/b5426c132f47b14874de7ce26a4e1bca80182e4c
Author: Lang Hames <lhames at gmail.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M orc-rt/include/orc-rt-c/support/Logging.h
M orc-rt/test/unit/support/LoggingTest.cpp
Log Message:
-----------
[orc-rt] Add ORC_RT_LOG_ENABLED macro. (#226500)
ORC_RT_LOG_ENABLED(Level) reports whether log sites at the given level
are compiled in, taking into account both the backend and the
ORC_RT_LOG_LEVEL floor. It takes the same level token as ORC_RT_LOG and
can be used in preprocessor conditionals, allowing code that relies on
logging to surface something important (e.g. a logging error reporter)
to choose an alternative when logging is compiled out.
Commit: f739fbc831cbd670b9dc3044a492240cfede20c3
https://github.com/llvm/llvm-project/commit/f739fbc831cbd670b9dc3044a492240cfede20c3
Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
A llvm/test/Transforms/LoopVectorize/AArch64/diff-checks-force-interleave-count.ll
Log Message:
-----------
[LV] Honor -force-vector-interleave when generating diff checks (#225768)
We use both IC and UserIC in the checks below. However, once those
checks are done, UserIC will always override IC if it's non-zero. That
means using the max is unnecessary and can result in overly conservative
checks when UserIC < IC.
Commit: 201e76d4559e9d8acdfec1c202df8f2269acbd8b
https://github.com/llvm/llvm-project/commit/201e76d4559e9d8acdfec1c202df8f2269acbd8b
Author: Changpeng Fang <changpeng.fang at amd.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/CodeGen/DetectDeadLanes.cpp
A llvm/test/CodeGen/AMDGPU/detect-dead-lanes-reg-sequence-narrow-slot.mir
M llvm/test/CodeGen/AMDGPU/frem.ll
A llvm/test/CodeGen/AMDGPU/true16-uniform-f16-phi-copysign.ll
Log Message:
-----------
[CodeGen] Fix DetectDeadLanes for same-class copies with mismatched widths (#226556)
isCrossCopy() returned early whenever source and destination shared a
register class, treating the transfer as lane-for-lane. That is wrong
when a REG_SEQUENCE names a subregister slot narrower than the source
operand, e.g. a 32-bit vreg used as the lo16 piece of another 32-bit
vreg. Only take the early exit when the two widths match; otherwise fall
through to findCommonRegClass().
Fixes: ROCM-31212
Commit: 3a2787d5ca6ba0271f7203997f8a9b65679398a4
https://github.com/llvm/llvm-project/commit/3a2787d5ca6ba0271f7203997f8a9b65679398a4
Author: Lang Hames <lhames at gmail.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M orc-rt/include/orc-rt-c/config.h.in
M orc-rt/include/orc-rt-c/support/Logging.h
Log Message:
-----------
[orc-rt] Move ORC_RT_LOG_ENABLED into config.h. (#226617)
ORC_RT_LOG_ENABLED depends only on the logging configuration values
defined in config.h, but was defined in Logging.h, so checking whether a
log level is compiled in required pulling in the logging backend's
headers (e.g. <os/log.h>).
This commit moves ORC_RT_LOG_ENABLED (and its level-token aliases) into
config.h, so that headers can check the logging configuration without
including Logging.h.
Commit: f8c2918d49d3a3803ae3c9e1b6c216b24db9ad51
https://github.com/llvm/llvm-project/commit/f8c2918d49d3a3803ae3c9e1b6c216b24db9ad51
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
A llvm/test/Transforms/SLPVectorizer/AArch64/ordered-reduction-of-loads.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/ordered-reduction.ll
Log Message:
-----------
[SLP][NFC]Add extra test for reductions vectorization, NFC
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/226618
Commit: 90c150f868adb53b45dbf7489e93a23c22f6b6b3
https://github.com/llvm/llvm-project/commit/90c150f868adb53b45dbf7489e93a23c22f6b6b3
Author: Fangrui Song <i at maskray.me>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M clang/tools/clang-format/ClangFormat.cpp
M llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
M llvm/lib/Target/AArch64/AArch64CodeLayoutOpt.cpp
Log Message:
-----------
Replace cl::bits with cl::list. NFC (#226399)
cl::bits packs enum values into an unsigned, which would block migration
to TableGen based representation. The three users only test membership.
LLM-aided
Commit: 0b61b734cf84a19491f4bcb61e04956995807051
https://github.com/llvm/llvm-project/commit/0b61b734cf84a19491f4bcb61e04956995807051
Author: Fangrui Song <i at maskray.me>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M clang-tools-extra/clangd/tool/ClangdMain.cpp
Log Message:
-----------
[clangd] Report retired flags after parsing (#226360)
cl::callback will be removed to enable migration to TableGen
https://discourse.llvm.org/t/rfc-declare-library-command-line-options-in-tablegen-one-struct-per-library/91877/3
LLM-aided
Commit: ab08c75ffe0a40626a4dc62ed010d6e3ceece056
https://github.com/llvm/llvm-project/commit/ab08c75ffe0a40626a4dc62ed010d6e3ceece056
Author: Fangrui Song <i at maskray.me>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M bolt/lib/Passes/BinaryPasses.cpp
M bolt/lib/Passes/ReorderFunctions.cpp
M bolt/lib/Profile/DataAggregator.cpp
Log Message:
-----------
[BOLT] Remove cl::callback uses (#226359)
cl::callback will be removed to enable migration to TableGen based
representation.
https://discourse.llvm.org/t/rfc-declare-library-command-line-options-in-tablegen-one-struct-per-library/91877/3
LLM-aided
Commit: e59a0c697552ae7d1c3aeed5774e829cdc5e16b5
https://github.com/llvm/llvm-project/commit/e59a0c697552ae7d1c3aeed5774e829cdc5e16b5
Author: Lang Hames <lhames at gmail.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M orc-rt/include/orc-rt/bedrock/Session.h
M orc-rt/lib/bedrock/Session.cpp
M orc-rt/test/unit/CommonTestUtils.h
M orc-rt/test/unit/bedrock/InProcessControllerAccessTest.cpp
M orc-rt/test/unit/bedrock/SessionTest.cpp
M orc-rt/tools/ogre/ogre.cpp
Log Message:
-----------
[orc-rt] Pass the reporting Session to Session error reporters. (#226622)
Session error reporters previously received only the Error, and had to
be supplied to the Session constructor, so they had no direct way to
refer to the Session reporting the error (e.g. to include its address in
a log message).
This commit changes ErrorReporterFn to take the reporting Session along
with the Error, and adds a Session::logErrors reporter that logs errors
via ORC_RT_LOG at Error level in the Session category. logErrors is only
available when Error-level logging is compiled in
(ORC_RT_LOG_ENABLED(Error)), so that it can't silently discard errors in
configurations where logging is compiled out. The noErrors and
AccumulateErrors test helpers are updated to work as both plain and
Session error reporters.
Commit: 240a9cb75dd9210cae8e987700d0ef6537b723cb
https://github.com/llvm/llvm-project/commit/240a9cb75dd9210cae8e987700d0ef6537b723cb
Author: Twice <twice at apache.org>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M mlir/python/mlir/dialects/ext.py
M mlir/test/python/dialects/ext.py
Log Message:
-----------
[MLIR][Python] Allow `Attribute` to denote unconstrained attributes in Python-defined ops (#224679)
Operation definitions support attribute constraints such as
`IntegerAttr`, `StringAttr`, and `IntegerAttr | StringAttr`, but
currently reject `Attribute` itself.
This change allows `Attribute` to denote an unconstrained attribute,
accepting both built-in and Python-defined attributes:
```python
class MyOp(MyDialect.Operation, name="my_op"):
arg: Operand
attr: Attribute
res: Result
```
This complements the unconstrained `Operand` and `Result` annotations
introduced in #220216. The annotation also works with `attribute()`
field specifiers, including `kw_only` and `default_factory`.
Assisted-by: Codex / GPT6
Commit: 163950475fc724cd5d62e868bdb46ba0c39e5519
https://github.com/llvm/llvm-project/commit/163950475fc724cd5d62e868bdb46ba0c39e5519
Author: Steffen Larsen <sholstla at amd.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M clang/include/clang/CIR/Dialect/Builder/CIRBaseBuilder.h
M clang/lib/CIR/CodeGen/CIRGenDecl.cpp
M clang/test/CIR/CodeGenCUDA/address-spaces.cu
Log Message:
-----------
[CIR] Attach address space to global variables (#226455)
Signed-off-by: Steffen Holst Larsen <sholstla at amd.com>
Commit: 60059de6eb6d647857ac55b48d465580aa3ecdc5
https://github.com/llvm/llvm-project/commit/60059de6eb6d647857ac55b48d465580aa3ecdc5
Author: A. Jiang <de34 at live.cn>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M libcxx/include/__ranges/adjacent_transform_view.h
M libcxx/include/__ranges/adjacent_view.h
M libcxx/include/__ranges/chunk_by_view.h
M libcxx/include/__ranges/common_view.h
M libcxx/include/__ranges/concat_view.h
M libcxx/include/__ranges/counted.h
M libcxx/include/__ranges/drop_view.h
M libcxx/include/__ranges/drop_while_view.h
M libcxx/include/__ranges/elements_view.h
M libcxx/include/__ranges/empty_view.h
M libcxx/include/__ranges/enumerate_view.h
M libcxx/include/__ranges/filter_view.h
M libcxx/include/__ranges/iota_view.h
M libcxx/include/__ranges/join_view.h
M libcxx/include/__ranges/join_with_view.h
M libcxx/include/__ranges/lazy_split_view.h
M libcxx/include/__ranges/movable_box.h
M libcxx/include/__ranges/non_propagating_cache.h
M libcxx/include/__ranges/rbegin.h
M libcxx/include/__ranges/rend.h
M libcxx/include/__ranges/reverse_view.h
M libcxx/include/__ranges/single_view.h
M libcxx/include/__ranges/split_view.h
M libcxx/include/__ranges/stride_view.h
M libcxx/include/__ranges/take_view.h
M libcxx/include/__ranges/take_while_view.h
M libcxx/include/__ranges/to.h
M libcxx/include/__ranges/transform_view.h
M libcxx/include/__ranges/views.h
M libcxx/include/__ranges/zip_transform_view.h
M libcxx/include/__ranges/zip_view.h
Log Message:
-----------
[libc++][NFC] Avoid empty namespace in internal headers of `<ranges>` (#226034)
...in pre-C++20/23 modes. This follows up
0c94a978df783bd67535350eac84088fc482716a and fixes more complaints from
clang-tidy checks in CI.
Commit: 18af9ef08eec59d1bce7b941f164ba3f866acf59
https://github.com/llvm/llvm-project/commit/18af9ef08eec59d1bce7b941f164ba3f866acf59
Author: Douglas Yung <douglas.yung at sony.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M clang/docs/ReleaseNotes.md
M clang/lib/Sema/SemaOpenMP.cpp
R clang/test/OpenMP/error_message.c
M clang/test/OpenMP/error_message.cpp
M clang/test/OpenMP/parallel_message_messages.cpp
Log Message:
-----------
Revert "[clang][OpenMP] Only accept char strings in the message clause" (#226636)
Reverts llvm/llvm-project#226080
The newly added test error_message.c is failing on the PS4 bot
https://lab.llvm.org/buildbot/#/builders/144/builds/66294
Commit: e0316c1b4762263caa49e3c41ddde752a2b6b775
https://github.com/llvm/llvm-project/commit/e0316c1b4762263caa49e3c41ddde752a2b6b775
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M clang/lib/AST/ByteCode/ByteCodeEmitter.h
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ByteCode/Context.cpp
M clang/lib/AST/ByteCode/Disasm.cpp
M clang/lib/AST/ByteCode/EvalEmitter.cpp
M clang/lib/AST/ByteCode/EvalEmitter.h
M clang/lib/AST/ByteCode/EvaluationResult.cpp
M clang/lib/AST/ByteCode/EvaluationResult.h
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/InterpBuiltinObjectSize.cpp
M clang/lib/AST/ByteCode/Pointer.cpp
M clang/lib/AST/ByteCode/Pointer.h
M clang/lib/AST/ExprConstShared.h
M clang/lib/AST/ExprConstant.cpp
M clang/test/AST/ByteCode/builtin-functions.cpp
M clang/test/AST/ByteCode/codegen-constexpr-unknown.cpp
M clang/test/AST/ByteCode/references.cpp
M clang/test/CodeGenCXX/global-init.cpp
M clang/test/SemaCXX/PR19955.cpp
M clang/test/SemaCXX/cxx2c-expansion-stmts.cpp
Log Message:
-----------
Revert "[clang][bytecode] Stop relying on `CheckEvaluationResult()` (… (#226637)
…#186045)"
This reverts commit 55b498466a7b2620d09fcdf1b2300f71a35f6d8b.
This breaks two msan builders and reproducing the failure locally takes
forever.
Commit: 6a37cee09997b28c6cc708dd36b283bbd5bd7147
https://github.com/llvm/llvm-project/commit/6a37cee09997b28c6cc708dd36b283bbd5bd7147
Author: asudarsa-qti <asudarsa at qti.qualcomm.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M clang/lib/Interpreter/IncrementalAction.cpp
A clang/test/Interpreter/nonexistent-xcc-file.cpp
Log Message:
-----------
Fix for a clang-repl crash when passing non-existent file to --Xcc (#225861)
Problem: When clang-repl fails to initialize because an --Xcc file does
not exist, Interpreter::create() destroys the partially initialized
Interpreter. Its destructor unconditionally calls FinalizeAction(),
which invokes FrontendAction::EndSourceFile() without a registered
CompilerInstance and triggers an assertion.
Fix: Track whether interpreter initialization completed successfully and
only finalize the frontend action for successfully initialized
interpreters.
Test: Add a regression test covering a nonexistent --Xcc file.
This change resolves https://github.com/llvm/llvm-project/issues/225429
Assisted by gpt-5.6-luna
---------
Co-authored-by: Anutosh Bhat <andersonbhat491 at gmail.com>
Commit: c4896792fb97b2ad237c5c404cdda2d0cd4fcf61
https://github.com/llvm/llvm-project/commit/c4896792fb97b2ad237c5c404cdda2d0cd4fcf61
Author: Med Ismail Bennani <ismail at bennani.ma>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M lldb/include/lldb/Target/Process.h
M lldb/source/API/SBProcess.cpp
M lldb/source/Target/Process.cpp
M lldb/test/API/python_api/process/address-masks/TestAddressMasks.py
Log Message:
-----------
[lldb] Rebuild stack frames when a process address mask changes (#224989)
Commit: 4257da8ee2e84b3e62d2a2a5010e81823b799805
https://github.com/llvm/llvm-project/commit/4257da8ee2e84b3e62d2a2a5010e81823b799805
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
A llvm/test/Transforms/LoopVectorize/AArch64/low-trip-count-fixed-vf-no-epilogue.ll
M llvm/test/Transforms/LoopVectorize/RISCV/short-trip-count.ll
Log Message:
-----------
[LV] Always try to use fixed VF for low TC loops if no epilogue allowed. (#226318)
Remove the MaxPowerOf2RuntimeVF gate for falling back to using fixed
width VFs when no epilogue is allowed and the trip count is below the
minimum for tail folding.
MaxPowerOf2RuntimeVF being not set means we cannot compute the maximum
runtime VF, due to missing max vscale. In that case we are not able to
determine if a epilogue loop remains for scalable VFs, but we can still
pick a fixed VF, if no epilogue remains for it.
Also updates processLoop to ignore CM_EpilogueNotNeededFoldTail, if the
trip count is below the tail-folding threshold.
PR: https://github.com/llvm/llvm-project/pull/226318
Commit: 825903711948134578537eda6dd94a488ed50319
https://github.com/llvm/llvm-project/commit/825903711948134578537eda6dd94a488ed50319
Author: Lang Hames <lhames at gmail.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M orc-rt/include/orc-rt/support/bind.h
M orc-rt/test/unit/support/bind-test.cpp
Log Message:
-----------
[orc-rt] make bind_front match std::bind_front semantics. (#226646)
orc_rt::bind_front stands in for std::bind_front until the ORC runtime
can use C++20, so code written against it should keep working after the
switch. This commit brings its behavior in line with std::bind_front:
- noexcept propagation
- const and rvalue call operators, forwarding the wrapper's qualifiers
- no fallback to a differently-qualified call operator
- reference return types
- member pointers
- copyable wrappers, including nested binds
The unit tests are reorganized and extended to cover these.
Assisted-by: Claude
Commit: 0b4f72d00bdd2ef1707c5098d12936bfa159b414
https://github.com/llvm/llvm-project/commit/0b4f72d00bdd2ef1707c5098d12936bfa159b414
Author: Aditya Sinha <155882262+AdityaSinha149 at users.noreply.github.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M clang/include/clang/CodeGen/CodeGenAction.h
M clang/include/clang/Interpreter/Interpreter.h
M clang/lib/CodeGen/BackendConsumer.h
M clang/lib/CodeGen/CodeGenAction.cpp
M clang/lib/Interpreter/DeviceOffload.cpp
M clang/lib/Interpreter/DeviceOffload.h
M clang/lib/Interpreter/Interpreter.cpp
M clang/unittests/Basic/CMakeLists.txt
A clang/unittests/Basic/TargetIDTest.cpp
Log Message:
-----------
[clang-repl] Implement IncrementalHIPDeviceParser for HIP device compilation (#218337)
This PR implements the IncrementalHIPDeviceParser. It takes each
incremental statement's device code and lowers it all the way to a
loadable HIP fat binary: linking the ROCm device libraries, running the
AMDGPU optimization/codegen pipeline, producing a .hsaco code object,
and embedding it as __hip_fatbin for the host runtime to register and
launch.
This PR only adds the parser class, wiring it into Interpreter.cpp and
the end-to-end tests will come in a follow-up.
Assisted by Claude Opus 4.8
Commit: 5f609f950d2e80addf5566623013db68394334db
https://github.com/llvm/llvm-project/commit/5f609f950d2e80addf5566623013db68394334db
Author: Fangrui Song <i at maskray.me>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M llvm/docs/CommandLine.md
M llvm/include/llvm/Support/CommandLine.h
M llvm/unittests/Support/CommandLineTest.cpp
Log Message:
-----------
[Support] Remove cl::bits (#226628)
cl::list covers the same use, and cl::bits would block migration to
TableGen based representation.
LLM-aided
Commit: c0b6ee14c2f8dece229da557352e116f9a6d7064
https://github.com/llvm/llvm-project/commit/c0b6ee14c2f8dece229da557352e116f9a6d7064
Author: David Green <david.green at arm.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
A llvm/test/CodeGen/AArch64/sve-fixed-length-shuffle-reverse.ll
Log Message:
-----------
[AArch64] Add tests for sve fixed length reverse shuffles. NFC (#226661)
Commit: 96b5cc3d836494c56c8d5ae1e73e90864eb19a5d
https://github.com/llvm/llvm-project/commit/96b5cc3d836494c56c8d5ae1e73e90864eb19a5d
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M llvm/include/llvm/Analysis/BranchProbabilityInfo.h
M llvm/lib/Analysis/BranchProbabilityInfo.cpp
Log Message:
-----------
[BPI] Add getEdgeProbabilitiesFromWeights (NFC). (#226560)
Move computing edge probabilities from branch weights to a static
helper. This allows re-using the core logic when computing execution
frequencies in VPlan, fixing a number of subtle differences.
While touching the code, also modernize the code slightly.
Note that the helper does not handle the case where all successors are
unreachable. This would need additional info and is not needed for the
VPlan case.
PR: https://github.com/llvm/llvm-project/pull/226560
Commit: 97e9558844822e1ff8f986319ef354fda42b8215
https://github.com/llvm/llvm-project/commit/97e9558844822e1ff8f986319ef354fda42b8215
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M llvm/lib/CodeGen/DetectDeadLanes.cpp
R llvm/test/CodeGen/AMDGPU/detect-dead-lanes-reg-sequence-narrow-slot.mir
M llvm/test/CodeGen/AMDGPU/frem.ll
R llvm/test/CodeGen/AMDGPU/true16-uniform-f16-phi-copysign.ll
Log Message:
-----------
Revert "[CodeGen] Fix DetectDeadLanes for same-class copies with mismatched widths" (#226665)
Reverts llvm/llvm-project#226556
This is handling malformed IR and adding size based instead of register
class based reasoning
Commit: d94f3a52dad756d7354a9ca688b4ac76a97b9d38
https://github.com/llvm/llvm-project/commit/d94f3a52dad756d7354a9ca688b4ac76a97b9d38
Author: Lang Hames <lhames at gmail.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M orc-rt/test/unit/CMakeLists.txt
R orc-rt/test/unit/bedrock/SocketConnectorTest.cpp
M orc-rt/test/unit/bedrock/SocketTestUtils.h
M orc-rt/test/unit/bedrock/sps/SimpleRemoteCAOverSocketTest.cpp
A orc-rt/test/unit/bedrock/sys/posix/SocketConnectorTest.cpp
M orc-rt/test/unit/bedrock/sys/posix/SocketTestUtils.cpp
Log Message:
-----------
[orc-rt] Make socket unit tests portable; build them on POSIX. (#226662)
SimpleRemoteCAOverSocketTest.cpp tests a POSIX-only implementation, so
move it to the POSIX source list. Its tests are portable, so move the
fixture's POSIX code into SocketTestUtils (makeStreamSocketPair,
sendAll, recvAll, makeNativeNonStreamSocket) rather than moving the file
under sys/posix; a Windows transport will need only Windows definitions
of those helpers.
makeStreamSocketPair documents the properties the tests rely on beyond a
connected stream pair: neither direction buffers StallingPayloadSize
bytes, and closing an end delivers what it already sent even if it has
unread data. AF_UNIX provides both; a loopback TCP pair may not.
SocketConnectorTest.cpp tests fd adoption with pipe and fcntl, so it is
a test of the POSIX implementation: move it to sys/posix/.
Assisted-by: Claude
Commit: a4e311d3f80f0bc1b0912d3f9f650a8d949a06e5
https://github.com/llvm/llvm-project/commit/a4e311d3f80f0bc1b0912d3f9f650a8d949a06e5
Author: Lang Hames <lhames at gmail.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M llvm/lib/ExecutionEngine/Orc/ELFNixPlatform.cpp
M llvm/lib/ExecutionEngine/Orc/MachOPlatform.cpp
Log Message:
-----------
[ORC] Call createPThreadKey through a Proxy in MachO/ELFNixPlatform (#226656)
Replace the callSPSWrapper calls in MachOPlatform::createPThreadKey and
ELFNixPlatform::createPThreadKey with a Proxy built over the address
recorded during bootstrap, using a local CI descriptor for each
platform's create_pthread_key wrapper. The address stays in the
platforms' RuntimeFunction table, which is filled uniformly by the
bootstrap recording pass.
Commit: 0407861c32056a8ac57de2d7ef304ebbb3922139
https://github.com/llvm/llvm-project/commit/0407861c32056a8ac57de2d7ef304ebbb3922139
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M llvm/lib/Target/Mips/MipsAsmPrinter.cpp
M llvm/lib/Target/Mips/MipsAsmPrinter.h
M llvm/lib/Target/Mips/MipsBranchExpansion.cpp
M llvm/lib/Target/Mips/MipsCallLowering.cpp
M llvm/lib/Target/Mips/MipsFastISel.cpp
M llvm/lib/Target/Mips/MipsISelLowering.cpp
M llvm/lib/Target/Mips/MipsMachineFunction.cpp
M llvm/lib/Target/Mips/MipsRegisterInfo.cpp
M llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
M llvm/lib/Target/Mips/MipsSERegisterInfo.cpp
Log Message:
-----------
Mips: Route ABI queries through the subtarget (#226667)
Commit: e7019f85692bab245c02f4fa433b37105f2d9c0d
https://github.com/llvm/llvm-project/commit/e7019f85692bab245c02f4fa433b37105f2d9c0d
Author: Ivan Ho <ivan.ho at cl.cam.ac.uk>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M mlir/lib/Dialect/IRDL/IR/IRDL.cpp
M mlir/lib/Target/IRDLToCpp/IRDLToCpp.cpp
M mlir/test/lib/Dialect/TestIRDLToCpp/test_irdl_to_cpp.irdl.mlir
Log Message:
-----------
[MLIR][IRDL] Instantiate "." in IRDL-defined names as nested namespaces (#207035)
In PR #187911, it was revealed that the constraints on IRDL op names
placed by irdl-to-cpp were too restrictive.
This PR will address that by allowing "." in operation names to denote
nested namespaces, but not "$".
To discuss:
- ops like `wmma.f16.16x16x64.bf8_bf` cannot be registered as C++
identifiers cannot begin with a number. In discussions, we have opted to
prefix the generated namespaces with _.
Codex was used to generate the lit tests.
Close #187911.
Assisted-by: OpenAI Codex (GPT-5 and 6)
Commit: e8e4a54cfbbc054ec9801dea03e6c6868bf0708a
https://github.com/llvm/llvm-project/commit/e8e4a54cfbbc054ec9801dea03e6c6868bf0708a
Author: David Green <david.green at arm.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/test/CodeGen/AArch64/sve-fixed-length-shuffle-reverse.ll
Log Message:
-----------
[AArch64] Use SVE rev for full reverse shuffles with SVE128 (#224589)
When the vscale_range is always 1, we can make use of the SVE rev
instruction to perform a full 128bit vector reverse.
Sidesteps #223597 for SVE128
Commit: fccc8632f21fa8a13f7962932b614e8c1079d9ac
https://github.com/llvm/llvm-project/commit/fccc8632f21fa8a13f7962932b614e8c1079d9ac
Author: Lang Hames <lhames at gmail.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M orc-rt/include/orc-rt/bedrock/sps/SimpleRemoteCAOverSocket.h
M orc-rt/lib/bedrock/sys/posix/sps/SimpleRemoteCAOverSocket.cpp
M orc-rt/test/unit/bedrock/sps/SimpleRemoteCAOverSocketTest.cpp
Log Message:
-----------
[orc-rt] SimpleRemoteCAOverSocket: require a stream socket. (#226676)
SimpleRemote framing reads each message in as many parts as the socket
delivers it, which a socket that preserves message boundaries (datagram,
seqpacket) would truncate. Check SO_TYPE up front and reject anything
but SOCK_STREAM; the socket is owned by then, so it is closed on
failure.
Assisted-by: Claude
Commit: e9e27436e89127e5e42863cc6804945b3619b015
https://github.com/llvm/llvm-project/commit/e9e27436e89127e5e42863cc6804945b3619b015
Author: Ben Shi <2283975856 at qq.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M llvm/lib/Target/AVR/AVRAsmPrinter.cpp
M llvm/lib/Target/AVR/AVRDevices.td
M llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp
M llvm/lib/Target/AVR/AVRISelLowering.cpp
M llvm/lib/Target/AVR/AVRInstrInfo.cpp
M llvm/lib/Target/AVR/AVRInstrInfo.td
M llvm/lib/Target/AVR/AVRRegisterInfo.cpp
M llvm/lib/Target/AVR/MCTargetDesc/AVRMCAsmInfo.cpp
M llvm/lib/Target/AVR/MCTargetDesc/AVRMCTargetDesc.h
R llvm/lib/Target/AVR/TODO.md
Log Message:
-----------
[AVR][NFC] Improve some comment messages (#226423)
Commit: c495a9b796c46456e523a5eeb3690415ba99f5db
https://github.com/llvm/llvm-project/commit/c495a9b796c46456e523a5eeb3690415ba99f5db
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M clang/include/clang/CIR/Dialect/IR/CIRDialect.td
M flang/include/flang/Optimizer/Dialect/CUF/CUFDialect.td
M flang/include/flang/Optimizer/Dialect/FIRCG/CGOps.td
M flang/include/flang/Optimizer/Dialect/FIRDialect.td
M flang/include/flang/Optimizer/Dialect/MIF/MIFDialect.td
M flang/include/flang/Optimizer/HLFIR/HLFIROpBase.td
M mlir/docs/DefiningDialects/Operations.md
M mlir/docs/DefiningDialects/_index.md
M mlir/docs/ReleaseNotes.md
M mlir/examples/toy/Ch4/include/toy/Ops.td
M mlir/examples/toy/Ch5/include/toy/Ops.td
M mlir/examples/toy/Ch6/include/toy/Ops.td
M mlir/examples/toy/Ch7/include/toy/Ops.td
M mlir/include/mlir/Dialect/AMDGPU/IR/AMDGPUBase.td
M mlir/include/mlir/Dialect/Affine/IR/AffineOps.td
M mlir/include/mlir/Dialect/Arith/IR/ArithBase.td
M mlir/include/mlir/Dialect/ArmNeon/ArmNeon.td
M mlir/include/mlir/Dialect/ArmSME/IR/ArmSME.td
M mlir/include/mlir/Dialect/ArmSVE/IR/ArmSVE.td
M mlir/include/mlir/Dialect/Async/IR/AsyncDialect.td
M mlir/include/mlir/Dialect/Bufferization/IR/BufferizationBase.td
M mlir/include/mlir/Dialect/Complex/IR/ComplexBase.td
M mlir/include/mlir/Dialect/ControlFlow/IR/ControlFlowOps.td
M mlir/include/mlir/Dialect/DLTI/DLTIBase.td
M mlir/include/mlir/Dialect/EmitC/IR/EmitCBase.td
M mlir/include/mlir/Dialect/Func/IR/FuncOps.td
M mlir/include/mlir/Dialect/GPU/IR/GPUBase.td
M mlir/include/mlir/Dialect/IRDL/IR/IRDL.td
M mlir/include/mlir/Dialect/Index/IR/IndexDialect.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMDialect.td
M mlir/include/mlir/Dialect/LLVMIR/NVVMDialect.td
M mlir/include/mlir/Dialect/LLVMIR/ROCDLDialect.td
M mlir/include/mlir/Dialect/LLVMIR/VCIXOps.td
M mlir/include/mlir/Dialect/LLVMIR/XeVMOps.td
M mlir/include/mlir/Dialect/Linalg/IR/LinalgBase.td
M mlir/include/mlir/Dialect/MLProgram/IR/MLProgramBase.td
M mlir/include/mlir/Dialect/MPI/IR/MPI.td
M mlir/include/mlir/Dialect/Math/IR/MathBase.td
M mlir/include/mlir/Dialect/MemRef/IR/MemRefBase.td
M mlir/include/mlir/Dialect/NVGPU/IR/NVGPU.td
M mlir/include/mlir/Dialect/OpenACC/OpenACCBase.td
M mlir/include/mlir/Dialect/OpenMP/OpenMPDialect.td
M mlir/include/mlir/Dialect/PDL/IR/PDLDialect.td
M mlir/include/mlir/Dialect/PDLInterp/IR/PDLInterpOps.td
M mlir/include/mlir/Dialect/Ptr/IR/PtrDialect.td
M mlir/include/mlir/Dialect/Quant/IR/QuantBase.td
M mlir/include/mlir/Dialect/SCF/IR/SCFOps.td
M mlir/include/mlir/Dialect/SMT/IR/SMTDialect.td
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBase.td
M mlir/include/mlir/Dialect/Shape/IR/ShapeBase.td
M mlir/include/mlir/Dialect/Shard/IR/ShardBase.td
M mlir/include/mlir/Dialect/SparseTensor/IR/SparseTensorBase.td
M mlir/include/mlir/Dialect/Tensor/IR/TensorBase.td
M mlir/include/mlir/Dialect/Tosa/IR/TosaOpBase.td
M mlir/include/mlir/Dialect/Transform/IR/TransformDialect.td
M mlir/include/mlir/Dialect/UB/IR/UBOps.td
M mlir/include/mlir/Dialect/Vector/IR/Vector.td
M mlir/include/mlir/Dialect/WasmSSA/IR/WasmSSABase.td
M mlir/include/mlir/Dialect/X86/X86.td
M mlir/include/mlir/Dialect/XeGPU/IR/XeGPUDialect.td
M mlir/include/mlir/IR/BuiltinDialect.td
M mlir/include/mlir/IR/DialectBase.td
M mlir/test/lib/Dialect/Test/TestDialect.td
M mlir/test/mlir-tblgen/op-format-invalid.td
M mlir/test/mlir-tblgen/op-format.td
M mlir/test/python/python_test_ops.td
Log Message:
-----------
[mlir] Enable strict properties in assembly formats by default (#225742)
Make strict property assembly formats the default and remove redundant
per-dialect settings. Keep legacy test fixtures explicitly opted out and
update the documentation.
Downstream can opt out for now using `let
useStrictPropertiesInAssemblyFormat = 0;` ; This will be removed in a
future release.
Part of #155475
Assisted-by: Codex
Commit: 9f8d812535d90508d9932cc7c7d39756a5e5d2db
https://github.com/llvm/llvm-project/commit/9f8d812535d90508d9932cc7c7d39756a5e5d2db
Author: theRonShark <ron.lieberman at amd.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M clang/include/clang/CodeGen/CodeGenAction.h
M clang/include/clang/Interpreter/Interpreter.h
M clang/lib/CodeGen/BackendConsumer.h
M clang/lib/CodeGen/CodeGenAction.cpp
M clang/lib/Interpreter/DeviceOffload.cpp
M clang/lib/Interpreter/DeviceOffload.h
M clang/lib/Interpreter/Interpreter.cpp
M clang/unittests/Basic/CMakeLists.txt
R clang/unittests/Basic/TargetIDTest.cpp
Log Message:
-----------
Revert "[clang-repl] Implement IncrementalHIPDeviceParser for HIP device compilation" (#226679)
Reverts llvm/llvm-project#218337 buildbot failures
Commit: 10872feadab49e23b8a2ef831dc454b712937ae2
https://github.com/llvm/llvm-project/commit/10872feadab49e23b8a2ef831dc454b712937ae2
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
A llvm/test/Transforms/SLPVectorizer/AArch64/reduced-value-next-to-fused-fmul.ll
A llvm/test/Transforms/SLPVectorizer/AMDGPU/fmul-sunk-into-fadd-block.ll
Log Message:
-----------
[SLP][NFC]Add extra FMA candidates tests, NFC
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/226684
Commit: 1916c2c7fec07c06d0a781154f64bcce79576a0d
https://github.com/llvm/llvm-project/commit/1916c2c7fec07c06d0a781154f64bcce79576a0d
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-09-26 (Sat, 26 Sep 2026)
Changed paths:
M .github/workflows/libcxx-benchmark-commit.yml
M .github/workflows/libcxx-benchmark-cron.yml
M .github/workflows/libcxx-pr-benchmark.yml
M bolt/lib/Passes/BinaryPasses.cpp
M bolt/lib/Passes/ReorderFunctions.cpp
M bolt/lib/Profile/DataAggregator.cpp
M clang-tools-extra/clangd/tool/ClangdMain.cpp
M clang/docs/ReleaseNotes.md
M clang/include/clang/Basic/Builtins.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Basic/HLSLIntrinsics.td
M clang/include/clang/CIR/Dialect/Builder/CIRBaseBuilder.h
M clang/include/clang/CIR/Dialect/IR/CIRDialect.td
M clang/lib/AST/ByteCode/ByteCodeEmitter.h
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ByteCode/Context.cpp
M clang/lib/AST/ByteCode/Disasm.cpp
M clang/lib/AST/ByteCode/EvalEmitter.cpp
M clang/lib/AST/ByteCode/EvalEmitter.h
M clang/lib/AST/ByteCode/EvaluationResult.cpp
M clang/lib/AST/ByteCode/EvaluationResult.h
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/InterpBuiltinObjectSize.cpp
M clang/lib/AST/ByteCode/Pointer.cpp
M clang/lib/AST/ByteCode/Pointer.h
M clang/lib/AST/ExprConstShared.h
M clang/lib/AST/ExprConstant.cpp
M clang/lib/CIR/CodeGen/CIRGenDecl.cpp
M clang/lib/CodeGen/CGHLSLBuiltins.cpp
M clang/lib/CodeGen/CGHLSLRuntime.h
M clang/lib/CodeGen/CGLoopInfo.cpp
M clang/lib/CodeGen/TargetBuiltins/ARM.cpp
M clang/lib/Format/ContinuationIndenter.cpp
M clang/lib/Interpreter/IncrementalAction.cpp
M clang/lib/Lex/HeaderSearch.cpp
M clang/lib/Sema/SemaARM.cpp
M clang/lib/Sema/SemaHLSL.cpp
M clang/lib/Sema/SemaOpenMP.cpp
M clang/lib/Sema/SemaType.cpp
M clang/test/AST/ByteCode/builtin-functions.cpp
M clang/test/AST/ByteCode/codegen-constexpr-unknown.cpp
M clang/test/AST/ByteCode/references.cpp
M clang/test/CIR/CodeGenCUDA/address-spaces.cu
A clang/test/ClangScanDeps/modules-context-hash-case-sensitive-vfs-paths.c
M clang/test/ClangScanDeps/modules-context-hash-module-map-path.c
M clang/test/CodeGen/align-loops.c
M clang/test/CodeGenCXX/global-init.cpp
A clang/test/CodeGenHLSL/builtins/WaveReadLaneFirst.hlsl
A clang/test/Interpreter/nonexistent-xcc-file.cpp
A clang/test/Modules/implicit-module-map-path-case-sensitive.c
R clang/test/OpenMP/error_message.c
M clang/test/OpenMP/error_message.cpp
M clang/test/OpenMP/parallel_message_messages.cpp
M clang/test/Sema/large-bit-int.c
M clang/test/Sema/types.c
M clang/test/SemaCXX/PR19955.cpp
M clang/test/SemaCXX/cxx2c-expansion-stmts.cpp
M clang/test/SemaCXX/vector.cpp
A clang/test/SemaHLSL/BuiltIns/WaveReadLaneFirst-errors.hlsl
M clang/test/SemaHLSL/WaveBuiltinAvailability.hlsl
M clang/tools/clang-format/ClangFormat.cpp
M clang/unittests/Format/FormatTest.cpp
M flang/include/flang/Optimizer/Dialect/CUF/CUFDialect.td
M flang/include/flang/Optimizer/Dialect/FIRCG/CGOps.td
M flang/include/flang/Optimizer/Dialect/FIRDialect.td
M flang/include/flang/Optimizer/Dialect/MIF/MIFDialect.td
M flang/include/flang/Optimizer/HLFIR/HLFIROpBase.td
M flang/lib/Lower/OpenMP/ClauseProcessor.cpp
M flang/lib/Lower/OpenMP/Utils.cpp
M flang/lib/Lower/OpenMP/Utils.h
M flang/lib/Parser/openacc-parsers.cpp
M flang/test/Lower/OpenMP/declare-mapper.f90
A flang/test/Lower/OpenMP/target-map-nested-dtype-allocatable-member.f90
M flang/test/Parser/acc-label-do.f90
M libc/src/__support/FPUtil/FEnvImpl.h
M libcxx/include/CMakeLists.txt
M libcxx/include/__algorithm/pstl.h
M libcxx/include/__pstl/backend_fwd.h
M libcxx/include/__pstl/backends/default.h
M libcxx/include/__pstl/backends/libdispatch.h
M libcxx/include/__pstl/backends/serial.h
M libcxx/include/__pstl/backends/std_thread.h
A libcxx/include/__pstl/cpu_algos/swap_ranges.h
M libcxx/include/__ranges/adjacent_transform_view.h
M libcxx/include/__ranges/adjacent_view.h
M libcxx/include/__ranges/chunk_by_view.h
M libcxx/include/__ranges/common_view.h
M libcxx/include/__ranges/concat_view.h
M libcxx/include/__ranges/counted.h
M libcxx/include/__ranges/drop_view.h
M libcxx/include/__ranges/drop_while_view.h
M libcxx/include/__ranges/elements_view.h
M libcxx/include/__ranges/empty_view.h
M libcxx/include/__ranges/enumerate_view.h
M libcxx/include/__ranges/filter_view.h
M libcxx/include/__ranges/iota_view.h
M libcxx/include/__ranges/join_view.h
M libcxx/include/__ranges/join_with_view.h
M libcxx/include/__ranges/lazy_split_view.h
M libcxx/include/__ranges/movable_box.h
M libcxx/include/__ranges/non_propagating_cache.h
M libcxx/include/__ranges/rbegin.h
M libcxx/include/__ranges/rend.h
M libcxx/include/__ranges/reverse_view.h
M libcxx/include/__ranges/single_view.h
M libcxx/include/__ranges/split_view.h
M libcxx/include/__ranges/stride_view.h
M libcxx/include/__ranges/take_view.h
M libcxx/include/__ranges/take_while_view.h
M libcxx/include/__ranges/to.h
M libcxx/include/__ranges/transform_view.h
M libcxx/include/__ranges/views.h
M libcxx/include/__ranges/zip_transform_view.h
M libcxx/include/__ranges/zip_view.h
M libcxx/include/module.modulemap.in
M libcxx/test/benchmarks/containers/string.bench.cpp
M libcxx/test/libcxx/algorithms/pstl.iterator-requirements.verify.cpp
A libcxx/test/std/algorithms/alg.modifying.operations/alg.swap/pstl.swap_ranges.pass.cpp
M libcxx/test/std/algorithms/pstl.exception_handling.pass.cpp
M libcxx/utils/ci/lnt/README.md
M libcxx/utils/ci/lnt/machines.json
M libcxx/utils/ci/lnt/run-benchmarks
M libcxx/utils/ci/run-buildbot
M lldb/include/lldb/Target/Process.h
M lldb/include/lldb/Utility/StructuredData.h
M lldb/source/API/SBProcess.cpp
M lldb/source/Commands/CommandObjectVersion.cpp
M lldb/source/Target/Process.cpp
M lldb/source/Utility/StructuredData.cpp
M lldb/test/API/python_api/process/address-masks/TestAddressMasks.py
M lldb/test/API/python_api/value/TestValueAPI.py
M llvm/docs/CommandLine.md
M llvm/include/llvm/Analysis/BranchProbabilityInfo.h
M llvm/include/llvm/CodeGen/SDPatternMatch.h
M llvm/include/llvm/IR/AutoUpgrade.h
M llvm/include/llvm/IR/IntrinsicsDirectX.td
M llvm/include/llvm/IR/IntrinsicsSPIRV.td
M llvm/include/llvm/Support/AArch64MemoryHints.h
M llvm/include/llvm/Support/CommandLine.h
M llvm/include/llvm/Transforms/IPO/InstrumentorUtils.h
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/Passes/LoadStoreVec.h
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/VecUtils.h
M llvm/lib/Analysis/BranchProbabilityInfo.cpp
M llvm/lib/Analysis/TypeBasedAliasAnalysis.cpp
M llvm/lib/Bitcode/Reader/MetadataLoader.cpp
M llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
M llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
M llvm/lib/ExecutionEngine/Orc/ELFNixPlatform.cpp
M llvm/lib/ExecutionEngine/Orc/MachOPlatform.cpp
M llvm/lib/IR/AutoUpgrade.cpp
M llvm/lib/MC/WasmObjectWriter.cpp
M llvm/lib/Support/StringRef.cpp
M llvm/lib/Target/AArch64/AArch64CodeLayoutOpt.cpp
M llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AVR/AVRAsmPrinter.cpp
M llvm/lib/Target/AVR/AVRDevices.td
M llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp
M llvm/lib/Target/AVR/AVRISelLowering.cpp
M llvm/lib/Target/AVR/AVRInstrInfo.cpp
M llvm/lib/Target/AVR/AVRInstrInfo.td
M llvm/lib/Target/AVR/AVRRegisterInfo.cpp
M llvm/lib/Target/AVR/MCTargetDesc/AVRMCAsmInfo.cpp
M llvm/lib/Target/AVR/MCTargetDesc/AVRMCTargetDesc.h
R llvm/lib/Target/AVR/TODO.md
M llvm/lib/Target/DirectX/DXIL.td
M llvm/lib/Target/DirectX/DXILOpBuilder.cpp
M llvm/lib/Target/DirectX/DXILShaderFlags.cpp
M llvm/lib/Target/Mips/MipsAsmPrinter.cpp
M llvm/lib/Target/Mips/MipsAsmPrinter.h
M llvm/lib/Target/Mips/MipsBranchExpansion.cpp
M llvm/lib/Target/Mips/MipsCallLowering.cpp
M llvm/lib/Target/Mips/MipsFastISel.cpp
M llvm/lib/Target/Mips/MipsISelLowering.cpp
M llvm/lib/Target/Mips/MipsMachineFunction.cpp
M llvm/lib/Target/Mips/MipsRegisterInfo.cpp
M llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
M llvm/lib/Target/Mips/MipsSERegisterInfo.cpp
M llvm/lib/Target/RISCV/RISCVExpandPseudoPostRA.cpp
M llvm/lib/Target/RISCV/RISCVExpandPseudoPreEmit.cpp
M llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
M llvm/lib/Target/RISCV/RISCVLoadStoreOptimizer.cpp
M llvm/lib/Target/RISCV/RISCVZilsdOptimizer.cpp
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
M llvm/lib/Transforms/IPO/Instrumentor.cpp
M llvm/lib/Transforms/Scalar/LoopFuse.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/Passes/LoadStoreVec.cpp
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/VecUtils.cpp
M llvm/lib/Transforms/Vectorize/VPlan.cpp
M llvm/lib/Transforms/Vectorize/VPlanHelpers.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanVerifier.cpp
M llvm/runtimes/CMakeLists.txt
A llvm/test/Bitcode/upgrade-tbaa-struct.ll
A llvm/test/Bitcode/upgrade-tbaa-struct.ll.bc
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-undef.mir
A llvm/test/CodeGen/AArch64/sve-fixed-length-shuffle-reverse.ll
M llvm/test/CodeGen/AMDGPU/call-constant.ll
M llvm/test/CodeGen/AMDGPU/invalid-addrspacecast.ll
M llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-pal.ll
M llvm/test/CodeGen/DirectX/LoadInput.ll
A llvm/test/CodeGen/DirectX/LongVector/wave-readlane-first.ll
M llvm/test/CodeGen/DirectX/ShaderFlags/wave-ops.ll
M llvm/test/CodeGen/DirectX/StoreOutput.ll
A llvm/test/CodeGen/DirectX/WaveReadLaneFirst.ll
A llvm/test/CodeGen/DirectX/WaveReadLaneFirst_mat.ll
M llvm/test/CodeGen/Mips/extins.ll
M llvm/test/CodeGen/RISCV/rvv/trunc-select-to-max-usat.ll
A llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_long_vector/wave-readlane-first.ll
A llvm/test/CodeGen/SPIRV/hlsl-intrinsics/WaveReadLaneFirst.ll
A llvm/test/CodeGen/SPIRV/hlsl-intrinsics/WaveReadLaneFirst_mat.ll
M llvm/test/CodeGen/X86/llvm.frexp.ll
M llvm/test/MC/WebAssembly/reloc-pic64.s
M llvm/test/Transforms/InstCombine/struct-assign-tbaa.ll
A llvm/test/Transforms/LoopFusion/guard_skip_empty_block.ll
A llvm/test/Transforms/LoopVectorize/AArch64/diff-checks-force-interleave-count.ll
A llvm/test/Transforms/LoopVectorize/AArch64/low-trip-count-fixed-vf-no-epilogue.ll
M llvm/test/Transforms/LoopVectorize/RISCV/short-trip-count.ll
M llvm/test/Transforms/LoopVectorize/VPlan/execution-frequencies-match-bfi.ll
M llvm/test/Transforms/LoopVectorize/X86/predicated-instruction-cost.ll
M llvm/test/Transforms/LoopVectorize/replicate-region-branch-weights.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/hor-fp-reduction-instcount.ll
A llvm/test/Transforms/SLPVectorizer/AArch64/ordered-reduction-of-loads.ll
A llvm/test/Transforms/SLPVectorizer/AArch64/reduced-value-next-to-fused-fmul.ll
A llvm/test/Transforms/SLPVectorizer/AMDGPU/fmul-sunk-into-fadd-block.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/ordered-reduction.ll
A llvm/test/Transforms/SLPVectorizer/RISCV/trimmed-node-matching-gather.ll
M llvm/unittests/ADT/StringRefTest.cpp
M llvm/unittests/Support/CommandLineTest.cpp
M llvm/unittests/Transforms/Vectorize/VPlanVerifierTest.cpp
M llvm/utils/gn/secondary/lld/unittests/AsLibELF/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/Target/AMDGPU/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/DebugInfo/LogicalView/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/DebugInfo/PDB/BUILD.gn
M mlir/docs/DefiningDialects/Operations.md
M mlir/docs/DefiningDialects/_index.md
M mlir/docs/Interfaces.md
M mlir/docs/ReleaseNotes.md
M mlir/examples/toy/Ch4/include/toy/Ops.td
M mlir/examples/toy/Ch5/include/toy/Ops.td
M mlir/examples/toy/Ch6/include/toy/Ops.td
M mlir/examples/toy/Ch7/include/toy/Ops.td
M mlir/include/mlir/Dialect/AMDGPU/IR/AMDGPUBase.td
M mlir/include/mlir/Dialect/Affine/IR/AffineOps.td
M mlir/include/mlir/Dialect/Arith/IR/ArithBase.td
M mlir/include/mlir/Dialect/ArmNeon/ArmNeon.td
M mlir/include/mlir/Dialect/ArmSME/IR/ArmSME.td
M mlir/include/mlir/Dialect/ArmSVE/IR/ArmSVE.td
M mlir/include/mlir/Dialect/Async/IR/AsyncDialect.td
M mlir/include/mlir/Dialect/Bufferization/IR/BufferizationBase.td
M mlir/include/mlir/Dialect/Complex/IR/ComplexBase.td
M mlir/include/mlir/Dialect/ControlFlow/IR/ControlFlowOps.td
M mlir/include/mlir/Dialect/DLTI/DLTIBase.td
M mlir/include/mlir/Dialect/EmitC/IR/EmitCBase.td
M mlir/include/mlir/Dialect/Func/IR/FuncOps.td
M mlir/include/mlir/Dialect/GPU/IR/GPUBase.td
M mlir/include/mlir/Dialect/IRDL/IR/IRDL.td
M mlir/include/mlir/Dialect/Index/IR/IndexDialect.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMDialect.td
M mlir/include/mlir/Dialect/LLVMIR/NVVMDialect.td
M mlir/include/mlir/Dialect/LLVMIR/ROCDLDialect.td
M mlir/include/mlir/Dialect/LLVMIR/VCIXOps.td
M mlir/include/mlir/Dialect/LLVMIR/XeVMOps.td
M mlir/include/mlir/Dialect/Linalg/IR/LinalgBase.td
M mlir/include/mlir/Dialect/Linalg/IR/LinalgInterfaces.td
M mlir/include/mlir/Dialect/MLProgram/IR/MLProgramBase.td
M mlir/include/mlir/Dialect/MPI/IR/MPI.td
M mlir/include/mlir/Dialect/Math/IR/MathBase.td
M mlir/include/mlir/Dialect/MemRef/IR/MemRefBase.td
M mlir/include/mlir/Dialect/NVGPU/IR/NVGPU.td
M mlir/include/mlir/Dialect/OpenACC/OpenACCBase.td
M mlir/include/mlir/Dialect/OpenACC/OpenACCOpsInterfaces.td
M mlir/include/mlir/Dialect/OpenMP/OpenMPDialect.td
M mlir/include/mlir/Dialect/OpenMP/OpenMPOpsInterfaces.td
M mlir/include/mlir/Dialect/PDL/IR/PDLDialect.td
M mlir/include/mlir/Dialect/PDLInterp/IR/PDLInterpOps.td
M mlir/include/mlir/Dialect/Ptr/IR/PtrDialect.td
M mlir/include/mlir/Dialect/Quant/IR/QuantBase.td
M mlir/include/mlir/Dialect/SCF/IR/SCFOps.td
M mlir/include/mlir/Dialect/SMT/IR/SMTDialect.td
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBase.td
M mlir/include/mlir/Dialect/Shape/IR/ShapeBase.td
M mlir/include/mlir/Dialect/Shard/IR/ShardBase.td
M mlir/include/mlir/Dialect/SparseTensor/IR/SparseTensorBase.td
M mlir/include/mlir/Dialect/SparseTensor/IR/SparseTensorInterfaces.td
M mlir/include/mlir/Dialect/Tensor/IR/TensorBase.td
M mlir/include/mlir/Dialect/Tosa/IR/TosaOpBase.td
M mlir/include/mlir/Dialect/Transform/IR/TransformDialect.td
M mlir/include/mlir/Dialect/UB/IR/UBOps.td
M mlir/include/mlir/Dialect/Vector/IR/Vector.td
M mlir/include/mlir/Dialect/WasmSSA/IR/WasmSSABase.td
M mlir/include/mlir/Dialect/WasmSSA/IR/WasmSSAInterfaces.td
M mlir/include/mlir/Dialect/X86/X86.td
M mlir/include/mlir/Dialect/XeGPU/IR/XeGPUDialect.td
M mlir/include/mlir/IR/BuiltinOps.td
M mlir/include/mlir/IR/DialectBase.td
M mlir/include/mlir/Interfaces/ControlFlowInterfaces.td
M mlir/lib/Dialect/IRDL/IR/IRDL.cpp
M mlir/lib/Target/IRDLToCpp/IRDLToCpp.cpp
M mlir/python/mlir/dialects/ext.py
M mlir/test/IR/module-op.mlir
M mlir/test/Transforms/sccp-callgraph.mlir
M mlir/test/Transforms/test-symbol-dce.mlir
M mlir/test/lib/Dialect/Test/TestDialect.td
M mlir/test/lib/Dialect/TestIRDLToCpp/test_irdl_to_cpp.irdl.mlir
M mlir/test/mlir-tblgen/op-format-invalid.td
M mlir/test/mlir-tblgen/op-format.td
M mlir/test/mlir-tblgen/op-interface.td
M mlir/test/python/dialects/ext.py
M mlir/test/python/dialects/ml_program.py
M mlir/test/python/python_test_ops.td
M mlir/tools/mlir-tblgen/OpInterfacesGen.cpp
M offload/test/offloading/info.c
M orc-rt/include/orc-rt-c/config.h.in
M orc-rt/include/orc-rt-c/support/Logging.h
M orc-rt/include/orc-rt/bedrock/Session.h
M orc-rt/include/orc-rt/bedrock/sps/SimpleRemoteCAOverSocket.h
M orc-rt/include/orc-rt/support/bind.h
M orc-rt/lib/bedrock/Session.cpp
M orc-rt/lib/bedrock/sys/posix/sps/SimpleRemoteCAOverSocket.cpp
M orc-rt/test/unit/CMakeLists.txt
M orc-rt/test/unit/CommonTestUtils.h
M orc-rt/test/unit/bedrock/InProcessControllerAccessTest.cpp
M orc-rt/test/unit/bedrock/SessionTest.cpp
R orc-rt/test/unit/bedrock/SocketConnectorTest.cpp
M orc-rt/test/unit/bedrock/SocketTestUtils.h
M orc-rt/test/unit/bedrock/sps/SimpleRemoteCAOverSocketTest.cpp
A orc-rt/test/unit/bedrock/sys/posix/SocketConnectorTest.cpp
M orc-rt/test/unit/bedrock/sys/posix/SocketTestUtils.cpp
M orc-rt/test/unit/support/LoggingTest.cpp
M orc-rt/test/unit/support/bind-test.cpp
M orc-rt/tools/ogre/ogre.cpp
M utils/bazel/MODULE.bazel.lock
M utils/bazel/linux_uapi.bzl
Log Message:
-----------
Rebase, address comments, improvements
Created using spr 1.3.7
Compare: https://github.com/llvm/llvm-project/compare/92388ee55bba...1916c2c7fec0
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