[all-commits] [llvm/llvm-project] 7af28a: [SystemZ][z/OS] Use section ordinal for temporary ...
Syadus Sefat via All-commits
all-commits at lists.llvm.org
Fri Sep 25 21:13:41 PDT 2026
Branch: refs/heads/users/mssefat/anti-hints-pr4-amdgpu-pre-ra
Home: https://github.com/llvm/llvm-project
Commit: 7af28a7e7b3073593d5f394d02b10f382d6cbab1
https://github.com/llvm/llvm-project/commit/7af28a7e7b3073593d5f394d02b10f382d6cbab1
Author: Kai Nacke <kai.peter.nacke at ibm.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/MC/GOFFObjectWriter.cpp
M llvm/test/CodeGen/SystemZ/zos-section-1.ll
M llvm/test/CodeGen/SystemZ/zos-section-2.ll
M llvm/test/CodeGen/SystemZ/zos-symbol-2.ll
Log Message:
-----------
[SystemZ][z/OS] Use section ordinal for temporary symbols (#226306)
A relocation involving a temporary symbol is interpreted as offset of
the symbol to the section begin. Currently, this is resolved via the
begin symbol of the section. However, that symbol may also have the
temporary flag set, and therefore has an index of 0. Since a symbol is
emitted of reach section, it is safe to use the ordinal of the section
instead, avoiding all issues with temporary symbols.
Commit: 621e088c0f5d435506a0d344d3b62ddc11f16147
https://github.com/llvm/llvm-project/commit/621e088c0f5d435506a0d344d3b62ddc11f16147
Author: Ebuka Ezike <e_ezike at apple.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M lldb/packages/Python/lldbsuite/test/tools/lldb_dap/session_helpers.py
M lldb/tools/lldb-dap/Handler/ThreadsRequestHandler.cpp
Log Message:
-----------
[lldb-dap] Always return the up-to-date thread if possible. (#226140)
Only send the initial thread list if the process is not stopped and only
the first time.
Remove the workaround in tests. This should not affect tests since we
mostly get the `threadId` from a stopped event.
Commit: edd241997b82b7803bd496933e340762cc06bd77
https://github.com/llvm/llvm-project/commit/edd241997b82b7803bd496933e340762cc06bd77
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h
Log Message:
-----------
[LV] Remove unused VectorizationFactor comparison operators (NFC) (#226511)
VectorizationFactor::operator== and operator!= have no users. Remove it.
Commit: 8ccb1826dad0257eda59d88b5fd35a0bc3b933f8
https://github.com/llvm/llvm-project/commit/8ccb1826dad0257eda59d88b5fd35a0bc3b933f8
Author: Pedro Vicente <pmadcv at gmail.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/docs/LangRef.md
M llvm/docs/ReleaseNotes.md
M llvm/include/llvm-c/Core.h
M llvm/include/llvm/Analysis/InstSimplifyFolder.h
M llvm/include/llvm/Analysis/TargetFolder.h
M llvm/include/llvm/AsmParser/LLParser.h
M llvm/include/llvm/AsmParser/LLToken.h
M llvm/include/llvm/Bitcode/LLVMBitCodes.h
M llvm/include/llvm/IR/ConstantFolder.h
M llvm/include/llvm/IR/IRBuilder.h
M llvm/include/llvm/IR/IRBuilderFolder.h
M llvm/include/llvm/IR/InstVisitor.h
M llvm/include/llvm/IR/Instruction.def
M llvm/include/llvm/IR/Instructions.h
M llvm/include/llvm/IR/NoFolder.h
M llvm/lib/AsmParser/LLLexer.cpp
M llvm/lib/AsmParser/LLParser.cpp
M llvm/lib/Bitcode/Reader/BitcodeReader.cpp
M llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
M llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h
M llvm/lib/CodeGen/TargetLoweringBase.cpp
M llvm/lib/IR/AsmWriter.cpp
M llvm/lib/IR/Core.cpp
M llvm/lib/IR/Instruction.cpp
M llvm/lib/IR/Instructions.cpp
M llvm/lib/IR/Verifier.cpp
M llvm/test/Analysis/IR2Vec/Inputs/reference_default_vocab_print.txt
M llvm/test/Analysis/IR2Vec/Inputs/reference_wtd1_vocab_print.txt
M llvm/test/Analysis/IR2Vec/Inputs/reference_wtd2_vocab_print.txt
A llvm/test/Assembler/bitinsert-bitextract-invalid.ll
A llvm/test/Assembler/bitinsert-bitextract.ll
M llvm/test/Bitcode/compatibility.ll
A llvm/test/CodeGen/AArch64/bitinsert-bitextract-common-offsets.ll
A llvm/test/CodeGen/AArch64/bitinsert-bitextract-fp.ll
A llvm/test/CodeGen/AArch64/bitinsert-bitextract.ll
A llvm/test/CodeGen/AMDGPU/bitinsert-bitextract-common-offsets.ll
A llvm/test/CodeGen/AMDGPU/bitinsert-bitextract-fp.ll
A llvm/test/CodeGen/AMDGPU/bitinsert-bitextract.ll
A llvm/test/CodeGen/ARM/bitinsert-bitextract-common-offsets.ll
A llvm/test/CodeGen/ARM/bitinsert-bitextract-fp.ll
A llvm/test/CodeGen/ARM/bitinsert-bitextract.ll
A llvm/test/CodeGen/PowerPC/bitinsert-bitextract-common-offsets.ll
A llvm/test/CodeGen/PowerPC/bitinsert-bitextract-fp.ll
A llvm/test/CodeGen/PowerPC/bitinsert-bitextract.ll
A llvm/test/CodeGen/RISCV/bitinsert-bitextract-common-offsets.ll
A llvm/test/CodeGen/RISCV/bitinsert-bitextract-fp.ll
A llvm/test/CodeGen/RISCV/bitinsert-bitextract.ll
A llvm/test/CodeGen/X86/GlobalISel/bitinsert-bitextract.ll
A llvm/test/CodeGen/X86/bitinsert-bitextract-common-offsets.ll
A llvm/test/CodeGen/X86/bitinsert-bitextract-fp.ll
A llvm/test/CodeGen/X86/bitinsert-bitextract.ll
A llvm/test/Verifier/bitextract-bitinsert-invalid-verifier.ll
M llvm/test/tools/llvm-ir2vec/entities.ll
M llvm/test/tools/llvm-ir2vec/triplets.ll
M llvm/tools/llvm-c-test/echo.cpp
M llvm/unittests/Analysis/IR2VecTest.cpp
Log Message:
-----------
[IR] Implementation and lowering of `bitinsert` and `bitextract` (#200605)
This PR introduces `bitinsert` and `bitextract` instructions for LLVM
IR. These allow bit manipulation for byte types. Both were lowered to
GlobalIsel and SDag.
Tests were added for AArch64, AMDGPU, ARM, PowerPC, RISCV, x86 and LLVM
IR.
The LangRef was updated to document the new instructions.
The lowering of `bitextract` and `bitinsert` instructions are
implemented using integer operations.
In order to obtain the results for `bitextract`, a shift right
instruction with a specific offset is used (that can be a variable or an
immediate).
Relative to floating-point, in `bitinsert`, we reinterpret the bits of
the floating-point value as if it is an integer.
Pointer operands and results are reinterpreted as if by bitcast, as
specified in the LangRef.
This PR is based on the RFC:
https://discourse.llvm.org/t/rfc-bitinsert-and-bitextract-instructions-for-llvm-ir-2/90764
Commit: 5b8e65685b4fe99191a217bfa0527c51cf36925c
https://github.com/llvm/llvm-project/commit/5b8e65685b4fe99191a217bfa0527c51cf36925c
Author: Jason Van Beusekom <jason.van-beusekom at hpe.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M offload/include/Shared/SourceInfo.h
M openmp/docs/ReleaseNotes.md
Log Message:
-----------
[Offload][OpenMP] remove SourceInfo::removePath (#226283)
Following discussion on
https://discourse.llvm.org/t/rfc-add-opt-in-option-for-full-source-paths-in-offload-info-output/91901
this commit removes SourceInfo::removePath which changes
LIBOMPTARGET_INFO to provide a non truncated source path:
``` c
#include <stdio.h>
#define N 4
int main(void) {
int a[N];
for (int i = 0; i < N; ++i)
a[i] = 0;
#pragma omp target map(tofrom : a[0 : N])
{
a[0] = 1;
}
printf("%d\n", a[0]); /* expect 1 */
return 0;
}
```
``` bash
clang -fopenmp -fopenmp-targets=amdgcn-amd-amdhsa -g ./test/test.c
# new
LIBOMPTARGET_INFO=-1 ./a.out
omptarget device 0 info: Entering OpenMP kernel at ./test/test.c:9:1 with 1 arguments:
# old
LIBOMPTARGET_INFO=-1 ./a.out
omptarget device 0 info: Entering OpenMP kernel at test.c:9:1 with 1 arguments:
```
Commit: 0551d60c516c2dc161007ee9ed466f36be40667d
https://github.com/llvm/llvm-project/commit/0551d60c516c2dc161007ee9ed466f36be40667d
Author: Zorojuro <sawantsukumar at gmail.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M libc/src/__support/math/bf16sub.h
M libc/src/__support/math/bf16subf.h
M libc/src/__support/math/bf16subf128.h
M libc/test/shared/shared_math_constexpr_test.cpp
Log Message:
-----------
[libc] Make bf16sub functions constexpr (#223506)
Makes the bf16sub for all types constexpr along with tests
Commit: d4c354ca333192d2db3d45b2b028a98f9fbbd347
https://github.com/llvm/llvm-project/commit/d4c354ca333192d2db3d45b2b028a98f9fbbd347
Author: Maksim Levental <maksim.levental at gmail.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M mlir/include/mlir-c/Rewrite.h
M mlir/lib/CAPI/Transforms/Rewrite.cpp
M mlir/test/CAPI/CMakeLists.txt
M mlir/test/CAPI/rewrite.c
Log Message:
-----------
[mlir-c] Add mlirDialectMaterializeConstant (#206553)
Exposes `Dialect::materializeConstant` through the MLIR C API, letting
callers ask a dialect to build a constant operation for a given
attribute and type.
Assisted by: Claude
Commit: 14f451262dc753b53f79a103744dd6988894467f
https://github.com/llvm/llvm-project/commit/14f451262dc753b53f79a103744dd6988894467f
Author: Derek Schuff <dschuff at chromium.org>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M clang/lib/Basic/Targets/WebAssembly.cpp
M clang/lib/Basic/Targets/WebAssembly.h
M clang/test/CodeGen/thread-model.c
M clang/test/CodeGenCXX/static-init-wasm.cpp
M clang/test/Preprocessor/init.c
M llvm/lib/Target/WebAssembly/WebAssemblyCoalesceFeaturesAndStripAtomics.cpp
M llvm/lib/TargetParser/Triple.cpp
R llvm/test/CodeGen/WebAssembly/coalesce-features-thread-model.ll
Log Message:
-----------
[clang][WeAssembly] Do not override thread model when building without atomics (#225981)
This change does 2 things. The first is to revert #223917, setting the
Triple's
default thread model back to posix. The second is to stop overriding it
when
atomics are not enabled.
This means that compiles with no thread- or atomics-related flags will
get the default posix thread model, independently of whether they get
_REENTRANT defined or the atomics feature is enabled. Practically this
means that the thread model will always be posix unless explicitly
overridden at the driver command line.
The leftover setting of Opts.POSIXThreads became a no-op when used
with the clang driver because the logic would only activate when
-pthread
was not already used (since the driver has separate logic linking
several
flags together).
This is a safer version of the status quo before the thread-model
module flag was introduced, because atomics are still lowered
in the same way but there is no risk of unsafe initialization
or LICM in such scenarios. We could probably further simplify
the interaction between various thread- and atomics-related
flags and thread agnosticism, but this is a small step
that fixes a known hazard.
Commit: 73fc71b19905b15e6ff14ae3149c6fabce961c1b
https://github.com/llvm/llvm-project/commit/73fc71b19905b15e6ff14ae3149c6fabce961c1b
Author: Jan Svoboda <jan_svoboda at apple.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M clang/unittests/Lex/LexerTest.cpp
Log Message:
-----------
[clang][test] Fix lifetimes of HS/PP options (#225885)
PR #133467 changed how lifetimes work for `PreprocessorOptions`. In
LexerTest.cpp, the lifetimes were set up incorrectly, leading to
potential use-after-free crashes. This PR fixes that by expanding the
lifetime of both `PreprocessorOptions` and `HeaderSearchOptions`.
Commit: 9068aede6fcbd3e47602fce96fbb077e3e4d8cc4
https://github.com/llvm/llvm-project/commit/9068aede6fcbd3e47602fce96fbb077e3e4d8cc4
Author: Luke Lau <luke at igalia.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/test/Transforms/LoopVectorize/early-exit-live-out-extract-lane.ll
Log Message:
-----------
[LV] Fix early exit tests after #223643. NFC (#226521)
Commit: 44f262eb67778e6bcb7675599384e010062cae10
https://github.com/llvm/llvm-project/commit/44f262eb67778e6bcb7675599384e010062cae10
Author: Alison Zhang <alisonzhang at ibm.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M clang/test/Analysis/Scalable/ssaf-src-edit-merge/conflict-preserves-unrelated-zero-length-insert.test
M clang/test/Analysis/Scalable/ssaf-src-edit-merge/conflict-stderr-without-sarif.test
M clang/test/Analysis/Scalable/ssaf-src-edit-merge/empty-input.test
M clang/test/Analysis/Scalable/ssaf-src-edit-merge/identical-overlap.test
M clang/test/Analysis/Scalable/ssaf-src-edit-merge/no-conflict-sarif-empty.test
M clang/test/Analysis/Scalable/ssaf-src-edit-merge/non-overlapping.test
M clang/test/Analysis/Scalable/ssaf-src-edit-merge/order-invariance.test
M clang/test/Analysis/Scalable/ssaf-src-edit-merge/parent-dir-missing.test
M clang/test/Analysis/Scalable/ssaf-src-edit-merge/pre-dedup-identical-non-zero-length.test
M clang/test/Analysis/Scalable/ssaf-src-edit-merge/pre-dedup-zero-length-insert.test
M clang/test/Analysis/Scalable/ssaf-src-edit-merge/range-overlap-cluster-of-three-sarif.test
M clang/test/Analysis/Scalable/ssaf-src-edit-merge/range-overlap-conflict-sarif.test
M clang/test/Analysis/Scalable/ssaf-src-edit-merge/sarif-out-parent-dir-missing.test
M clang/test/Analysis/Scalable/ssaf-src-edit-merge/single-input-internal-conflict.test
M clang/test/Analysis/Scalable/ssaf-src-edit-merge/single-input.test
M clang/test/Analysis/Scalable/ssaf-src-edit-merge/three-input-all-conflict.test
M clang/test/Analysis/Scalable/ssaf-src-edit-merge/three-input-conflict-sarif.test
M clang/test/Analysis/Scalable/ssaf-src-edit-merge/two-conflicts-different-offsets-sarif.test
M clang/test/Analysis/Scalable/ssaf-src-edit-merge/two-input-conflict-sarif.test
M clang/test/Analysis/Scalable/ssaf-src-edit-merge/two-input-conflict.test
Log Message:
-----------
[test][ssaf][AIX] Fix sed -i portability for AIX (#226293)
AIX's sed does not support the `-i` flag, causing the tests added in
https://github.com/llvm/llvm-project/pull/216183 to fail on AIX. This
patch updates the tests to use a POSIX-compliant redirect instead.
Commit: f1129f338806da062347a8ce019b88b51452917f
https://github.com/llvm/llvm-project/commit/f1129f338806da062347a8ce019b88b51452917f
Author: Ellis Hoag <ellis.sparky.hoag at gmail.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
R llvm/test/Transforms/PGOProfile/Inputs/indirect_call.proftext
M llvm/test/Transforms/PGOProfile/indirect_call_annotation.ll
Log Message:
-----------
[NFC][PGOProfile] Inline icall annotation proftext test (#226324)
Commit: 378ceb307bbc729bb918601a28c468df419b4d34
https://github.com/llvm/llvm-project/commit/378ceb307bbc729bb918601a28c468df419b4d34
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M clang/include/clang/Basic/BuiltinsRISCV.td
M clang/lib/CodeGen/TargetBuiltins/RISCV.cpp
M clang/lib/Headers/riscv_packed_simd.h
M clang/test/CodeGen/RISCV/rvp-intrinsics.c
M llvm/include/llvm/IR/IntrinsicsRISCV.td
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoP.td
M llvm/test/CodeGen/RISCV/rvp-simd-32.ll
M llvm/test/CodeGen/RISCV/rvp-simd-64.ll
Log Message:
-----------
[RISCV][P-Ext] Add builtins and IR intrinsics for packed shifts. (#225968)
The packed shift instructions use 5-bit shift amounts regardless of
element width. The C intrinsic should match this which means we can't
use C shift operators to implement them.
Rename RISCVISD::PSHL to RISCVISD::PSLL.
Commit: 1f9d3b2506fa32981fd281aab56357404af53ffe
https://github.com/llvm/llvm-project/commit/1f9d3b2506fa32981fd281aab56357404af53ffe
Author: Ellis Hoag <ellis.sparky.hoag at gmail.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
Log Message:
-----------
[NFC][PGOProfile] Inline icall annotation proftext test (#226324)
Commit: bff7b7503c1cdfdba72bcd12ef8208ad42130946
https://github.com/llvm/llvm-project/commit/bff7b7503c1cdfdba72bcd12ef8208ad42130946
Author: Ömer Sinan Ağacan <omer at osa1.net>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-vmax.ll
Log Message:
-----------
[msan] Update intrinsic list in arm64-vmax.ll (NFC) (#226387)
The intrinsics llvm.aarch64.neon.{u,s}{min,max} were removed in
0ce1b5f91add535d1e8b910ee90c178e054c65eb, remove the mentions of them in
the test file as per the review comment in #225339.
Commit: 6ec87e7ec4b3ca6f665a02e05d0e5fe9c37cd6cc
https://github.com/llvm/llvm-project/commit/6ec87e7ec4b3ca6f665a02e05d0e5fe9c37cd6cc
Author: Anshul Nigham <nigham at google.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/lldb/BUILD.bazel
Log Message:
-----------
[Bazel] Add Telemetry dependency to lldb-dap (#226526)
Fixes lldb-dap bazel layering failure introduced in commit 1cc5657c4ff6,
where LLDBUtils.h includes llvm/Telemetry/Telemetry.h.
Commit: 23e12c97a04c034a9487f4b95e3531d1ead90c59
https://github.com/llvm/llvm-project/commit/23e12c97a04c034a9487f4b95e3531d1ead90c59
Author: Kunal Dubey <xakep8 at protonmail.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M clang/include/clang/CIR/Dialect/IR/CIRAttrs.td
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/lib/CIR/CodeGen/CIRGenBuilder.h
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
M clang/test/CIR/IR/enum-attrs.cir
M clang/test/CIR/Lowering/call-llvm-intrinsic.cir
Log Message:
-----------
[CIR] Added fast-math flags to LLVM intrinsic calls (#224899)
Added fast-math flags attribute to CIR which cir.call_llvm_intrinsic now
carries through DirectToLLVM lowering. CIR now preserves fast-math flags
such as reassoc when lowering to llvm.call_intrinsic.
Added test for the same.
Commit: 774b4527fd60dc5ef7ed6539a8f2e6fe100e337b
https://github.com/llvm/llvm-project/commit/774b4527fd60dc5ef7ed6539a8f2e6fe100e337b
Author: Ryan Buchner <rbuchner at qti.qualcomm.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/include/llvm/Analysis/TargetTransformInfo.h
M llvm/include/llvm/CodeGen/BasicTTIImpl.h
M llvm/lib/Target/RISCV/RISCVProcessors.td
M llvm/lib/Target/RISCV/RISCVSubtarget.h
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/test/Analysis/CostModel/RISCV/vp-intrinsics.ll
Log Message:
-----------
[Analysis][RISCV] More accurately estimate the cost of strided vector loads (#175135)
For small constant strides, attempt to predict the amount of coalescing
that will be done by the target machine to give a better cost estimate.
Currently, strided loads/stores are costed as having a cost of 1 per
element (i.e. being equivalent to scalar loads/stores).
---------
Co-authored-by: Luke Lau <luke_lau at icloud.com>
Commit: f2b3ba3affb147bf085fd58f1f7261dd32ae91c8
https://github.com/llvm/llvm-project/commit/f2b3ba3affb147bf085fd58f1f7261dd32ae91c8
Author: Sang Ik Lee <sang.ik.lee at intel.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
A mlir/test/Integration/Dialect/XeGPU/WG/simple_gemm_bf16.mlir
R mlir/test/Integration/Dialect/XeGPU/WG/simple_mxfp_gemm.mlir
A mlir/test/Integration/Dialect/XeGPU/WG/simple_mxfp_gemm_F4.mlir
A mlir/test/Integration/Dialect/XeGPU/WG/simple_mxfp_gemm_F8.mlir
M mlir/test/Integration/Dialect/XeGPU/WG/simple_mxfp_gemm_dequantizeB_F4.mlir
A mlir/test/Integration/Dialect/XeGPU/WG/simple_mxfp_gemm_dequantizeB_F8.mlir
M mlir/test/Integration/Dialect/XeGPU/WG/simple_mxfp_gemm_quantizeA_F4.mlir
A mlir/test/Integration/Dialect/XeGPU/WG/simple_mxfp_gemm_quantizeA_F8.mlir
Log Message:
-----------
[MLIR][XeGPU] Add MXFP fp8 WG GEMM tests and use shared input set (#225944)
Adds four workgroup-level tests, updates two and renames one, so that
seven tests covering bf16, mx-fp4 and mx-fp8 exercise the same
arithmetic on the same operand values and check against the same
expected result.
1. simple_mxfp_gemm -> simple_mxfp_gemm_F4 - renamed, for consistency
with the F4/F8 suffixes used by the quantize and dequantize tests
2. (new) simple_gemm_bf16 - non-quantized bf16 GEMM at the MXFP problem
size, as the unquantized comparison point, and where the shared input
set is documented
3. (new) simple_mxfp_gemm_F8 - f8E5M2 operands with f8E8M0FNU scales
4. (new) simple_mxfp_gemm_dequantizeB_F8
5. (new) simple_mxfp_gemm_quantizeA_F8 - fp8 counterparts of the
existing fp4 tests
6. simple_mxfp_gemm_dequantizeB_F4 and simple_mxfp_gemm_quantizeA_F4 are
updated in place.
What the update changes:
* Meaningful operand values. The tests previously used all-ones
operands, which cannot distinguish a correct kernel from one that swaps
the two fp4 values in a byte, misapplies a scale, or mixes up lanes or
tiles. Operands are now drawn from the 8 magnitudes e2m1 can represent -
0, 0.5, 1, 1.5, 2, 3, 4, 6 - indexed by (i + k) % 8 and (j + k) % 8, so
consecutive K values differ and the packing is exercised. Every value is
exact in f4E2M1FN, f8E5M2, bf16 and f32, which is what lets one input
set serve all three formats.
* Non-unit block scales. A carries a per-K-block divisor and B a
per-K-block scale, three of each, all powers of two, cycling per block
of 32. The quantized formats realise the same values through their own
scales, so a scale that is ignored or applied to the wrong block now
changes the result.
* One reference result. Each test computes its expected C with a host
f32 GEMM over f32 shadows of the operands, filled in the same loop that
writes the device operands so the two cannot drift. Every product is a
multiple of 0.25 and the largest result is well under 2^24, so the
accumulation is exact and the comparison is bit-for-bit rather than
approximate.
* A labelled result line. verifyMemRefF32's mismatch count is printed as
"mismatches: <n>" via printString/printI64/printNewline and matched with
{{^mismatches: 0$}}. A bare "0" check is a substring match over all of
stdout, so it passes on any 0 the runtime happens to print, including
one inside a larger number, and cannot distinguish a correct run from a
kernel that never ran.
* A fix for the fp4 A operand in simple_mxfp_gemm_F4.
gpu.alloc/memcpy/dealloc size a memref by rounding the element type up
to a whole byte - the size is lowered as gep(null, numElements) on i4,
which LLVM strides by 1 byte - so a packed fp4 memref is sized at twice
its real footprint. The test allocated A as memref<256x4096xf4E2M1FN>,
giving a 512 KB overread of a 524288-byte host buffer; because
mgpuMemcpy is asynchronous the fault surfaces later, at the stream sync
inside the first mgpuMemFree, so the test passed regardless. A now
crosses as memref<524288xi8> and is viewed as fp4 on the device, which
is what the B operand already does.
All seven follow the existing convention in this directory: the mlir-opt
compile is the active RUN line and the mlir-runner pipeline is kept
behind RUN-DISABLED with a MISMATCH check prefix, so no device is needed
and the compile-only run cannot pick up the result check.
Commit: b3ed324d42c0487e38980f4beddbb67c096f5f3f
https://github.com/llvm/llvm-project/commit/b3ed324d42c0487e38980f4beddbb67c096f5f3f
Author: Keith Smiley <keithbsmiley at gmail.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M lld/test/Unit/lit.cfg.py
M lld/unittests/AsLibELF/CMakeLists.txt
M lld/unittests/AsLibELF/OutputStream.cpp
M lld/unittests/AsLibELF/ROCm.cpp
Log Message:
-----------
[lld][test] Use LLVM helpers for input file discovery (#220404)
This was a suggestion on #220340 to avoid the custom env var handling
and use the `getInputFileDirectory` helper from the LLVM support library
Commit: 07aec21c88f48907b5da1d42f4522e106d30a9f1
https://github.com/llvm/llvm-project/commit/07aec21c88f48907b5da1d42f4522e106d30a9f1
Author: Guo Chen <guochen2 at amd.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.h
M llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/CMakeLists.txt
A llvm/lib/Target/AMDGPU/SIPostRA16BitMovFolding.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/merge-values-s16-true16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/usubsat.ll
M llvm/test/CodeGen/AMDGPU/add.v2i16.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.32bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.48bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.64bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll
M llvm/test/CodeGen/AMDGPU/flat-saddr-load.ll
M llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll
M llvm/test/CodeGen/AMDGPU/llc-pipeline.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.gather4.a16.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.msaa.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.a16.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.g16.encode.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.g16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.waitcnt.out.order.ll
M llvm/test/CodeGen/AMDGPU/mad-mix-hi-bf16.ll
M llvm/test/CodeGen/AMDGPU/repeated-divisor.ll
M llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll
A llvm/test/CodeGen/AMDGPU/si-post-ra-merge-v-mov-b16.mir
M llvm/test/CodeGen/AMDGPU/sub.v2i16.ll
M llvm/test/CodeGen/AMDGPU/v_swap_b16.ll
M llvm/test/CodeGen/AMDGPU/vector_shuffle.packed.ll
Log Message:
-----------
[AMDGPU] merge 16bit mov pairs in post-RA peephole (#208625)
Address https://github.com/llvm/llvm-project/issues/207011. Add 5
patterns to merge 16bit mov pairs.
Since we hoist instruction which might cross the waitcnt boundary,
insert a new pass before waitcnt for this transformation
Co-Authored-By: Claude
Commit: 3621db6aff701dcd9e6ff54ea281d24ee2f43448
https://github.com/llvm/llvm-project/commit/3621db6aff701dcd9e6ff54ea281d24ee2f43448
Author: Akash Manna <akash.manna.mymail at gmail.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M clang/docs/ReleaseNotes.md
M clang/lib/Sema/SemaOpenMP.cpp
A clang/test/OpenMP/for_loop_bitint_messages.c
Log Message:
-----------
[Clang][OpenMP] Fix crash on `_BitInt` loop bounds and counters in loop analysis (#226464)
Fixes #140074
When building the iteration count of an OpenMP loop, Sema derives a few
integer types from bit widths, e.g. to promote the upper bound to an
unsigned type as wide as the wider bound so that `upper - lower` cannot
overflow. Those types came from `ASTContext::getIntTypeForBitwidth`,
which only knows the standard integer widths and returns a null type for
anything else. With a bound or loop counter of type `_BitInt(931)` the
request was for a 960-bit type, the result was null, and it went
straight into `PerformImplicitConversion`, which asserted. The
`collapse(2)` in the reduced reproducer is incidental; a plain `#pragma
omp for` on the same loop crashes the same way.
The loop analysis now goes through a small helper that asks for the
standard type first and otherwise builds the `_BitInt` type of that
width and signedness with `ASTContext::getBitIntType`. It is used at the
three places that derive a type from a loop width: the upper-bound
promotion in `calculateNumIters`, the conversion to the loop variable's
width in `buildNumIterations`, and the logical iteration type in
`ActOnOpenMPCanonicalLoop`. Wide `_BitInt` loop variables are then
narrowed to the runtime's 64-bit iteration variable with the existing
warning, the same as `__int128` today.
Commit: 05f0bf084929c4fdbb5ac2952047ed00cd1d8b57
https://github.com/llvm/llvm-project/commit/05f0bf084929c4fdbb5ac2952047ed00cd1d8b57
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/Target/Mips/MipsSubtarget.cpp
M llvm/lib/Target/Mips/MipsSubtarget.h
Log Message:
-----------
Mips: Remove redundant Triple copy from the subtarget (#226528)
MCSubtargetInfo already stores the target triple, so MipsSubtarget's own
copy is unnecessary.
Co-authored-by: Claude Opus 5 <noreply at anthropic.com>
Commit: 3bcbae4bed67f5cadd9f68d39af47ae5b5af1794
https://github.com/llvm/llvm-project/commit/3bcbae4bed67f5cadd9f68d39af47ae5b5af1794
Author: Alex Langford <alangford at apple.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M lldb/include/lldb/Target/DynamicRegisterInfo.h
M lldb/source/Target/DynamicRegisterInfo.cpp
Log Message:
-----------
[lldb] Introduce DynamicRegisterInfo::RegisterSetWithStorage (#225555)
The RegisterSet struct is created in 2 different ways:
1.) Statically in headers/source files for register sets that are known
ahead of time.
2.) Dynamically according to input from outside of LLDB. Usually this is
through the gdb-remote stub, but may also come from a python script or
by determining an ISA variant's features (e.g. in RISCV).
This PR aims to address the lifetime of strings in RegisterSet. In
scenario (1), the lifetime of all data in a RegisterSet is static and
there is no concern about dangling pointers. However, in scenario (2),
DynamicRegisterInfo maintains a vector of RegisterSets. Until now, it
has relied on ConstString to persist the storage for the strings
indefinitely. As part of my quest to remove ConstString, I am
introducing a new struct wrapping RegisterSet that is responsible for
the storage and lifetime of the underlying RegisterSet strings.
Commit: d220d5e8239db918bd68f404dae589385a8029e8
https://github.com/llvm/llvm-project/commit/d220d5e8239db918bd68f404dae589385a8029e8
Author: Aditya Sinha <155882262+AdityaSinha149 at users.noreply.github.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M clang/include/clang/Interpreter/Interpreter.h
M clang/lib/Interpreter/Interpreter.cpp
A clang/test/Interpreter/HIP/hip-environment.hip
A clang/test/Interpreter/HIP/lit.local.cfg
M clang/test/lit.cfg.py
M clang/tools/clang-repl/ClangRepl.cpp
Log Message:
-----------
[clang-repl] Initialized HIP environment for clang-repl (#217582)
This PR initializes the HIP environment for clang-repl. Since an
IncrementalHipDeviceParser does not exist yet, a message is printed
after the environment setup indicating that the HIP environment was set
up but is not yet supported.
It also adds a test file that runs clang-repl with the -hip option and
checks that this message is printed. Once the parser is built, the
current test file will be removed and replaced with tests that verify
the complete flow.
This PR has a prerequisite, #217228, which skips emitting the
`__hip_cuid_` global under incremental extensions. Without it,
clang-repl's HIP mode would emit the same symbol in every incremental
module and fail at JIT link with a duplicate-symbol error.
Assisted by Claude Opus 4.8
Commit: 0ae27ad06c80796bdae576e27a44b2877e5c2a4f
https://github.com/llvm/llvm-project/commit/0ae27ad06c80796bdae576e27a44b2877e5c2a4f
Author: Gaëtan Bossu <gaetan.bossu at arm.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/test/Analysis/CostModel/AArch64/masked_ldst.ll
M llvm/test/Analysis/CostModel/AArch64/sve-arith.ll
M llvm/test/Analysis/CostModel/AArch64/sve-ldst.ll
M llvm/test/CodeGen/AArch64/sve-int-arith.ll
M llvm/test/Transforms/LoopVectorize/AArch64/force-scalable-vectorization-always.ll
M llvm/test/Transforms/LoopVectorize/AArch64/invalid-costs.ll
M llvm/test/Transforms/LoopVectorize/AArch64/scalable-alloca.ll
M llvm/test/Transforms/LoopVectorize/AArch64/scalable-call.ll
M llvm/test/Transforms/LoopVectorize/AArch64/scalable-vectorization-cost-tuning.ll
Log Message:
-----------
Revert "[AArch64][CostModel] Consider some nxv1 operations as legal" (#226531)
Reverts llvm/llvm-project#214471
This caused a failure in
https://lab.llvm.org/buildbot/#/builders/198/builds/15417 and I want to
spend a bit more time to test the ISel for vector_reverse and
vector_splice. It's also quite surprising that the test picked a VF of
`vscale x 1`
Commit: 9214c04da2ea302b773797f50ad11636c7bab097
https://github.com/llvm/llvm-project/commit/9214c04da2ea302b773797f50ad11636c7bab097
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M clang/lib/CodeGen/CGLoopInfo.cpp
M clang/test/CodeGen/align-loops.c
Log Message:
-----------
clang: Emit llvm.loop.align metadata for -falign-loops (#223147)
Commit: 9dcb4291cea195b9f0941d39540a4f2ccb9ff6bd
https://github.com/llvm/llvm-project/commit/9dcb4291cea195b9f0941d39540a4f2ccb9ff6bd
Author: Charles Zablit <c_zablit at apple.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M lldb/test/API/python_api/value/TestValueAPI.py
Log Message:
-----------
[lldb][test] Skip the sp/rsp check in register sets that have no rsp (#226176)
The test asserts the ABI name `"sp"` resolves to `"rsp"` within the same
register set. However, on Windows the architectural 16-bit `"sp"` lives
in `"supplementary registers"` while `"rsp"` is in `"General Purpose
Registers"`, so there is nothing to compare against.
https://learn.microsoft.com/en-us/windows-hardware/drivers/debugger/x64-architecture
This fixes `python_api/value/TestValueAPI.py` (`test_register`) on
Windows in swiftlang.
Commit: 51ccdfeadcfe29b1d46f978e8582ada109aebb91
https://github.com/llvm/llvm-project/commit/51ccdfeadcfe29b1d46f978e8582ada109aebb91
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M libcxx/test/benchmarks/containers/string.bench.cpp
Log Message:
-----------
[libc++] Add benchmark for string::pop_back() (#223729)
Commit: 68d354f5795682ea1fe03304ac3e7b2a43a36b0d
https://github.com/llvm/llvm-project/commit/68d354f5795682ea1fe03304ac3e7b2a43a36b0d
Author: Jason Van Beusekom <jason.van-beusekom at hpe.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M offload/include/Shared/SourceInfo.h
M openmp/docs/ReleaseNotes.md
Log Message:
-----------
Revert "[Offload][OpenMP] remove SourceInfo::removePath (#226283)" (#226557)
This reverts commit 5b8e65685b4fe99191a217bfa0527c51cf36925c.
In https://github.com/llvm/llvm-project/pull/226283 I forgot to update
info.c to account for the full file paths in its output, will update
commit with fixed test and re open PR
Commit: d92a0c1e5eba51dbf9a4c2a61a709b6758f2e40d
https://github.com/llvm/llvm-project/commit/d92a0c1e5eba51dbf9a4c2a61a709b6758f2e40d
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M mlir/include/mlir/IR/BuiltinDialect.td
M mlir/include/mlir/IR/BuiltinOps.td
M mlir/test/IR/module-op.mlir
M mlir/test/Transforms/sccp-callgraph.mlir
M mlir/test/Transforms/test-symbol-dce.mlir
M mlir/test/python/dialects/ml_program.py
Log Message:
-----------
[MLIR] Enable strict assembly properties for the builtin dialect (#225750)
Commit: 48884d2ddba0718960f68eb01a5b8c42c089f27c
https://github.com/llvm/llvm-project/commit/48884d2ddba0718960f68eb01a5b8c42c089f27c
Author: Cyndy Ishida <cyndy_ishida at apple.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M clang/lib/Lex/HeaderSearch.cpp
A clang/test/ClangScanDeps/modules-context-hash-case-sensitive-vfs-paths.c
M clang/test/ClangScanDeps/modules-context-hash-module-map-path.c
A clang/test/Modules/implicit-module-map-path-case-sensitive.c
Log Message:
-----------
[clang][Modules] Respect case sensitivity when hashing implicit module map path (#226339)
Before this patch, the implicit module hash normalized the module map
path, but explicit modules always respected the case in paths. This
worked by depending on FileEntry caching and/or relocation checking to
resolve correctly. This behavior was both subtle and difficult to
understand. Instead, respect the casing in paths for hashing to match
explicitly built modules so they can never diverge.
This patch also updates `modules-context-hash-module-map-path.c` to
match a downstream version that already tested for the case where vfs
overlay entries differ by case but point to the same file.
`modules-context-hash-case-sensitive-vfs-paths.c` is the same but points
to different underlying files.
Commit: 36e7743d8ec9e743ae66485ddf2a6b27549c8833
https://github.com/llvm/llvm-project/commit/36e7743d8ec9e743ae66485ddf2a6b27549c8833
Author: Anshil Gandhi <95053726+gandhi56 at users.noreply.github.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/Passes/LoadStoreVec.h
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/VecUtils.h
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/Passes/LoadStoreVec.cpp
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/VecUtils.cpp
Log Message:
-----------
[SandboxVec][LoadStoreVec][NFC] Tighten bundle element types (#226348)
Use Instruction*/Constant* for LoadStoreVec APIs where that is what
callers hold, and template getCombinedVectorTypeFor so BndlRef is not
forced through a non-covariant Value* conversion.
Co-authored-by: Cursor <cursoragent at cursor.com>
Commit: 4825f4aa936d7628b9fdf599aba7bf25d8179e52
https://github.com/llvm/llvm-project/commit/4825f4aa936d7628b9fdf599aba7bf25d8179e52
Author: mssefat <syadus.sefat at gmail.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M clang/docs/ReleaseNotes.md
M clang/include/clang/Basic/BuiltinsRISCV.td
M clang/include/clang/CIR/Dialect/IR/CIRAttrs.td
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/include/clang/Interpreter/Interpreter.h
M clang/lib/Basic/Targets/WebAssembly.cpp
M clang/lib/Basic/Targets/WebAssembly.h
M clang/lib/CIR/CodeGen/CIRGenBuilder.h
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
M clang/lib/CodeGen/CGLoopInfo.cpp
M clang/lib/CodeGen/TargetBuiltins/RISCV.cpp
M clang/lib/Headers/riscv_packed_simd.h
M clang/lib/Interpreter/Interpreter.cpp
M clang/lib/Lex/HeaderSearch.cpp
M clang/lib/Sema/SemaOpenMP.cpp
M clang/test/Analysis/Scalable/ssaf-src-edit-merge/conflict-preserves-unrelated-zero-length-insert.test
M clang/test/Analysis/Scalable/ssaf-src-edit-merge/conflict-stderr-without-sarif.test
M clang/test/Analysis/Scalable/ssaf-src-edit-merge/empty-input.test
M clang/test/Analysis/Scalable/ssaf-src-edit-merge/identical-overlap.test
M clang/test/Analysis/Scalable/ssaf-src-edit-merge/no-conflict-sarif-empty.test
M clang/test/Analysis/Scalable/ssaf-src-edit-merge/non-overlapping.test
M clang/test/Analysis/Scalable/ssaf-src-edit-merge/order-invariance.test
M clang/test/Analysis/Scalable/ssaf-src-edit-merge/parent-dir-missing.test
M clang/test/Analysis/Scalable/ssaf-src-edit-merge/pre-dedup-identical-non-zero-length.test
M clang/test/Analysis/Scalable/ssaf-src-edit-merge/pre-dedup-zero-length-insert.test
M clang/test/Analysis/Scalable/ssaf-src-edit-merge/range-overlap-cluster-of-three-sarif.test
M clang/test/Analysis/Scalable/ssaf-src-edit-merge/range-overlap-conflict-sarif.test
M clang/test/Analysis/Scalable/ssaf-src-edit-merge/sarif-out-parent-dir-missing.test
M clang/test/Analysis/Scalable/ssaf-src-edit-merge/single-input-internal-conflict.test
M clang/test/Analysis/Scalable/ssaf-src-edit-merge/single-input.test
M clang/test/Analysis/Scalable/ssaf-src-edit-merge/three-input-all-conflict.test
M clang/test/Analysis/Scalable/ssaf-src-edit-merge/three-input-conflict-sarif.test
M clang/test/Analysis/Scalable/ssaf-src-edit-merge/two-conflicts-different-offsets-sarif.test
M clang/test/Analysis/Scalable/ssaf-src-edit-merge/two-input-conflict-sarif.test
M clang/test/Analysis/Scalable/ssaf-src-edit-merge/two-input-conflict.test
M clang/test/CIR/IR/enum-attrs.cir
M clang/test/CIR/Lowering/call-llvm-intrinsic.cir
A clang/test/ClangScanDeps/modules-context-hash-case-sensitive-vfs-paths.c
M clang/test/ClangScanDeps/modules-context-hash-module-map-path.c
M clang/test/CodeGen/RISCV/rvp-intrinsics.c
M clang/test/CodeGen/align-loops.c
M clang/test/CodeGen/thread-model.c
M clang/test/CodeGenCXX/static-init-wasm.cpp
A clang/test/Interpreter/HIP/hip-environment.hip
A clang/test/Interpreter/HIP/lit.local.cfg
A clang/test/Modules/implicit-module-map-path-case-sensitive.c
A clang/test/OpenMP/for_loop_bitint_messages.c
M clang/test/Preprocessor/init.c
M clang/test/lit.cfg.py
M clang/tools/clang-repl/ClangRepl.cpp
M clang/unittests/Lex/LexerTest.cpp
M libc/src/__support/math/bf16sub.h
M libc/src/__support/math/bf16subf.h
M libc/src/__support/math/bf16subf128.h
M libc/test/shared/shared_math_constexpr_test.cpp
M libcxx/test/benchmarks/containers/string.bench.cpp
M lld/test/Unit/lit.cfg.py
M lld/unittests/AsLibELF/CMakeLists.txt
M lld/unittests/AsLibELF/OutputStream.cpp
M lld/unittests/AsLibELF/ROCm.cpp
M lldb/include/lldb/Target/DynamicRegisterInfo.h
M lldb/packages/Python/lldbsuite/test/tools/lldb_dap/session_helpers.py
M lldb/source/Target/DynamicRegisterInfo.cpp
M lldb/test/API/python_api/value/TestValueAPI.py
M lldb/tools/lldb-dap/Handler/ThreadsRequestHandler.cpp
M llvm/docs/LangRef.md
M llvm/docs/ReleaseNotes.md
M llvm/include/llvm-c/Core.h
M llvm/include/llvm/Analysis/InstSimplifyFolder.h
M llvm/include/llvm/Analysis/TargetFolder.h
M llvm/include/llvm/Analysis/TargetTransformInfo.h
M llvm/include/llvm/AsmParser/LLParser.h
M llvm/include/llvm/AsmParser/LLToken.h
M llvm/include/llvm/Bitcode/LLVMBitCodes.h
M llvm/include/llvm/CodeGen/BasicTTIImpl.h
M llvm/include/llvm/IR/ConstantFolder.h
M llvm/include/llvm/IR/IRBuilder.h
M llvm/include/llvm/IR/IRBuilderFolder.h
M llvm/include/llvm/IR/InstVisitor.h
M llvm/include/llvm/IR/Instruction.def
M llvm/include/llvm/IR/Instructions.h
M llvm/include/llvm/IR/IntrinsicsRISCV.td
M llvm/include/llvm/IR/NoFolder.h
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/Passes/LoadStoreVec.h
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/VecUtils.h
M llvm/lib/AsmParser/LLLexer.cpp
M llvm/lib/AsmParser/LLParser.cpp
M llvm/lib/Bitcode/Reader/BitcodeReader.cpp
M llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
M llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h
M llvm/lib/CodeGen/TargetLoweringBase.cpp
M llvm/lib/IR/AsmWriter.cpp
M llvm/lib/IR/Core.cpp
M llvm/lib/IR/Instruction.cpp
M llvm/lib/IR/Instructions.cpp
M llvm/lib/IR/Verifier.cpp
M llvm/lib/MC/GOFFObjectWriter.cpp
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPU.h
M llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/CMakeLists.txt
A llvm/lib/Target/AMDGPU/SIPostRA16BitMovFolding.cpp
M llvm/lib/Target/Mips/MipsSubtarget.cpp
M llvm/lib/Target/Mips/MipsSubtarget.h
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoP.td
M llvm/lib/Target/RISCV/RISCVProcessors.td
M llvm/lib/Target/RISCV/RISCVSubtarget.h
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyCoalesceFeaturesAndStripAtomics.cpp
M llvm/lib/TargetParser/Triple.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/Passes/LoadStoreVec.cpp
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/VecUtils.cpp
M llvm/test/Analysis/CostModel/AArch64/masked_ldst.ll
M llvm/test/Analysis/CostModel/AArch64/sve-arith.ll
M llvm/test/Analysis/CostModel/AArch64/sve-ldst.ll
M llvm/test/Analysis/CostModel/RISCV/vp-intrinsics.ll
M llvm/test/Analysis/IR2Vec/Inputs/reference_default_vocab_print.txt
M llvm/test/Analysis/IR2Vec/Inputs/reference_wtd1_vocab_print.txt
M llvm/test/Analysis/IR2Vec/Inputs/reference_wtd2_vocab_print.txt
A llvm/test/Assembler/bitinsert-bitextract-invalid.ll
A llvm/test/Assembler/bitinsert-bitextract.ll
M llvm/test/Bitcode/compatibility.ll
A llvm/test/CodeGen/AArch64/bitinsert-bitextract-common-offsets.ll
A llvm/test/CodeGen/AArch64/bitinsert-bitextract-fp.ll
A llvm/test/CodeGen/AArch64/bitinsert-bitextract.ll
M llvm/test/CodeGen/AArch64/sve-int-arith.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/merge-values-s16-true16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/usubsat.ll
M llvm/test/CodeGen/AMDGPU/add.v2i16.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.32bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.48bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.64bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll
A llvm/test/CodeGen/AMDGPU/bitinsert-bitextract-common-offsets.ll
A llvm/test/CodeGen/AMDGPU/bitinsert-bitextract-fp.ll
A llvm/test/CodeGen/AMDGPU/bitinsert-bitextract.ll
M llvm/test/CodeGen/AMDGPU/flat-saddr-load.ll
M llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll
M llvm/test/CodeGen/AMDGPU/llc-pipeline.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.gather4.a16.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.msaa.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.a16.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.g16.encode.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.g16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.waitcnt.out.order.ll
M llvm/test/CodeGen/AMDGPU/mad-mix-hi-bf16.ll
M llvm/test/CodeGen/AMDGPU/repeated-divisor.ll
M llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll
A llvm/test/CodeGen/AMDGPU/si-post-ra-merge-v-mov-b16.mir
M llvm/test/CodeGen/AMDGPU/sub.v2i16.ll
M llvm/test/CodeGen/AMDGPU/v_swap_b16.ll
M llvm/test/CodeGen/AMDGPU/vector_shuffle.packed.ll
A llvm/test/CodeGen/ARM/bitinsert-bitextract-common-offsets.ll
A llvm/test/CodeGen/ARM/bitinsert-bitextract-fp.ll
A llvm/test/CodeGen/ARM/bitinsert-bitextract.ll
A llvm/test/CodeGen/PowerPC/bitinsert-bitextract-common-offsets.ll
A llvm/test/CodeGen/PowerPC/bitinsert-bitextract-fp.ll
A llvm/test/CodeGen/PowerPC/bitinsert-bitextract.ll
A llvm/test/CodeGen/RISCV/bitinsert-bitextract-common-offsets.ll
A llvm/test/CodeGen/RISCV/bitinsert-bitextract-fp.ll
A llvm/test/CodeGen/RISCV/bitinsert-bitextract.ll
M llvm/test/CodeGen/RISCV/rvp-simd-32.ll
M llvm/test/CodeGen/RISCV/rvp-simd-64.ll
M llvm/test/CodeGen/SystemZ/zos-section-1.ll
M llvm/test/CodeGen/SystemZ/zos-section-2.ll
M llvm/test/CodeGen/SystemZ/zos-symbol-2.ll
R llvm/test/CodeGen/WebAssembly/coalesce-features-thread-model.ll
A llvm/test/CodeGen/X86/GlobalISel/bitinsert-bitextract.ll
A llvm/test/CodeGen/X86/bitinsert-bitextract-common-offsets.ll
A llvm/test/CodeGen/X86/bitinsert-bitextract-fp.ll
A llvm/test/CodeGen/X86/bitinsert-bitextract.ll
M llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-vmax.ll
M llvm/test/Transforms/LoopVectorize/AArch64/force-scalable-vectorization-always.ll
M llvm/test/Transforms/LoopVectorize/AArch64/invalid-costs.ll
M llvm/test/Transforms/LoopVectorize/AArch64/scalable-alloca.ll
M llvm/test/Transforms/LoopVectorize/AArch64/scalable-call.ll
M llvm/test/Transforms/LoopVectorize/AArch64/scalable-vectorization-cost-tuning.ll
M llvm/test/Transforms/LoopVectorize/early-exit-live-out-extract-lane.ll
R llvm/test/Transforms/PGOProfile/Inputs/indirect_call.proftext
M llvm/test/Transforms/PGOProfile/indirect_call_annotation.ll
A llvm/test/Verifier/bitextract-bitinsert-invalid-verifier.ll
M llvm/test/tools/llvm-ir2vec/entities.ll
M llvm/test/tools/llvm-ir2vec/triplets.ll
M llvm/tools/llvm-c-test/echo.cpp
M llvm/unittests/Analysis/IR2VecTest.cpp
M mlir/include/mlir-c/Rewrite.h
M mlir/include/mlir/IR/BuiltinDialect.td
M mlir/include/mlir/IR/BuiltinOps.td
M mlir/lib/CAPI/Transforms/Rewrite.cpp
M mlir/test/CAPI/CMakeLists.txt
M mlir/test/CAPI/rewrite.c
M mlir/test/IR/module-op.mlir
A mlir/test/Integration/Dialect/XeGPU/WG/simple_gemm_bf16.mlir
R mlir/test/Integration/Dialect/XeGPU/WG/simple_mxfp_gemm.mlir
A mlir/test/Integration/Dialect/XeGPU/WG/simple_mxfp_gemm_F4.mlir
A mlir/test/Integration/Dialect/XeGPU/WG/simple_mxfp_gemm_F8.mlir
M mlir/test/Integration/Dialect/XeGPU/WG/simple_mxfp_gemm_dequantizeB_F4.mlir
A mlir/test/Integration/Dialect/XeGPU/WG/simple_mxfp_gemm_dequantizeB_F8.mlir
M mlir/test/Integration/Dialect/XeGPU/WG/simple_mxfp_gemm_quantizeA_F4.mlir
A mlir/test/Integration/Dialect/XeGPU/WG/simple_mxfp_gemm_quantizeA_F8.mlir
M mlir/test/Transforms/sccp-callgraph.mlir
M mlir/test/Transforms/test-symbol-dce.mlir
M mlir/test/python/dialects/ml_program.py
M utils/bazel/llvm-project-overlay/lldb/BUILD.bazel
Log Message:
-----------
Merge remote-tracking branch 'upstream/main' into users/mssefat/anti-hints-pr4-amdgpu-pre-ra
Compare: https://github.com/llvm/llvm-project/compare/628e294dbb6e...4825f4aa936d
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