[all-commits] [llvm/llvm-project] 201e76: [CodeGen] Fix DetectDeadLanes for same-class copie...

[Changpeng Fang via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 201e76d4559e9d8acdfec1c202df8f2269acbd8b
      https://github.com/llvm/llvm-project/commit/201e76d4559e9d8acdfec1c202df8f2269acbd8b
  Author: Changpeng Fang <changpeng.fang at amd.com>
  Date:   2026-09-25 (Fri, 25 Sep 2026)

  Changed paths:
    M llvm/lib/CodeGen/DetectDeadLanes.cpp
    A llvm/test/CodeGen/AMDGPU/detect-dead-lanes-reg-sequence-narrow-slot.mir
    M llvm/test/CodeGen/AMDGPU/frem.ll
    A llvm/test/CodeGen/AMDGPU/true16-uniform-f16-phi-copysign.ll

  Log Message:
  -----------
  [CodeGen] Fix DetectDeadLanes for same-class copies with mismatched widths (#226556)

isCrossCopy() returned early whenever source and destination shared a
register class, treating the transfer as lane-for-lane. That is wrong
when a REG_SEQUENCE names a subregister slot narrower than the source
operand, e.g. a 32-bit vreg used as the lo16 piece of another 32-bit
vreg. Only take the early exit when the two widths match; otherwise fall
through to findCommonRegClass().

Fixes: ROCM-31212



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