[all-commits] [llvm/llvm-project] f739fb: [LV] Honor -force-vector-interleave when generatin...

[Benjamin Maxwell via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: f739fbc831cbd670b9dc3044a492240cfede20c3
      https://github.com/llvm/llvm-project/commit/f739fbc831cbd670b9dc3044a492240cfede20c3
  Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
  Date:   2026-09-26 (Sat, 26 Sep 2026)

  Changed paths:
    M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
    A llvm/test/Transforms/LoopVectorize/AArch64/diff-checks-force-interleave-count.ll

  Log Message:
  -----------
  [LV] Honor -force-vector-interleave when generating diff checks  (#225768)

We use both IC and UserIC in the checks below. However, once those
checks are done, UserIC will always override IC if it's non-zero. That
means using the max is unnecessary and can result in overly conservative
checks when UserIC < IC.



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