[all-commits] [llvm/llvm-project] 57e112: RuntimeLibcalls: Describe register-returning divmo...
Alexey Bataev via All-commits
all-commits at lists.llvm.org
Fri Sep 25 14:23:53 PDT 2026
Branch: refs/heads/users/alexey-bataev/spr/slpnfcbroader-use-of-filterisa-ranges
Home: https://github.com/llvm/llvm-project
Commit: 57e112ccb2a509c0e1d36963b187fccdd59566de
https://github.com/llvm/llvm-project/commit/57e112ccb2a509c0e1d36963b187fccdd59566de
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/IR/RuntimeLibcalls.cpp
A llvm/test/Transforms/Util/DeclareRuntimeLibcalls/divmod.ll
Log Message:
-----------
RuntimeLibcalls: Describe register-returning divmod libcall ABIs (#217825)
Teach RuntimeLibcallsInfo::getFunctionTy about the ARM AEABI
(__aeabi_*divmod) and Windows (__rt_*div*) divmod signatures. Currently
the custom lowering to these calls hardcodes the call signature
information, but in the future this should be automatically handled.
Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
Commit: 2fe83ee7dc5bb40e2f15e164c21a01bec01c1792
https://github.com/llvm/llvm-project/commit/2fe83ee7dc5bb40e2f15e164c21a01bec01c1792
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/Target/SystemZ/SystemZFrameLowering.cpp
M llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
M llvm/test/CodeGen/SystemZ/atomicrmw-fadd-04.ll
M llvm/test/CodeGen/SystemZ/cmpxchg-01.ll
M llvm/test/CodeGen/SystemZ/cmpxchg-02.ll
A llvm/test/CodeGen/SystemZ/dead-cc-defs.ll
Log Message:
-----------
SystemZ: Mark unread CC defs dead at build time (#226434)
The custom inserters for the subword atomic pseudos and for probed
allocas, plus the inline stack probe emitted by frame lowering, build
instructions whose CC def is never read. Set the dead flags.
Marking the RISBG32 in the subword cmpxchg loop dead lets MachineSink
move it out of the compare block and into the store block, so it is
skipped when the comparison fails.
Co-authored-by: Claude Opus 5 <noreply at anthropic.com>
Commit: 4e50049d9d5b44028c9cca9763f6ceeda1c667fb
https://github.com/llvm/llvm-project/commit/4e50049d9d5b44028c9cca9763f6ceeda1c667fb
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-phis-no-lane-mask-merging.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-used-outside-loop.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-structurizer.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-i1.ll
M llvm/test/CodeGen/AMDGPU/block-should-not-be-in-alive-blocks.mir
M llvm/test/CodeGen/AMDGPU/branch-folding-implicit-def-subreg.ll
M llvm/test/CodeGen/AMDGPU/collapse-endcf.mir
M llvm/test/CodeGen/AMDGPU/divergent-branch-uniform-condition.ll
M llvm/test/CodeGen/AMDGPU/i1-copy-from-loop.ll
M llvm/test/CodeGen/AMDGPU/insert-waitcnts-merge.ll
M llvm/test/CodeGen/AMDGPU/loop_break.ll
M llvm/test/CodeGen/AMDGPU/lower-control-flow-live-intervals.mir
M llvm/test/CodeGen/AMDGPU/lower-control-flow-live-variables-update.mir
M llvm/test/CodeGen/AMDGPU/lower-control-flow-other-terminators.mir
M llvm/test/CodeGen/AMDGPU/sgpr-scavenge-fi-stack-id.ll
M llvm/test/CodeGen/AMDGPU/si-lower-control-flow-remove-redundant-block-liveintervals.mir
M llvm/test/CodeGen/AMDGPU/si-lower-control-flow.mir
M llvm/test/CodeGen/AMDGPU/transform-block-with-return-to-epilog.ll
Log Message:
-----------
AMDGPU: Mark the SCC def dead when expanding CF pseudos (#226249)
The control flow pseudos start with dead flags on the implicit scc def,
but did not transfer to the replacement instruction
Co-Authored-By: Claude Opus 5 <noreply at anthropic.com>
Commit: 319529bbe0ef99a5262fef91317e1327fa1e8453
https://github.com/llvm/llvm-project/commit/319529bbe0ef99a5262fef91317e1327fa1e8453
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/test/CodeGen/AMDGPU/add_sub_u64_pseudos.mir
Log Message:
-----------
AMDGPU: Mark the SCC def dead when expanding 64-bit scalar add/sub (#226269)
Co-authored-by: Claude Opus 5 <noreply at anthropic.com>
Commit: 01b8b4dfc99e46273b9811cb4663a90c2fb61676
https://github.com/llvm/llvm-project/commit/01b8b4dfc99e46273b9811cb4663a90c2fb61676
Author: Gaëtan Bossu <gaetan.bossu at arm.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
Log Message:
-----------
[AArch64] Remove variable only used in assert (#226433)
This caused a buildbot failure after the variable was introduced in #208212
Commit: 0e7fb8bcf11a59d564bf45d0568d528bf1e9bdcf
https://github.com/llvm/llvm-project/commit/0e7fb8bcf11a59d564bf45d0568d528bf1e9bdcf
Author: Dhairyashil R G <dhairyashil25 at gmail.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M mlir/include/mlir/Dialect/Vector/Transforms/VectorTransforms.h
M mlir/lib/Dialect/Vector/Transforms/VectorMaskElimination.cpp
M mlir/test/Dialect/Vector/eliminate-masks.mlir
M mlir/test/lib/Dialect/Vector/TestVectorTransforms.cpp
Log Message:
-----------
[mlir][vector] Support fixed-size masks in `eliminateVectorMasks` (#221595)
`eliminateVectorMasks` returned immediately unless a `VscaleRange` was
supplied. The TODO above that early return argued the fixed-size case
was unlikely to be useful, because "for fixed-size code dimensions are
all static so masks tend to fold away".
That is only true when the mask operand is constant. When it comes from
an induction variable, which is what tiling produces, the operand is not
constant and no fold removes the mask, even though value-bounds analysis
can prove it all-true. For example, `-canonicalize` leaves this alone:
```mlir
scf.for %i = %c0 to %c1024 step %c4 {
%rem = arith.subi %c1024, %i : index
%mask = vector.create_mask %rem : vector<4xi1>
%v = vector.transfer_read %t[%i], %f0, %mask : tensor<1024xf32>, vector<4xf32>
...
}
```
`%i <= 1020`, so `%rem >= 4` and the mask is all-true.
The algorithm was never scalable-specific; only the bound query was.
This makes `vscaleRange` genuinely optional: without one, the lower
bound is computed with `ValueBoundsConstraintSet::computeConstantBound`
and compared against the mask dimension. Scalable dimensions still need
a range and bail without one, so a fixed-size caller cannot prove a
dimension whose runtime size is `vscale` times the size in the type. The
scalable path is unchanged, and the existing test still passes with its
RUN line untouched.
### Behaviour change for downstream callers
An omitted `vscaleRange` used to make the call a no-op. It now runs the
fixed-size analysis.
No in-tree caller relies on the old meaning, but IREE does call this
unconditionally in `Codegen/Common/GenericVectorization.cpp`, passing
`getDefaultVscaleRange()`, which returns `std::nullopt` for every target
other than AArch64+SVE. For those targets this patch turns a no-op into
live mask elimination. That is the intended benefit, but it is worth
knowing before the next integrate. The added cost is bounded: constant
and `vscale`-multiple operands short-circuit before any analysis, so
only `create_mask` ops with unknown operands pay for a bound query.
### Tests
New `eliminate-masks-fixed-size.mlir`, run through a `fixed-size` option
added to the test pass: two cases that are eliminated (the tiled loop
above, and a dynamic operand bounded by `arith.maxsi`) and three that
are not (an unbounded operand, a lower bound smaller than the mask
dimension, and a scalable dimension with no vscale range). Each negative
was checked to fail for the stated reason, by making the smallest change
that flips it.
Context:
https://discourse.llvm.org/t/rfc-should-vector-transfer-read-write-keep-in-bounds-measurements-on-the-masking-alternative/91649
Assisted-by: Claude
Commit: 675c1cfa5d925232db882942674a40de41654bc5
https://github.com/llvm/llvm-project/commit/675c1cfa5d925232db882942674a40de41654bc5
Author: Paul Walker <paul.walker at arm.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64PTrueCoalescing.cpp
M llvm/test/CodeGen/AArch64/insert-subvector-res-legalization.ll
M llvm/test/CodeGen/AArch64/llvm-ir-to-intrinsic.ll
M llvm/test/CodeGen/AArch64/masked-srem-scalable.ll
M llvm/test/CodeGen/AArch64/masked-urem-scalable.ll
M llvm/test/CodeGen/AArch64/sve-bf16-combines.ll
M llvm/test/CodeGen/AArch64/sve-bf16-int-converts.ll
M llvm/test/CodeGen/AArch64/sve-bitcast.ll
M llvm/test/CodeGen/AArch64/sve-fpext-load.ll
M llvm/test/CodeGen/AArch64/sve-ld1-addressing-mode-reg-imm.ll
M llvm/test/CodeGen/AArch64/sve-load-store-legalisation.ll
M llvm/test/CodeGen/AArch64/sve-lsrchain.ll
M llvm/test/CodeGen/AArch64/sve-partial-reduce-dot-product.ll
M llvm/test/CodeGen/AArch64/sve-partial-reduce-wide-add.ll
M llvm/test/CodeGen/AArch64/sve-pred-selectop2.ll
M llvm/test/CodeGen/AArch64/sve-shift-trunc-combine.ll
M llvm/test/CodeGen/AArch64/sve-st1-addressing-mode-reg-imm.ll
M llvm/test/CodeGen/AArch64/vec-combine-compare-to-bitmask.ll
M llvm/test/CodeGen/AArch64/vector-absolute-difference.ll
M llvm/test/Transforms/LoopStrengthReduce/AArch64/vscale-fixups.ll
Log Message:
-----------
[LLVM][CodeGen] Enable the AArch64PTrueCoalescing pass. (#225830)
Fixes https://github.com/llvm/llvm-project/issues/137040
Commit: 68a9cd31fd277f9f6b8a8ab95e18d00a786e7c12
https://github.com/llvm/llvm-project/commit/68a9cd31fd277f9f6b8a8ab95e18d00a786e7c12
Author: Timur Baidusenov <timurbaidusenov at gmail.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M polly/lib/Analysis/ScopBuilder.cpp
A polly/test/ScopInfo/user-assumption-cached-precondition.ll
Log Message:
-----------
[Polly] Detect preconditions of cached user assumption translations (#226204)
`addUserAssumptions` detected preconditions of a user assumption by
checking whether building its condition recorded new assumptions, but
`SCEVAffinator` caches translated expressions, so a precondition shared
with an earlier assumption (e.g. the same truncation) was missed and the
assumption went into the context, removing the runtime check it relied
on. For example, with `__builtin_assume((signed char)n >= 0)` and
`__builtin_assume((signed char)n < 10)`, the `n >= 128` check was
dropped, although `n = 261` satisfies both assumptions. Instead, check
the invalid domain of each assumption, which is also cached, and if it
is non-empty, add the assumption to the defined behavior context as in
#189350.
Assisted-by: Claude (Anthropic)
Commit: 940105295f88426cb85b01b075f44f36a90c12fd
https://github.com/llvm/llvm-project/commit/940105295f88426cb85b01b075f44f36a90c12fd
Author: Sergey Semenov <sergey.semenov at intel.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M .github/workflows/sycl-tests.yml
Log Message:
-----------
[CI][libsycl] Enable -Werror in libsycl precommit testing (#226129)
Commit: 952fa726ae35661f86ea92ed989d0efa36e69c7f
https://github.com/llvm/llvm-project/commit/952fa726ae35661f86ea92ed989d0efa36e69c7f
Author: Andrzej Warzyński <andrzej.warzynski at arm.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
R clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_len.c
M clang/test/CodeGen/AArch64/sve/len.c
Log Message:
-----------
[clang][AArch64] Consolidate codegen tests for SVE's LEN intrinsics (#226131)
This patch completes the migration of the tests from:
* clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_len.c
to:
* clang/test/CodeGen/AArch64/sve/len.c
`len.c` covers all the cases previously tested by `acle_sve_len.c`.
However, unlike `acle_sve_dup.c`, it was only tested as C. Add `-x c++`
RUN lines to provide the equivalent C++ coverage, including lowering
via CIR.
Commit: f1c5f1e98cac5bf9d688272f2137da992ab005da
https://github.com/llvm/llvm-project/commit/f1c5f1e98cac5bf9d688272f2137da992ab005da
Author: Lang Hames <lhames at gmail.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M orc-rt/include/orc-rt/bedrock/BootstrapInfo.h
M orc-rt/lib/bedrock/BootstrapInfo.cpp
Log Message:
-----------
[orc-rt] Make BootstrapInfo construction noexcept. (#226459)
These methods should never throw.
Commit: df26d549b9115ff7c32b6fb9031250994d0f3515
https://github.com/llvm/llvm-project/commit/df26d549b9115ff7c32b6fb9031250994d0f3515
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/lib/Target/ARM/ARMISelLowering.cpp
Log Message:
-----------
ARM: Use divmod type signatures from RuntimeLibcallsInfo (#217869)
Start moving towards an API to emit calls from RuntimeLibcallsInfo's
knowledge about the type signature of a function instead of manually
computing an IR type from the EVT of the operation.
Also change the swap of arguments to be based on the libcall impl,
rather than the ABI since it's logically a property of the function
itself.
Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
Commit: dcdeeebef2ef008326211b661cfb81d1d35b4086
https://github.com/llvm/llvm-project/commit/dcdeeebef2ef008326211b661cfb81d1d35b4086
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/test/CodeGen/LoongArch/pr177863.ll
A llvm/test/CodeGen/X86/vec_setcc-3.ll
Log Message:
-----------
[DAG] SimplifySetCC - adjust setcc result type when peeking through truncates (#226422)
For the "(setcc (trunc x) (trunc y)) -> (setcc x y)" fold with non vXi1
cmp result type, make sure we adjust the type and then trunc/extend it
correctly using BooleanContent.
Fixes #226365
Commit: a509a4e98a50a2acc172a5f6eba77b8df020e3cd
https://github.com/llvm/llvm-project/commit/a509a4e98a50a2acc172a5f6eba77b8df020e3cd
Author: Benedek Kaibas <82393336+benedekaibas at users.noreply.github.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M clang/docs/LifetimeSafety.md
M clang/docs/ReleaseNotes.md
M clang/include/clang/Basic/LangOptions.def
M clang/include/clang/Options/Options.td
M clang/lib/Driver/ToolChains/Clang.cpp
A clang/test/Driver/flifetime-safety-c.c
M clang/test/Sema/LifetimeSafety/annotation-suggestions-fixits.c
M clang/test/Sema/LifetimeSafety/safety-c.c
Log Message:
-----------
[LifetimeSafety] Enable C support by default under -Wlifetime-safety (#224028)
This PR extends the lifetime safety analysis to C. When the analysis is
enabled with `-Wlifetime-safety`, it now also runs on C code without the
extra `-fexperimental-lifetime-safety-c` flag.
I have renamed `-fexperimental-lifetime-safety-c` to
`-flifetime-safety-c` since it is on by default from now on. The
`-fno-lifetime-safety-c` flag disables the analysis for C. I have
updated the documentation and the release notes and rewrote the RUN
lines of the test cases that used the old flag.
Commit: b60afea0d31f4da34b9d867a00817a0e53dbdb05
https://github.com/llvm/llvm-project/commit/b60afea0d31f4da34b9d867a00817a0e53dbdb05
Author: Akash Manna <akash.manna.mymail at gmail.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Utils/SimplifyCFG.cpp
A llvm/test/Transforms/SimplifyCFG/fold-branch-to-common-dest-call-debugloc.ll
Log Message:
-----------
[SimplifyCFG] Keep a debug location on calls cloned by `FoldBranchToCommonDest` (#224247)
Fixes #220848
When folding a branch to a common destination, SimplifyCFG clones the
bonus instructions into the predecessor and resets their debug
locations, so the debugger doesn't step onto code from a branch that
wasn't taken. It did that with `setDebugLoc(DebugLoc::getDropped())` for
every instruction. That's fine for an `icmp`, but with
`-bonus-inst-threshold=2` a `speculatable` call can be a bonus
instruction too, and an inlinable call in a function with debug info
must have a `!dbg` location, otherwise the inliner can't set up the
inlined-at scope. The verifier rejects the module with "inlinable
function call in a function with debug info must have a !dbg location".
The clone now uses `Instruction::dropLocation()`, which is what
`speculativelyExecuteBB` in the same file already does. Non-call
instructions still lose their location as before, while calls get a line
0 location in the function's scope, so nothing misleading shows up when
stepping and the IR stays valid. `dropLocation()` needs the parent
function, so the clone is inserted into the predecessor before its
location is updated. An earlier attempt at this swap (674f57870f4c) was
reverted after buildbot crashes; the clone was still unparented when
`dropLocation()` ran there, which would explain them.
Commit: eae3e9e64de82ae5a162783808c89521cfea7742
https://github.com/llvm/llvm-project/commit/eae3e9e64de82ae5a162783808c89521cfea7742
Author: Lang Hames <lhames at gmail.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M orc-rt/include/orc-rt/support/move_only_function.h
M orc-rt/test/unit/support/move_only_function-test.cpp
Log Message:
-----------
[orc-rt] Fix move_only_function storing references to lvalue callables. (#226474)
move_only_function's converting constructor instantiated CallableImpl
with the deduced forwarding-reference type, so constructing from an
lvalue callable stored a reference to it rather than a copy, leaving the
move_only_function dangling once the original went out of scope.
This commit decays the callable type before instantiating CallableImpl,
and adds a static_assert to CallableImpl to enforce that it's only
instantiated with decayed types.
Commit: 176a24691b1b315cfd0f15ee8bb8adcc086683be
https://github.com/llvm/llvm-project/commit/176a24691b1b315cfd0f15ee8bb8adcc086683be
Author: George Burgess IV <george.burgess.iv at gmail.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M clang/docs/SourceBasedCodeCoverage.md
M compiler-rt/include/profile/instr_prof_interface.h
M compiler-rt/lib/profile/InstrProfiling.h
M compiler-rt/test/profile/instrprof-api.c
Log Message:
-----------
[docs][clang] Document additional public profile runtime APIs (#224424)
Android's code coverage runtime started using these functions recently,
and I noticed they were undocumented (and the reviewer highlighted
that `instr_prof_interface.h` exists).
So this commit:
- Moves their declarations to that header
- Updates `SourceBasedCodeCoverage.md` to highlight that header
- Adds quips to said `.md` file for these functions
An LLM was used to take a first pass at this; I reviewed and refined.
Commit: 8de4cb45931adab063265b565408ff2b72be668d
https://github.com/llvm/llvm-project/commit/8de4cb45931adab063265b565408ff2b72be668d
Author: Lang Hames <lhames at gmail.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M orc-rt/test/unit/support/move_only_function-test.cpp
Log Message:
-----------
[orc-rt] Tighten move_only_function ShouldCopyInitialize test. (#226483)
ShouldCopyInitialize only checked that constructing a move_only_function
from an lvalue didn't move the callable, so it passed when the callable
was held by reference and never copied at all.
This commit replaces the moved flag with copy and move counters, and
checks that construction performs exactly one copy and no moves.
Commit: 83589c854329a8366672f9932ee27b422902038f
https://github.com/llvm/llvm-project/commit/83589c854329a8366672f9932ee27b422902038f
Author: google-yfyang <yfyang at google.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
Log Message:
-----------
Fix Bazel build for 0a0e0fa (#226489)
Buildkite error link:
https://buildkite.com/llvm-project/upstream-bazel/builds?commit=0a0e0fa181cf162bcc93be85abf2b1b911027e73
Co-authored-by: Google Bazel Bot <google-bazel-bot at google.com>
Commit: 84d75c8ab6eb610cde0048458f96085f923fc392
https://github.com/llvm/llvm-project/commit/84d75c8ab6eb610cde0048458f96085f923fc392
Author: Nico Weber <thakis at chromium.org>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/TargetParser/AArch64TargetParser.cpp
Log Message:
-----------
[AArch64] Make compiling arm_neon.h faster (#226378)
Replace two linear scans with map lookups.
On my system, reduces time to compile a TU that does nothing but
`#include <arm_neon.h>` from 92.0 ms ± 1.4 ms to 70.9 ms ± 1.3 ms.
No behavior change.
Commit: f2f70fc15fca532f4968ba211e430e269dd18489
https://github.com/llvm/llvm-project/commit/f2f70fc15fca532f4968ba211e430e269dd18489
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
A llvm/test/tools/llubi/main_declaration.ll
M llvm/tools/llubi/llubi.cpp
Log Message:
-----------
[llubi] Error if main is not a definition (#226475)
Currently this crashes. Ran into this while using llubi with
llvm-reduce.
Commit: 2dc2a1f1b94f1953f0ef52bd748fb1f0c07cd780
https://github.com/llvm/llvm-project/commit/2dc2a1f1b94f1953f0ef52bd748fb1f0c07cd780
Author: Anonmiraj <ezzibrahimx at gmail.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M libc/src/__support/math/lgammaf.h
Log Message:
-----------
[libc][math] Fix lgammaf 1-ULP errors in non-FMA builds (#225449)
There were some inaccuracies in the non-FMA builds.
I retested exhaustively with FMA both enabled and disabled, and all
tests seems to pass noww.
Commit: e1dc804fcc352b841e798efe0aa4a6c40ba1f2b3
https://github.com/llvm/llvm-project/commit/e1dc804fcc352b841e798efe0aa4a6c40ba1f2b3
Author: Nico Weber <thakis at chromium.org>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/test/tools/llvm-objdump/MachO/AArch64/macho-arm64-subtypes.test
M llvm/test/tools/llvm-objdump/MachO/universal-arm64.test
Log Message:
-----------
Add more llvm-objdump test coverage for arm64e.x1 (#224110)
Commit: 6ad85f11c5151f18a3686322e37f8e64a48be327
https://github.com/llvm/llvm-project/commit/6ad85f11c5151f18a3686322e37f8e64a48be327
Author: Timur Baidusenov <timurbaidusenov at gmail.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M polly/lib/Analysis/ScopBuilder.cpp
M polly/test/ScopInfo/issue190128.ll
M polly/test/ScopInfo/simple_loop_unsigned.ll
A polly/test/ScopInfo/zext-loop-bound-unbounded.ll
Log Message:
-----------
[Polly] Do not assume loops to be bounded if latch conditions are invalid (#226202)
If a loop with an `<nsw>` induction variable appears to be unbounded for
some parameter values, `addLoopBoundsToHeaderDomain` removes them from
its domain without a runtime check, but the loop may only appear
unbounded because its latch condition is modeled incorrectly for these
values, e.g. `(zext i16 %n to i64)` is modeled as `n` under the
assumption `n >= 0`. Removing them also dropped that assumption, so for
`n < 0` the loop was not executed at all instead of running `65536 + n`
iterations. Exclude the parameter values for which the latch conditions
are invalid by a runtime check instead.
Fixes #192616 and #192618.
Assisted-by: Claude (Anthropic)
Commit: 9de286c070e3f3176e7bbfb79d3c4d95807e19a5
https://github.com/llvm/llvm-project/commit/9de286c070e3f3176e7bbfb79d3c4d95807e19a5
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M flang/lib/Semantics/check-omp-structure.cpp
M flang/lib/Semantics/check-omp-structure.h
M flang/lib/Semantics/check-omp-syntax.cpp
M flang/lib/Semantics/check-omp-variant.cpp
Log Message:
-----------
[flang][OpenMP] Rename some symbols in check-omp-syntax.cpp (#226484)
Some function names did not conform to the naming convention. Include a
couple of other non-significant changes.
Commit: ff5f397d6cd06d0eb72f798b4454d490050fb442
https://github.com/llvm/llvm-project/commit/ff5f397d6cd06d0eb72f798b4454d490050fb442
Author: Lei Zhang <antiagainst at gmail.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUMachineFunctionInfo.cpp
A llvm/test/CodeGen/AMDGPU/lds-dynamic-direct-and-indirect-use.ll
Log Message:
-----------
[AMDGPU] Fix dynamic LDS consistency check in setDynLDSAlign (#225825)
5bf967cb132b ("[RFC][AMDGPU] Add BARRIER address space") changed the
absolute-address check in `setDynLDSAlign` to read the dynamic LDS
global being lowered (`GV`) instead of the kernel's representative
`llvm.amdgcn.<kernel>.dynlds` variable (`Dyn`).
`amdgpu-lower-module-lds` attaches `!absolute_symbol` only to the
representative; uses of the original dynamic LDS global inside the
kernel are left in place and never carry that metadata. As a result, a
kernel that accesses dynamic LDS both directly and through a non-inlined
callee now aborts with "Inconsistent metadata on dynamic LDS variable".
Commit: a514ce406f06bfbebeb5d8d9bc76e9cc5ec6a92b
https://github.com/llvm/llvm-project/commit/a514ce406f06bfbebeb5d8d9bc76e9cc5ec6a92b
Author: Nico Weber <thakis at chromium.org>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/utils/gn/secondary/clang/tools/driver/BUILD.gn
Log Message:
-----------
[gn] Add clang_static_plugin_sources to link out-of-tree plugins into clang (#226381)
This is useful for testing and profiling e.g. Chromium's clang plugins
without having to export symbols from the clang binary.
# args.gn
clang_static_plugin_sources = [
"/path/to/chromium/src/tools/clang/plugins/FindBadConstructsAction.cpp",
...
]
clang_static_plugin_include_dirs = [ "/path/to/chromium/src" ]
...or put the above in a gni file and put just `import("plugins.gni")`
in args.gn
No behavior change if the list is empty (the default).
Commit: 1978a469493fec319cd61e2eac42abade837fafc
https://github.com/llvm/llvm-project/commit/1978a469493fec319cd61e2eac42abade837fafc
Author: Kazu Hirata <kazu at google.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M clang/lib/AST/ASTImporter.cpp
M clang/lib/CodeGen/CGBlocks.cpp
M clang/lib/Serialization/ASTWriterStmt.cpp
Log Message:
-----------
[clang] Migrate away from PointerUnion::dyn_cast (NFC) (#226390)
Note that PointerUnion::dyn_cast has been soft deprecated in
PointerUnion.h:
// FIXME: Replace the uses of is(), get() and dyn_cast() with
// isa<T>, cast<T> and the llvm::dyn_cast<T>
Literal migration would result in dyn_cast_if_present (see the
definition of PointerUnion::dyn_cast), but this patch uses dyn_cast on
ExprWithCleanups::CleanupObject because it is always nonnull.
Specifically, ExprWithCleanups::getObjects() is populated from a slice
of Sema::ExprCleanupObjects, which only receives nonnull pointers in
the following places:
- Sema::BuildCompoundLiteralExpr
- Sema::ActOnBlockStmtExpr
- Sema::BuildBlockForLambdaConversion
Assisted-by: Antigravity
Commit: 76d4a51fe990d5915c8b30587b09d57e45d533a2
https://github.com/llvm/llvm-project/commit/76d4a51fe990d5915c8b30587b09d57e45d533a2
Author: Kazu Hirata <kazu at google.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanHelpers.h
M llvm/lib/Transforms/Vectorize/VPlanValue.h
Log Message:
-----------
[Vectorize] Remove unused functions (NFC) (#226392)
BoUpSLP::TreeEntry::isOneOf:
The last caller was removed on April 1, 2025 in commit
0e3049c562ccdea288c3b1f3b3d1ce5992d284b0.
BoUpSLP::ScheduleCopyableData::verify:
Introduced on August 11, 2025 in commit
2d7b55a028139dde58a994a65895841190dfde96 without any callers.
HorizontalReduction::hasSameParent:
The last caller was removed on July 29, 2024 in commit
197f4a90519df308d9bfddcc931f7683a5ae9cb9.
VPBlockBase::getHierarchicalPredecessors:
The last caller was removed on May 24, 2025 in commit
dcef154b5caf6556e69bb18bbb0506d274aa474e.
VPIRFlags::isNonNeg:
The last caller was removed on July 1, 2025 in commit
6b3d2b629cc3805d483ec4522cc97e2540070ae1.
VPHistogramRecipe::getOpcode:
Introduced on September 27, 2024 in commit
6f1a8c2da278a04565877e277bc4d5b70055ac74 without any callers.
VPWidenInductionRecipe::setStepValue:
The last caller was removed on May 22, 2026 in commit
5c853423f4f9e7296b7596b7f3ccade481686bfd.
VPReductionPHIRecipe::isPartialReduction:
Introduced on November 26, 2025 in commit
071d1fb8beda4c0ec9ede0acab12a382f34758fe without any callers.
VPTransformState::reset:
The last callers were removed on May 3, 2026 in commit
efd429fdfb6f3f0a6991d9d08ab15ca89f27a7c3.
VPValue::hasDefiningRecipe:
The last caller was removed on June 28, 2026 in commit
7abad0faf4bfe1cb674d7fd362cc31edb1d0c460.
Assisted-by: Antigravity
Commit: 58e81dc9a3e25cc41ad26f7cf222dea2c4aa391b
https://github.com/llvm/llvm-project/commit/58e81dc9a3e25cc41ad26f7cf222dea2c4aa391b
Author: Luke Lau <luke at igalia.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/early_exit_costs.ll
M llvm/test/Transforms/LoopVectorize/AArch64/simple_early_exit.ll
M llvm/test/Transforms/LoopVectorize/AArch64/single-early-exit-interleave.ll
M llvm/test/Transforms/LoopVectorize/RISCV/early-exit-live-out.ll
M llvm/test/Transforms/LoopVectorize/RISCV/sink-to-early-exit.ll
M llvm/test/Transforms/LoopVectorize/VPlan/uncountable-early-exit-vplan.ll
M llvm/test/Transforms/LoopVectorize/dereferenceable-info-from-assumption-constant-size.ll
M llvm/test/Transforms/LoopVectorize/early-exit-calls.ll
M llvm/test/Transforms/LoopVectorize/early-exit-load-live-out.ll
M llvm/test/Transforms/LoopVectorize/early-exit-unary-ops.ll
M llvm/test/Transforms/LoopVectorize/multiple-early-exits.ll
M llvm/test/Transforms/LoopVectorize/predicated-early-exits-interleave.ll
M llvm/test/Transforms/LoopVectorize/predicated-multiple-exits.ll
M llvm/test/Transforms/LoopVectorize/predicated-single-exit.ll
M llvm/test/Transforms/LoopVectorize/single-early-exit-cond-poison.ll
M llvm/test/Transforms/LoopVectorize/single-early-exit-deref-assumptions.ll
M llvm/test/Transforms/LoopVectorize/single-early-exit-interleave-only.ll
M llvm/test/Transforms/LoopVectorize/single-early-exit-interleave.ll
M llvm/test/Transforms/LoopVectorize/single_early_exit.ll
M llvm/test/Transforms/LoopVectorize/single_early_exit_live_outs.ll
M llvm/test/Transforms/LoopVectorize/sink-to-early-exit.ll
M llvm/test/Transforms/LoopVectorize/vector-loop-backedge-elimination-early-exit.ll
M llvm/test/Transforms/LoopVectorize/vector-loop-backedge-elimination-predicated-early-exit.ll
Log Message:
-----------
[VPlan] Use frozen combined condition in early exit first-active-lane (#223643)
Combined is used both to compute if an early exit was taken via
VPInstruction::AnyOf, as well as the index of the early-exited lane in
VPInstruction::FirstActiveLane.
Combined can have poison lanes past the exited lane, so the AnyOf uses
freeze to prevent branching on poison. However FirstActiveLane on a
vector with a poison lane is poison (see #223935), so we need to also
use the frozen version of Combined to prevent poison there.
Commit: 7af28a7e7b3073593d5f394d02b10f382d6cbab1
https://github.com/llvm/llvm-project/commit/7af28a7e7b3073593d5f394d02b10f382d6cbab1
Author: Kai Nacke <kai.peter.nacke at ibm.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/MC/GOFFObjectWriter.cpp
M llvm/test/CodeGen/SystemZ/zos-section-1.ll
M llvm/test/CodeGen/SystemZ/zos-section-2.ll
M llvm/test/CodeGen/SystemZ/zos-symbol-2.ll
Log Message:
-----------
[SystemZ][z/OS] Use section ordinal for temporary symbols (#226306)
A relocation involving a temporary symbol is interpreted as offset of
the symbol to the section begin. Currently, this is resolved via the
begin symbol of the section. However, that symbol may also have the
temporary flag set, and therefore has an index of 0. Since a symbol is
emitted of reach section, it is safe to use the ordinal of the section
instead, avoiding all issues with temporary symbols.
Commit: 621e088c0f5d435506a0d344d3b62ddc11f16147
https://github.com/llvm/llvm-project/commit/621e088c0f5d435506a0d344d3b62ddc11f16147
Author: Ebuka Ezike <e_ezike at apple.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M lldb/packages/Python/lldbsuite/test/tools/lldb_dap/session_helpers.py
M lldb/tools/lldb-dap/Handler/ThreadsRequestHandler.cpp
Log Message:
-----------
[lldb-dap] Always return the up-to-date thread if possible. (#226140)
Only send the initial thread list if the process is not stopped and only
the first time.
Remove the workaround in tests. This should not affect tests since we
mostly get the `threadId` from a stopped event.
Commit: edd241997b82b7803bd496933e340762cc06bd77
https://github.com/llvm/llvm-project/commit/edd241997b82b7803bd496933e340762cc06bd77
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h
Log Message:
-----------
[LV] Remove unused VectorizationFactor comparison operators (NFC) (#226511)
VectorizationFactor::operator== and operator!= have no users. Remove it.
Commit: 8ccb1826dad0257eda59d88b5fd35a0bc3b933f8
https://github.com/llvm/llvm-project/commit/8ccb1826dad0257eda59d88b5fd35a0bc3b933f8
Author: Pedro Vicente <pmadcv at gmail.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/docs/LangRef.md
M llvm/docs/ReleaseNotes.md
M llvm/include/llvm-c/Core.h
M llvm/include/llvm/Analysis/InstSimplifyFolder.h
M llvm/include/llvm/Analysis/TargetFolder.h
M llvm/include/llvm/AsmParser/LLParser.h
M llvm/include/llvm/AsmParser/LLToken.h
M llvm/include/llvm/Bitcode/LLVMBitCodes.h
M llvm/include/llvm/IR/ConstantFolder.h
M llvm/include/llvm/IR/IRBuilder.h
M llvm/include/llvm/IR/IRBuilderFolder.h
M llvm/include/llvm/IR/InstVisitor.h
M llvm/include/llvm/IR/Instruction.def
M llvm/include/llvm/IR/Instructions.h
M llvm/include/llvm/IR/NoFolder.h
M llvm/lib/AsmParser/LLLexer.cpp
M llvm/lib/AsmParser/LLParser.cpp
M llvm/lib/Bitcode/Reader/BitcodeReader.cpp
M llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
M llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h
M llvm/lib/CodeGen/TargetLoweringBase.cpp
M llvm/lib/IR/AsmWriter.cpp
M llvm/lib/IR/Core.cpp
M llvm/lib/IR/Instruction.cpp
M llvm/lib/IR/Instructions.cpp
M llvm/lib/IR/Verifier.cpp
M llvm/test/Analysis/IR2Vec/Inputs/reference_default_vocab_print.txt
M llvm/test/Analysis/IR2Vec/Inputs/reference_wtd1_vocab_print.txt
M llvm/test/Analysis/IR2Vec/Inputs/reference_wtd2_vocab_print.txt
A llvm/test/Assembler/bitinsert-bitextract-invalid.ll
A llvm/test/Assembler/bitinsert-bitextract.ll
M llvm/test/Bitcode/compatibility.ll
A llvm/test/CodeGen/AArch64/bitinsert-bitextract-common-offsets.ll
A llvm/test/CodeGen/AArch64/bitinsert-bitextract-fp.ll
A llvm/test/CodeGen/AArch64/bitinsert-bitextract.ll
A llvm/test/CodeGen/AMDGPU/bitinsert-bitextract-common-offsets.ll
A llvm/test/CodeGen/AMDGPU/bitinsert-bitextract-fp.ll
A llvm/test/CodeGen/AMDGPU/bitinsert-bitextract.ll
A llvm/test/CodeGen/ARM/bitinsert-bitextract-common-offsets.ll
A llvm/test/CodeGen/ARM/bitinsert-bitextract-fp.ll
A llvm/test/CodeGen/ARM/bitinsert-bitextract.ll
A llvm/test/CodeGen/PowerPC/bitinsert-bitextract-common-offsets.ll
A llvm/test/CodeGen/PowerPC/bitinsert-bitextract-fp.ll
A llvm/test/CodeGen/PowerPC/bitinsert-bitextract.ll
A llvm/test/CodeGen/RISCV/bitinsert-bitextract-common-offsets.ll
A llvm/test/CodeGen/RISCV/bitinsert-bitextract-fp.ll
A llvm/test/CodeGen/RISCV/bitinsert-bitextract.ll
A llvm/test/CodeGen/X86/GlobalISel/bitinsert-bitextract.ll
A llvm/test/CodeGen/X86/bitinsert-bitextract-common-offsets.ll
A llvm/test/CodeGen/X86/bitinsert-bitextract-fp.ll
A llvm/test/CodeGen/X86/bitinsert-bitextract.ll
A llvm/test/Verifier/bitextract-bitinsert-invalid-verifier.ll
M llvm/test/tools/llvm-ir2vec/entities.ll
M llvm/test/tools/llvm-ir2vec/triplets.ll
M llvm/tools/llvm-c-test/echo.cpp
M llvm/unittests/Analysis/IR2VecTest.cpp
Log Message:
-----------
[IR] Implementation and lowering of `bitinsert` and `bitextract` (#200605)
This PR introduces `bitinsert` and `bitextract` instructions for LLVM
IR. These allow bit manipulation for byte types. Both were lowered to
GlobalIsel and SDag.
Tests were added for AArch64, AMDGPU, ARM, PowerPC, RISCV, x86 and LLVM
IR.
The LangRef was updated to document the new instructions.
The lowering of `bitextract` and `bitinsert` instructions are
implemented using integer operations.
In order to obtain the results for `bitextract`, a shift right
instruction with a specific offset is used (that can be a variable or an
immediate).
Relative to floating-point, in `bitinsert`, we reinterpret the bits of
the floating-point value as if it is an integer.
Pointer operands and results are reinterpreted as if by bitcast, as
specified in the LangRef.
This PR is based on the RFC:
https://discourse.llvm.org/t/rfc-bitinsert-and-bitextract-instructions-for-llvm-ir-2/90764
Commit: 5b8e65685b4fe99191a217bfa0527c51cf36925c
https://github.com/llvm/llvm-project/commit/5b8e65685b4fe99191a217bfa0527c51cf36925c
Author: Jason Van Beusekom <jason.van-beusekom at hpe.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M offload/include/Shared/SourceInfo.h
M openmp/docs/ReleaseNotes.md
Log Message:
-----------
[Offload][OpenMP] remove SourceInfo::removePath (#226283)
Following discussion on
https://discourse.llvm.org/t/rfc-add-opt-in-option-for-full-source-paths-in-offload-info-output/91901
this commit removes SourceInfo::removePath which changes
LIBOMPTARGET_INFO to provide a non truncated source path:
``` c
#include <stdio.h>
#define N 4
int main(void) {
int a[N];
for (int i = 0; i < N; ++i)
a[i] = 0;
#pragma omp target map(tofrom : a[0 : N])
{
a[0] = 1;
}
printf("%d\n", a[0]); /* expect 1 */
return 0;
}
```
``` bash
clang -fopenmp -fopenmp-targets=amdgcn-amd-amdhsa -g ./test/test.c
# new
LIBOMPTARGET_INFO=-1 ./a.out
omptarget device 0 info: Entering OpenMP kernel at ./test/test.c:9:1 with 1 arguments:
# old
LIBOMPTARGET_INFO=-1 ./a.out
omptarget device 0 info: Entering OpenMP kernel at test.c:9:1 with 1 arguments:
```
Commit: 0551d60c516c2dc161007ee9ed466f36be40667d
https://github.com/llvm/llvm-project/commit/0551d60c516c2dc161007ee9ed466f36be40667d
Author: Zorojuro <sawantsukumar at gmail.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M libc/src/__support/math/bf16sub.h
M libc/src/__support/math/bf16subf.h
M libc/src/__support/math/bf16subf128.h
M libc/test/shared/shared_math_constexpr_test.cpp
Log Message:
-----------
[libc] Make bf16sub functions constexpr (#223506)
Makes the bf16sub for all types constexpr along with tests
Commit: d4c354ca333192d2db3d45b2b028a98f9fbbd347
https://github.com/llvm/llvm-project/commit/d4c354ca333192d2db3d45b2b028a98f9fbbd347
Author: Maksim Levental <maksim.levental at gmail.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M mlir/include/mlir-c/Rewrite.h
M mlir/lib/CAPI/Transforms/Rewrite.cpp
M mlir/test/CAPI/CMakeLists.txt
M mlir/test/CAPI/rewrite.c
Log Message:
-----------
[mlir-c] Add mlirDialectMaterializeConstant (#206553)
Exposes `Dialect::materializeConstant` through the MLIR C API, letting
callers ask a dialect to build a constant operation for a given
attribute and type.
Assisted by: Claude
Commit: 14f451262dc753b53f79a103744dd6988894467f
https://github.com/llvm/llvm-project/commit/14f451262dc753b53f79a103744dd6988894467f
Author: Derek Schuff <dschuff at chromium.org>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M clang/lib/Basic/Targets/WebAssembly.cpp
M clang/lib/Basic/Targets/WebAssembly.h
M clang/test/CodeGen/thread-model.c
M clang/test/CodeGenCXX/static-init-wasm.cpp
M clang/test/Preprocessor/init.c
M llvm/lib/Target/WebAssembly/WebAssemblyCoalesceFeaturesAndStripAtomics.cpp
M llvm/lib/TargetParser/Triple.cpp
R llvm/test/CodeGen/WebAssembly/coalesce-features-thread-model.ll
Log Message:
-----------
[clang][WeAssembly] Do not override thread model when building without atomics (#225981)
This change does 2 things. The first is to revert #223917, setting the
Triple's
default thread model back to posix. The second is to stop overriding it
when
atomics are not enabled.
This means that compiles with no thread- or atomics-related flags will
get the default posix thread model, independently of whether they get
_REENTRANT defined or the atomics feature is enabled. Practically this
means that the thread model will always be posix unless explicitly
overridden at the driver command line.
The leftover setting of Opts.POSIXThreads became a no-op when used
with the clang driver because the logic would only activate when
-pthread
was not already used (since the driver has separate logic linking
several
flags together).
This is a safer version of the status quo before the thread-model
module flag was introduced, because atomics are still lowered
in the same way but there is no risk of unsafe initialization
or LICM in such scenarios. We could probably further simplify
the interaction between various thread- and atomics-related
flags and thread agnosticism, but this is a small step
that fixes a known hazard.
Commit: 73fc71b19905b15e6ff14ae3149c6fabce961c1b
https://github.com/llvm/llvm-project/commit/73fc71b19905b15e6ff14ae3149c6fabce961c1b
Author: Jan Svoboda <jan_svoboda at apple.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M clang/unittests/Lex/LexerTest.cpp
Log Message:
-----------
[clang][test] Fix lifetimes of HS/PP options (#225885)
PR #133467 changed how lifetimes work for `PreprocessorOptions`. In
LexerTest.cpp, the lifetimes were set up incorrectly, leading to
potential use-after-free crashes. This PR fixes that by expanding the
lifetime of both `PreprocessorOptions` and `HeaderSearchOptions`.
Commit: 9068aede6fcbd3e47602fce96fbb077e3e4d8cc4
https://github.com/llvm/llvm-project/commit/9068aede6fcbd3e47602fce96fbb077e3e4d8cc4
Author: Luke Lau <luke at igalia.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/test/Transforms/LoopVectorize/early-exit-live-out-extract-lane.ll
Log Message:
-----------
[LV] Fix early exit tests after #223643. NFC (#226521)
Commit: 44f262eb67778e6bcb7675599384e010062cae10
https://github.com/llvm/llvm-project/commit/44f262eb67778e6bcb7675599384e010062cae10
Author: Alison Zhang <alisonzhang at ibm.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M clang/test/Analysis/Scalable/ssaf-src-edit-merge/conflict-preserves-unrelated-zero-length-insert.test
M clang/test/Analysis/Scalable/ssaf-src-edit-merge/conflict-stderr-without-sarif.test
M clang/test/Analysis/Scalable/ssaf-src-edit-merge/empty-input.test
M clang/test/Analysis/Scalable/ssaf-src-edit-merge/identical-overlap.test
M clang/test/Analysis/Scalable/ssaf-src-edit-merge/no-conflict-sarif-empty.test
M clang/test/Analysis/Scalable/ssaf-src-edit-merge/non-overlapping.test
M clang/test/Analysis/Scalable/ssaf-src-edit-merge/order-invariance.test
M clang/test/Analysis/Scalable/ssaf-src-edit-merge/parent-dir-missing.test
M clang/test/Analysis/Scalable/ssaf-src-edit-merge/pre-dedup-identical-non-zero-length.test
M clang/test/Analysis/Scalable/ssaf-src-edit-merge/pre-dedup-zero-length-insert.test
M clang/test/Analysis/Scalable/ssaf-src-edit-merge/range-overlap-cluster-of-three-sarif.test
M clang/test/Analysis/Scalable/ssaf-src-edit-merge/range-overlap-conflict-sarif.test
M clang/test/Analysis/Scalable/ssaf-src-edit-merge/sarif-out-parent-dir-missing.test
M clang/test/Analysis/Scalable/ssaf-src-edit-merge/single-input-internal-conflict.test
M clang/test/Analysis/Scalable/ssaf-src-edit-merge/single-input.test
M clang/test/Analysis/Scalable/ssaf-src-edit-merge/three-input-all-conflict.test
M clang/test/Analysis/Scalable/ssaf-src-edit-merge/three-input-conflict-sarif.test
M clang/test/Analysis/Scalable/ssaf-src-edit-merge/two-conflicts-different-offsets-sarif.test
M clang/test/Analysis/Scalable/ssaf-src-edit-merge/two-input-conflict-sarif.test
M clang/test/Analysis/Scalable/ssaf-src-edit-merge/two-input-conflict.test
Log Message:
-----------
[test][ssaf][AIX] Fix sed -i portability for AIX (#226293)
AIX's sed does not support the `-i` flag, causing the tests added in
https://github.com/llvm/llvm-project/pull/216183 to fail on AIX. This
patch updates the tests to use a POSIX-compliant redirect instead.
Commit: f1129f338806da062347a8ce019b88b51452917f
https://github.com/llvm/llvm-project/commit/f1129f338806da062347a8ce019b88b51452917f
Author: Ellis Hoag <ellis.sparky.hoag at gmail.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
R llvm/test/Transforms/PGOProfile/Inputs/indirect_call.proftext
M llvm/test/Transforms/PGOProfile/indirect_call_annotation.ll
Log Message:
-----------
[NFC][PGOProfile] Inline icall annotation proftext test (#226324)
Commit: 378ceb307bbc729bb918601a28c468df419b4d34
https://github.com/llvm/llvm-project/commit/378ceb307bbc729bb918601a28c468df419b4d34
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M clang/include/clang/Basic/BuiltinsRISCV.td
M clang/lib/CodeGen/TargetBuiltins/RISCV.cpp
M clang/lib/Headers/riscv_packed_simd.h
M clang/test/CodeGen/RISCV/rvp-intrinsics.c
M llvm/include/llvm/IR/IntrinsicsRISCV.td
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoP.td
M llvm/test/CodeGen/RISCV/rvp-simd-32.ll
M llvm/test/CodeGen/RISCV/rvp-simd-64.ll
Log Message:
-----------
[RISCV][P-Ext] Add builtins and IR intrinsics for packed shifts. (#225968)
The packed shift instructions use 5-bit shift amounts regardless of
element width. The C intrinsic should match this which means we can't
use C shift operators to implement them.
Rename RISCVISD::PSHL to RISCVISD::PSLL.
Commit: 1f9d3b2506fa32981fd281aab56357404af53ffe
https://github.com/llvm/llvm-project/commit/1f9d3b2506fa32981fd281aab56357404af53ffe
Author: Ellis Hoag <ellis.sparky.hoag at gmail.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
Log Message:
-----------
[NFC][PGOProfile] Inline icall annotation proftext test (#226324)
Commit: bff7b7503c1cdfdba72bcd12ef8208ad42130946
https://github.com/llvm/llvm-project/commit/bff7b7503c1cdfdba72bcd12ef8208ad42130946
Author: Ömer Sinan Ağacan <omer at osa1.net>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-vmax.ll
Log Message:
-----------
[msan] Update intrinsic list in arm64-vmax.ll (NFC) (#226387)
The intrinsics llvm.aarch64.neon.{u,s}{min,max} were removed in
0ce1b5f91add535d1e8b910ee90c178e054c65eb, remove the mentions of them in
the test file as per the review comment in #225339.
Commit: 6ec87e7ec4b3ca6f665a02e05d0e5fe9c37cd6cc
https://github.com/llvm/llvm-project/commit/6ec87e7ec4b3ca6f665a02e05d0e5fe9c37cd6cc
Author: Anshul Nigham <nigham at google.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/lldb/BUILD.bazel
Log Message:
-----------
[Bazel] Add Telemetry dependency to lldb-dap (#226526)
Fixes lldb-dap bazel layering failure introduced in commit 1cc5657c4ff6,
where LLDBUtils.h includes llvm/Telemetry/Telemetry.h.
Commit: 23e12c97a04c034a9487f4b95e3531d1ead90c59
https://github.com/llvm/llvm-project/commit/23e12c97a04c034a9487f4b95e3531d1ead90c59
Author: Kunal Dubey <xakep8 at protonmail.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M clang/include/clang/CIR/Dialect/IR/CIRAttrs.td
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/lib/CIR/CodeGen/CIRGenBuilder.h
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
M clang/test/CIR/IR/enum-attrs.cir
M clang/test/CIR/Lowering/call-llvm-intrinsic.cir
Log Message:
-----------
[CIR] Added fast-math flags to LLVM intrinsic calls (#224899)
Added fast-math flags attribute to CIR which cir.call_llvm_intrinsic now
carries through DirectToLLVM lowering. CIR now preserves fast-math flags
such as reassoc when lowering to llvm.call_intrinsic.
Added test for the same.
Commit: 774b4527fd60dc5ef7ed6539a8f2e6fe100e337b
https://github.com/llvm/llvm-project/commit/774b4527fd60dc5ef7ed6539a8f2e6fe100e337b
Author: Ryan Buchner <rbuchner at qti.qualcomm.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/include/llvm/Analysis/TargetTransformInfo.h
M llvm/include/llvm/CodeGen/BasicTTIImpl.h
M llvm/lib/Target/RISCV/RISCVProcessors.td
M llvm/lib/Target/RISCV/RISCVSubtarget.h
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/test/Analysis/CostModel/RISCV/vp-intrinsics.ll
Log Message:
-----------
[Analysis][RISCV] More accurately estimate the cost of strided vector loads (#175135)
For small constant strides, attempt to predict the amount of coalescing
that will be done by the target machine to give a better cost estimate.
Currently, strided loads/stores are costed as having a cost of 1 per
element (i.e. being equivalent to scalar loads/stores).
---------
Co-authored-by: Luke Lau <luke_lau at icloud.com>
Commit: f2b3ba3affb147bf085fd58f1f7261dd32ae91c8
https://github.com/llvm/llvm-project/commit/f2b3ba3affb147bf085fd58f1f7261dd32ae91c8
Author: Sang Ik Lee <sang.ik.lee at intel.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
A mlir/test/Integration/Dialect/XeGPU/WG/simple_gemm_bf16.mlir
R mlir/test/Integration/Dialect/XeGPU/WG/simple_mxfp_gemm.mlir
A mlir/test/Integration/Dialect/XeGPU/WG/simple_mxfp_gemm_F4.mlir
A mlir/test/Integration/Dialect/XeGPU/WG/simple_mxfp_gemm_F8.mlir
M mlir/test/Integration/Dialect/XeGPU/WG/simple_mxfp_gemm_dequantizeB_F4.mlir
A mlir/test/Integration/Dialect/XeGPU/WG/simple_mxfp_gemm_dequantizeB_F8.mlir
M mlir/test/Integration/Dialect/XeGPU/WG/simple_mxfp_gemm_quantizeA_F4.mlir
A mlir/test/Integration/Dialect/XeGPU/WG/simple_mxfp_gemm_quantizeA_F8.mlir
Log Message:
-----------
[MLIR][XeGPU] Add MXFP fp8 WG GEMM tests and use shared input set (#225944)
Adds four workgroup-level tests, updates two and renames one, so that
seven tests covering bf16, mx-fp4 and mx-fp8 exercise the same
arithmetic on the same operand values and check against the same
expected result.
1. simple_mxfp_gemm -> simple_mxfp_gemm_F4 - renamed, for consistency
with the F4/F8 suffixes used by the quantize and dequantize tests
2. (new) simple_gemm_bf16 - non-quantized bf16 GEMM at the MXFP problem
size, as the unquantized comparison point, and where the shared input
set is documented
3. (new) simple_mxfp_gemm_F8 - f8E5M2 operands with f8E8M0FNU scales
4. (new) simple_mxfp_gemm_dequantizeB_F8
5. (new) simple_mxfp_gemm_quantizeA_F8 - fp8 counterparts of the
existing fp4 tests
6. simple_mxfp_gemm_dequantizeB_F4 and simple_mxfp_gemm_quantizeA_F4 are
updated in place.
What the update changes:
* Meaningful operand values. The tests previously used all-ones
operands, which cannot distinguish a correct kernel from one that swaps
the two fp4 values in a byte, misapplies a scale, or mixes up lanes or
tiles. Operands are now drawn from the 8 magnitudes e2m1 can represent -
0, 0.5, 1, 1.5, 2, 3, 4, 6 - indexed by (i + k) % 8 and (j + k) % 8, so
consecutive K values differ and the packing is exercised. Every value is
exact in f4E2M1FN, f8E5M2, bf16 and f32, which is what lets one input
set serve all three formats.
* Non-unit block scales. A carries a per-K-block divisor and B a
per-K-block scale, three of each, all powers of two, cycling per block
of 32. The quantized formats realise the same values through their own
scales, so a scale that is ignored or applied to the wrong block now
changes the result.
* One reference result. Each test computes its expected C with a host
f32 GEMM over f32 shadows of the operands, filled in the same loop that
writes the device operands so the two cannot drift. Every product is a
multiple of 0.25 and the largest result is well under 2^24, so the
accumulation is exact and the comparison is bit-for-bit rather than
approximate.
* A labelled result line. verifyMemRefF32's mismatch count is printed as
"mismatches: <n>" via printString/printI64/printNewline and matched with
{{^mismatches: 0$}}. A bare "0" check is a substring match over all of
stdout, so it passes on any 0 the runtime happens to print, including
one inside a larger number, and cannot distinguish a correct run from a
kernel that never ran.
* A fix for the fp4 A operand in simple_mxfp_gemm_F4.
gpu.alloc/memcpy/dealloc size a memref by rounding the element type up
to a whole byte - the size is lowered as gep(null, numElements) on i4,
which LLVM strides by 1 byte - so a packed fp4 memref is sized at twice
its real footprint. The test allocated A as memref<256x4096xf4E2M1FN>,
giving a 512 KB overread of a 524288-byte host buffer; because
mgpuMemcpy is asynchronous the fault surfaces later, at the stream sync
inside the first mgpuMemFree, so the test passed regardless. A now
crosses as memref<524288xi8> and is viewed as fp4 on the device, which
is what the B operand already does.
All seven follow the existing convention in this directory: the mlir-opt
compile is the active RUN line and the mlir-runner pipeline is kept
behind RUN-DISABLED with a MISMATCH check prefix, so no device is needed
and the compile-only run cannot pick up the result check.
Commit: b3ed324d42c0487e38980f4beddbb67c096f5f3f
https://github.com/llvm/llvm-project/commit/b3ed324d42c0487e38980f4beddbb67c096f5f3f
Author: Keith Smiley <keithbsmiley at gmail.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M lld/test/Unit/lit.cfg.py
M lld/unittests/AsLibELF/CMakeLists.txt
M lld/unittests/AsLibELF/OutputStream.cpp
M lld/unittests/AsLibELF/ROCm.cpp
Log Message:
-----------
[lld][test] Use LLVM helpers for input file discovery (#220404)
This was a suggestion on #220340 to avoid the custom env var handling
and use the `getInputFileDirectory` helper from the LLVM support library
Commit: 07aec21c88f48907b5da1d42f4522e106d30a9f1
https://github.com/llvm/llvm-project/commit/07aec21c88f48907b5da1d42f4522e106d30a9f1
Author: Guo Chen <guochen2 at amd.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.h
M llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/CMakeLists.txt
A llvm/lib/Target/AMDGPU/SIPostRA16BitMovFolding.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/merge-values-s16-true16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/usubsat.ll
M llvm/test/CodeGen/AMDGPU/add.v2i16.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.32bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.48bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.64bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll
M llvm/test/CodeGen/AMDGPU/flat-saddr-load.ll
M llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll
M llvm/test/CodeGen/AMDGPU/llc-pipeline.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.gather4.a16.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.msaa.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.a16.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.g16.encode.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.g16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.waitcnt.out.order.ll
M llvm/test/CodeGen/AMDGPU/mad-mix-hi-bf16.ll
M llvm/test/CodeGen/AMDGPU/repeated-divisor.ll
M llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll
A llvm/test/CodeGen/AMDGPU/si-post-ra-merge-v-mov-b16.mir
M llvm/test/CodeGen/AMDGPU/sub.v2i16.ll
M llvm/test/CodeGen/AMDGPU/v_swap_b16.ll
M llvm/test/CodeGen/AMDGPU/vector_shuffle.packed.ll
Log Message:
-----------
[AMDGPU] merge 16bit mov pairs in post-RA peephole (#208625)
Address https://github.com/llvm/llvm-project/issues/207011. Add 5
patterns to merge 16bit mov pairs.
Since we hoist instruction which might cross the waitcnt boundary,
insert a new pass before waitcnt for this transformation
Co-Authored-By: Claude
Commit: 3621db6aff701dcd9e6ff54ea281d24ee2f43448
https://github.com/llvm/llvm-project/commit/3621db6aff701dcd9e6ff54ea281d24ee2f43448
Author: Akash Manna <akash.manna.mymail at gmail.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M clang/docs/ReleaseNotes.md
M clang/lib/Sema/SemaOpenMP.cpp
A clang/test/OpenMP/for_loop_bitint_messages.c
Log Message:
-----------
[Clang][OpenMP] Fix crash on `_BitInt` loop bounds and counters in loop analysis (#226464)
Fixes #140074
When building the iteration count of an OpenMP loop, Sema derives a few
integer types from bit widths, e.g. to promote the upper bound to an
unsigned type as wide as the wider bound so that `upper - lower` cannot
overflow. Those types came from `ASTContext::getIntTypeForBitwidth`,
which only knows the standard integer widths and returns a null type for
anything else. With a bound or loop counter of type `_BitInt(931)` the
request was for a 960-bit type, the result was null, and it went
straight into `PerformImplicitConversion`, which asserted. The
`collapse(2)` in the reduced reproducer is incidental; a plain `#pragma
omp for` on the same loop crashes the same way.
The loop analysis now goes through a small helper that asks for the
standard type first and otherwise builds the `_BitInt` type of that
width and signedness with `ASTContext::getBitIntType`. It is used at the
three places that derive a type from a loop width: the upper-bound
promotion in `calculateNumIters`, the conversion to the loop variable's
width in `buildNumIterations`, and the logical iteration type in
`ActOnOpenMPCanonicalLoop`. Wide `_BitInt` loop variables are then
narrowed to the runtime's 64-bit iteration variable with the existing
warning, the same as `__int128` today.
Commit: 05f0bf084929c4fdbb5ac2952047ed00cd1d8b57
https://github.com/llvm/llvm-project/commit/05f0bf084929c4fdbb5ac2952047ed00cd1d8b57
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/Target/Mips/MipsSubtarget.cpp
M llvm/lib/Target/Mips/MipsSubtarget.h
Log Message:
-----------
Mips: Remove redundant Triple copy from the subtarget (#226528)
MCSubtargetInfo already stores the target triple, so MipsSubtarget's own
copy is unnecessary.
Co-authored-by: Claude Opus 5 <noreply at anthropic.com>
Commit: 3bcbae4bed67f5cadd9f68d39af47ae5b5af1794
https://github.com/llvm/llvm-project/commit/3bcbae4bed67f5cadd9f68d39af47ae5b5af1794
Author: Alex Langford <alangford at apple.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M lldb/include/lldb/Target/DynamicRegisterInfo.h
M lldb/source/Target/DynamicRegisterInfo.cpp
Log Message:
-----------
[lldb] Introduce DynamicRegisterInfo::RegisterSetWithStorage (#225555)
The RegisterSet struct is created in 2 different ways:
1.) Statically in headers/source files for register sets that are known
ahead of time.
2.) Dynamically according to input from outside of LLDB. Usually this is
through the gdb-remote stub, but may also come from a python script or
by determining an ISA variant's features (e.g. in RISCV).
This PR aims to address the lifetime of strings in RegisterSet. In
scenario (1), the lifetime of all data in a RegisterSet is static and
there is no concern about dangling pointers. However, in scenario (2),
DynamicRegisterInfo maintains a vector of RegisterSets. Until now, it
has relied on ConstString to persist the storage for the strings
indefinitely. As part of my quest to remove ConstString, I am
introducing a new struct wrapping RegisterSet that is responsible for
the storage and lifetime of the underlying RegisterSet strings.
Commit: d220d5e8239db918bd68f404dae589385a8029e8
https://github.com/llvm/llvm-project/commit/d220d5e8239db918bd68f404dae589385a8029e8
Author: Aditya Sinha <155882262+AdityaSinha149 at users.noreply.github.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M clang/include/clang/Interpreter/Interpreter.h
M clang/lib/Interpreter/Interpreter.cpp
A clang/test/Interpreter/HIP/hip-environment.hip
A clang/test/Interpreter/HIP/lit.local.cfg
M clang/test/lit.cfg.py
M clang/tools/clang-repl/ClangRepl.cpp
Log Message:
-----------
[clang-repl] Initialized HIP environment for clang-repl (#217582)
This PR initializes the HIP environment for clang-repl. Since an
IncrementalHipDeviceParser does not exist yet, a message is printed
after the environment setup indicating that the HIP environment was set
up but is not yet supported.
It also adds a test file that runs clang-repl with the -hip option and
checks that this message is printed. Once the parser is built, the
current test file will be removed and replaced with tests that verify
the complete flow.
This PR has a prerequisite, #217228, which skips emitting the
`__hip_cuid_` global under incremental extensions. Without it,
clang-repl's HIP mode would emit the same symbol in every incremental
module and fail at JIT link with a duplicate-symbol error.
Assisted by Claude Opus 4.8
Commit: 0ae27ad06c80796bdae576e27a44b2877e5c2a4f
https://github.com/llvm/llvm-project/commit/0ae27ad06c80796bdae576e27a44b2877e5c2a4f
Author: Gaëtan Bossu <gaetan.bossu at arm.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/test/Analysis/CostModel/AArch64/masked_ldst.ll
M llvm/test/Analysis/CostModel/AArch64/sve-arith.ll
M llvm/test/Analysis/CostModel/AArch64/sve-ldst.ll
M llvm/test/CodeGen/AArch64/sve-int-arith.ll
M llvm/test/Transforms/LoopVectorize/AArch64/force-scalable-vectorization-always.ll
M llvm/test/Transforms/LoopVectorize/AArch64/invalid-costs.ll
M llvm/test/Transforms/LoopVectorize/AArch64/scalable-alloca.ll
M llvm/test/Transforms/LoopVectorize/AArch64/scalable-call.ll
M llvm/test/Transforms/LoopVectorize/AArch64/scalable-vectorization-cost-tuning.ll
Log Message:
-----------
Revert "[AArch64][CostModel] Consider some nxv1 operations as legal" (#226531)
Reverts llvm/llvm-project#214471
This caused a failure in
https://lab.llvm.org/buildbot/#/builders/198/builds/15417 and I want to
spend a bit more time to test the ISel for vector_reverse and
vector_splice. It's also quite surprising that the test picked a VF of
`vscale x 1`
Commit: 9214c04da2ea302b773797f50ad11636c7bab097
https://github.com/llvm/llvm-project/commit/9214c04da2ea302b773797f50ad11636c7bab097
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M clang/lib/CodeGen/CGLoopInfo.cpp
M clang/test/CodeGen/align-loops.c
Log Message:
-----------
clang: Emit llvm.loop.align metadata for -falign-loops (#223147)
Commit: 9dcb4291cea195b9f0941d39540a4f2ccb9ff6bd
https://github.com/llvm/llvm-project/commit/9dcb4291cea195b9f0941d39540a4f2ccb9ff6bd
Author: Charles Zablit <c_zablit at apple.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M lldb/test/API/python_api/value/TestValueAPI.py
Log Message:
-----------
[lldb][test] Skip the sp/rsp check in register sets that have no rsp (#226176)
The test asserts the ABI name `"sp"` resolves to `"rsp"` within the same
register set. However, on Windows the architectural 16-bit `"sp"` lives
in `"supplementary registers"` while `"rsp"` is in `"General Purpose
Registers"`, so there is nothing to compare against.
https://learn.microsoft.com/en-us/windows-hardware/drivers/debugger/x64-architecture
This fixes `python_api/value/TestValueAPI.py` (`test_register`) on
Windows in swiftlang.
Commit: 51ccdfeadcfe29b1d46f978e8582ada109aebb91
https://github.com/llvm/llvm-project/commit/51ccdfeadcfe29b1d46f978e8582ada109aebb91
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M libcxx/test/benchmarks/containers/string.bench.cpp
Log Message:
-----------
[libc++] Add benchmark for string::pop_back() (#223729)
Commit: 68d354f5795682ea1fe03304ac3e7b2a43a36b0d
https://github.com/llvm/llvm-project/commit/68d354f5795682ea1fe03304ac3e7b2a43a36b0d
Author: Jason Van Beusekom <jason.van-beusekom at hpe.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M offload/include/Shared/SourceInfo.h
M openmp/docs/ReleaseNotes.md
Log Message:
-----------
Revert "[Offload][OpenMP] remove SourceInfo::removePath (#226283)" (#226557)
This reverts commit 5b8e65685b4fe99191a217bfa0527c51cf36925c.
In https://github.com/llvm/llvm-project/pull/226283 I forgot to update
info.c to account for the full file paths in its output, will update
commit with fixed test and re open PR
Commit: d92a0c1e5eba51dbf9a4c2a61a709b6758f2e40d
https://github.com/llvm/llvm-project/commit/d92a0c1e5eba51dbf9a4c2a61a709b6758f2e40d
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M mlir/include/mlir/IR/BuiltinDialect.td
M mlir/include/mlir/IR/BuiltinOps.td
M mlir/test/IR/module-op.mlir
M mlir/test/Transforms/sccp-callgraph.mlir
M mlir/test/Transforms/test-symbol-dce.mlir
M mlir/test/python/dialects/ml_program.py
Log Message:
-----------
[MLIR] Enable strict assembly properties for the builtin dialect (#225750)
Commit: 48884d2ddba0718960f68eb01a5b8c42c089f27c
https://github.com/llvm/llvm-project/commit/48884d2ddba0718960f68eb01a5b8c42c089f27c
Author: Cyndy Ishida <cyndy_ishida at apple.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M clang/lib/Lex/HeaderSearch.cpp
A clang/test/ClangScanDeps/modules-context-hash-case-sensitive-vfs-paths.c
M clang/test/ClangScanDeps/modules-context-hash-module-map-path.c
A clang/test/Modules/implicit-module-map-path-case-sensitive.c
Log Message:
-----------
[clang][Modules] Respect case sensitivity when hashing implicit module map path (#226339)
Before this patch, the implicit module hash normalized the module map
path, but explicit modules always respected the case in paths. This
worked by depending on FileEntry caching and/or relocation checking to
resolve correctly. This behavior was both subtle and difficult to
understand. Instead, respect the casing in paths for hashing to match
explicitly built modules so they can never diverge.
This patch also updates `modules-context-hash-module-map-path.c` to
match a downstream version that already tested for the case where vfs
overlay entries differ by case but point to the same file.
`modules-context-hash-case-sensitive-vfs-paths.c` is the same but points
to different underlying files.
Commit: 36e7743d8ec9e743ae66485ddf2a6b27549c8833
https://github.com/llvm/llvm-project/commit/36e7743d8ec9e743ae66485ddf2a6b27549c8833
Author: Anshil Gandhi <95053726+gandhi56 at users.noreply.github.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/Passes/LoadStoreVec.h
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/VecUtils.h
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/Passes/LoadStoreVec.cpp
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/VecUtils.cpp
Log Message:
-----------
[SandboxVec][LoadStoreVec][NFC] Tighten bundle element types (#226348)
Use Instruction*/Constant* for LoadStoreVec APIs where that is what
callers hold, and template getCombinedVectorTypeFor so BndlRef is not
forced through a non-covariant Value* conversion.
Co-authored-by: Cursor <cursoragent at cursor.com>
Commit: 72674697a28c25467649c4993eb033dc4af65951
https://github.com/llvm/llvm-project/commit/72674697a28c25467649c4993eb033dc4af65951
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/test/Transforms/LoopVectorize/VPlan/execution-frequencies-match-bfi.ll
M llvm/test/Transforms/LoopVectorize/X86/predicated-instruction-cost.ll
M llvm/test/Transforms/LoopVectorize/replicate-region-branch-weights.ll
Log Message:
-----------
[LV] Add tests for zero branch weights and execution frequencies (NFC). (#226553)
Add missing test coverage for VPlan-based execution frequency
computation:
* blocks entered via an edge with zero branch weight,
* blocks whose sibling edge has zero weight,
* nested branches whose skipping edges have zero weight,
* a block executing on all paths through the loop after a switch whose
probabilities do not add up to 1,
* frequencies below the smallest representable non-zero one
* all-zero weights making a join's frequency unknown
* estimated frequencies propagating through a branch with weights.
Also updates
llvm/test/Transforms/LoopVectorize/VPlan/execution-frequencies-match-bfi.ll
to check frequencies directly after the frequencies have been recorded.
Commit: a9809116ca6130906f20c727464ba8e878b59aa5
https://github.com/llvm/llvm-project/commit/a9809116ca6130906f20c727464ba8e878b59aa5
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M .github/workflows/libcxx-benchmark-commit.yml
M .github/workflows/libcxx-benchmark-cron.yml
M .github/workflows/libcxx-pr-benchmark.yml
M libcxx/utils/ci/lnt/README.md
M libcxx/utils/ci/lnt/machines.json
M libcxx/utils/ci/lnt/run-benchmarks
M libcxx/utils/ci/run-buildbot
Log Message:
-----------
[libc++] Add a benchmark machine for libstdc++ (#226346)
Add a machine that benchmarks the libstdc++ shipped with GCC 16 on macOS
instead of a libc++ build. To enable that, generalize the scripts and
workflows to make more aspects of machines.json optional (e.g. support
machines that don't need to build libc++).
Commit: 8dc7b3d92cc6371d942dc7619a81faa1f56de938
https://github.com/llvm/llvm-project/commit/8dc7b3d92cc6371d942dc7619a81faa1f56de938
Author: Joshua Batista <jbatista at microsoft.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M clang/include/clang/Basic/Builtins.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Basic/HLSLIntrinsics.td
M clang/lib/CodeGen/CGHLSLBuiltins.cpp
M clang/lib/CodeGen/CGHLSLRuntime.h
M clang/lib/Sema/SemaHLSL.cpp
A clang/test/CodeGenHLSL/builtins/WaveReadLaneFirst.hlsl
A clang/test/SemaHLSL/BuiltIns/WaveReadLaneFirst-errors.hlsl
M clang/test/SemaHLSL/WaveBuiltinAvailability.hlsl
M llvm/include/llvm/IR/IntrinsicsDirectX.td
M llvm/include/llvm/IR/IntrinsicsSPIRV.td
M llvm/lib/Target/DirectX/DXIL.td
M llvm/lib/Target/DirectX/DXILShaderFlags.cpp
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
A llvm/test/CodeGen/DirectX/LongVector/wave-readlane-first.ll
M llvm/test/CodeGen/DirectX/ShaderFlags/wave-ops.ll
A llvm/test/CodeGen/DirectX/WaveReadLaneFirst.ll
A llvm/test/CodeGen/DirectX/WaveReadLaneFirst_mat.ll
A llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_long_vector/wave-readlane-first.ll
A llvm/test/CodeGen/SPIRV/hlsl-intrinsics/WaveReadLaneFirst.ll
A llvm/test/CodeGen/SPIRV/hlsl-intrinsics/WaveReadLaneFirst_mat.ll
Log Message:
-----------
Add WaveReadLaneFirst HLSL function (#220373)
This PR adds the `WaveReadLaneFirst` HLSL function.
Fixes https://github.com/llvm/llvm-project/issues/99164
Assisted by: Github Copilot
Commit: 7b42d2f9991c3680627878a49b1b323cb56176a0
https://github.com/llvm/llvm-project/commit/7b42d2f9991c3680627878a49b1b323cb56176a0
Author: Nico Weber <thakis at chromium.org>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/Target/AMDGPU/BUILD.gn
Log Message:
-----------
[gn build] Port 07aec21c88f4 (#226571)
Commit: cc527d5399997024a68be6241e3a70a6f05a338e
https://github.com/llvm/llvm-project/commit/cc527d5399997024a68be6241e3a70a6f05a338e
Author: Nico Weber <thakis at chromium.org>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/utils/gn/secondary/lld/unittests/AsLibELF/BUILD.gn
Log Message:
-----------
[gn] port b3ed324d42c04 (#226570)
Commit: bbd2e0f7ce13d2a1ff8336018d3b034eb3c698a0
https://github.com/llvm/llvm-project/commit/bbd2e0f7ce13d2a1ff8336018d3b034eb3c698a0
Author: Jiaxun Yang <jiaxun.yang at flygoat.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/Target/Mips/MipsISelLowering.cpp
M llvm/test/CodeGen/Mips/extins.ll
Log Message:
-----------
[Mips] Enable generic bitfield extract preparation (#226491)
Enable CodeGenPrepare's shift sinking when the subtarget supports
bitfield extract instructions. This exposes shift-and-mask patterns
across basic blocks to the existing MIPS extract combine.
Use hasExtractInsert() to keep this disabled for pre-r2 targets and
MIPS16. Add a minimal cross-block regression case to extins.ll.
Commit: 5bc083e278a59853fcfcf3649ba7a20457ead1e5
https://github.com/llvm/llvm-project/commit/5bc083e278a59853fcfcf3649ba7a20457ead1e5
Author: Nico Weber <thakis at chromium.org>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/utils/gn/secondary/lld/unittests/AsLibELF/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/DebugInfo/LogicalView/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/DebugInfo/PDB/BUILD.gn
Log Message:
-----------
[gn] port b3ed324d42c04 more (#226574)
Commit: 0a21a0712b800a3cc1af87e1d0ceb1a84f2b24bd
https://github.com/llvm/llvm-project/commit/0a21a0712b800a3cc1af87e1d0ceb1a84f2b24bd
Author: Patrick Rachford <pat at modular.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/MC/WasmObjectWriter.cpp
M llvm/test/MC/WebAssembly/reloc-pic64.s
Log Message:
-----------
[WebAssembly] Emit i64 GOT import globals on wasm64 (#226326)
WasmObjectWriter hardcodes the synthetic GOT import globals
(GOT.mem/GOT.func) to i32, but on wasm64 they hold 64-bit addresses, so
the object is type-invalid against the i64 global.get that consumes
them. wasm-ld already emits i64 GOT imports on wasm64, so this aligns
the object writer with the linker: the import type is gated on
is64Bit(), and the reloc-pic64 expectations are updated. The wasm32
checks are unchanged.
Commit: 229e7000493f118d49d23073d3bfa613b3798d85
https://github.com/llvm/llvm-project/commit/229e7000493f118d49d23073d3bfa613b3798d85
Author: Marcos Ramirez Joos <mramirezjoos.oss at proton.me>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M libc/src/__support/FPUtil/FEnvImpl.h
Log Message:
-----------
[libc] Avoid system fenv.h in FEnvImpl.h when LIBC_MATH_HAS_NO_EXCEPT is set (#224384)
The warning being added under #199009 triggers errors in subprojects
(e.g., flang) using libc headers that gate the use of `#pragma STDC
FENV_ACCESS ON` on the internal libc
`LIBC_COMPILER_HAS_STDC_FENV_ACCESS` flag, when building under
`-Wfenv-access -Werror`. As the idea is for these subprojects to not
access the libc FP environment (see
https://github.com/llvm/llvm-project/pull/199009#issuecomment-5299119396),
gating the use of system fenv.h functions on the
`LIBC_MATH_HAS_NO_EXCEPT` flag avoids having to specify the
`LIBC_COMPILER_HAS_STDC_FENV_ACCESS` flag when building them.
The three line removals are a clean-up related to
https://github.com/llvm/llvm-project/pull/200268. These uses are
redundant as the called functions already use the pragma when
appropriate.
Commit: 7ca0ce59bb82557a3052666562cc8f0d6d03ec41
https://github.com/llvm/llvm-project/commit/7ca0ce59bb82557a3052666562cc8f0d6d03ec41
Author: Finn Plummer <mail at inbelic.dev>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/Target/DirectX/DXILOpBuilder.cpp
M llvm/test/CodeGen/DirectX/LoadInput.ll
M llvm/test/CodeGen/DirectX/StoreOutput.ll
Log Message:
-----------
[DirectX] Preserve all shader-stage bits during DXIL op lowering (#225874)
The vertex-stage bit is above bit 15 and was lost when the mask was
narrowed to uint16_t. This would cause an incorrect lowering error:
https://godbolt.org/z/rEMj8ssK9.
Corrected by keeping it as a 32 bit value.
Assisted by: ChatGPT 6 Astra
Commit: 44c84768990686eb1e24b4d1dcbd13fff37442bb
https://github.com/llvm/llvm-project/commit/44c84768990686eb1e24b4d1dcbd13fff37442bb
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVExpandPseudoPostRA.cpp
M llvm/lib/Target/RISCV/RISCVExpandPseudoPreEmit.cpp
M llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
M llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
M llvm/lib/Target/RISCV/RISCVLoadStoreOptimizer.cpp
M llvm/lib/Target/RISCV/RISCVZilsdOptimizer.cpp
Log Message:
-----------
[RISCV] Replace uses of RegState::Define. NFC (#226569)
Either pass the destination register to the BuildMI call or use addDef
if there are multiple defs or other flags are set.
Commit: 19d72fd6deab2ea3addd8b945807abd02b1bbb70
https://github.com/llvm/llvm-project/commit/19d72fd6deab2ea3addd8b945807abd02b1bbb70
Author: Kerry McLaughlin <kerry.mclaughlin at arm.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M clang/lib/CodeGen/TargetBuiltins/ARM.cpp
M clang/lib/Sema/SemaARM.cpp
M llvm/include/llvm/Support/AArch64MemoryHints.h
M llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
Log Message:
-----------
[AArch64] Rename memory hints to avoid clash with arm_acle.h macros (#226432)
Renames the hints in AArch64MemoryHints.h, as HINT_STSHH_KEEP and
HINT_STSHH_STRM are already defined in arm_acle.h.
Commit: e76dd51398a8ceac33e9e5bf3253dd6b03b965dd
https://github.com/llvm/llvm-project/commit/e76dd51398a8ceac33e9e5bf3253dd6b03b965dd
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
A llvm/test/Transforms/SLPVectorizer/RISCV/trimmed-node-matching-gather.ll
Log Message:
-----------
[SLP][NFC]ADd a test with the missed vectorization, NFC
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/226581
Commit: d506ee743cdaef27448964890f813bd3b7da7953
https://github.com/llvm/llvm-project/commit/d506ee743cdaef27448964890f813bd3b7da7953
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/RISCV/trimmed-node-matching-gather.ll
Log Message:
-----------
[SLP]Reuse the trimmed nodes in the perfectly matched gathers of the same user
The gather node, perfectly matching the node of the same user
transformed to gather during throttling, did not treat this node as a
reuse source, and was costed and emitted as a separate buildvector.
Fixes #219030
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/226582
Commit: 4462816180ebabba0e44bc14d98403785dfa91f6
https://github.com/llvm/llvm-project/commit/4462816180ebabba0e44bc14d98403785dfa91f6
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M .github/workflows/libcxx-benchmark-commit.yml
M .github/workflows/libcxx-benchmark-cron.yml
M .github/workflows/libcxx-pr-benchmark.yml
M .github/workflows/sycl-tests.yml
M clang/docs/LifetimeSafety.md
M clang/docs/ReleaseNotes.md
M clang/docs/SourceBasedCodeCoverage.md
M clang/include/clang/Basic/Builtins.td
M clang/include/clang/Basic/BuiltinsRISCV.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Basic/HLSLIntrinsics.td
M clang/include/clang/Basic/LangOptions.def
M clang/include/clang/CIR/Dialect/IR/CIRAttrs.td
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/include/clang/Interpreter/Interpreter.h
M clang/include/clang/Options/Options.td
M clang/lib/AST/ASTImporter.cpp
M clang/lib/Basic/Targets/WebAssembly.cpp
M clang/lib/Basic/Targets/WebAssembly.h
M clang/lib/CIR/CodeGen/CIRGenBuilder.h
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
M clang/lib/CodeGen/CGBlocks.cpp
M clang/lib/CodeGen/CGHLSLBuiltins.cpp
M clang/lib/CodeGen/CGHLSLRuntime.h
M clang/lib/CodeGen/CGLoopInfo.cpp
M clang/lib/CodeGen/TargetBuiltins/ARM.cpp
M clang/lib/CodeGen/TargetBuiltins/RISCV.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Headers/riscv_packed_simd.h
M clang/lib/Interpreter/Interpreter.cpp
M clang/lib/Lex/HeaderSearch.cpp
M clang/lib/Sema/SemaARM.cpp
M clang/lib/Sema/SemaHLSL.cpp
M clang/lib/Sema/SemaOpenMP.cpp
M clang/lib/Serialization/ASTWriterStmt.cpp
M clang/test/Analysis/Scalable/ssaf-src-edit-merge/conflict-preserves-unrelated-zero-length-insert.test
M clang/test/Analysis/Scalable/ssaf-src-edit-merge/conflict-stderr-without-sarif.test
M clang/test/Analysis/Scalable/ssaf-src-edit-merge/empty-input.test
M clang/test/Analysis/Scalable/ssaf-src-edit-merge/identical-overlap.test
M clang/test/Analysis/Scalable/ssaf-src-edit-merge/no-conflict-sarif-empty.test
M clang/test/Analysis/Scalable/ssaf-src-edit-merge/non-overlapping.test
M clang/test/Analysis/Scalable/ssaf-src-edit-merge/order-invariance.test
M clang/test/Analysis/Scalable/ssaf-src-edit-merge/parent-dir-missing.test
M clang/test/Analysis/Scalable/ssaf-src-edit-merge/pre-dedup-identical-non-zero-length.test
M clang/test/Analysis/Scalable/ssaf-src-edit-merge/pre-dedup-zero-length-insert.test
M clang/test/Analysis/Scalable/ssaf-src-edit-merge/range-overlap-cluster-of-three-sarif.test
M clang/test/Analysis/Scalable/ssaf-src-edit-merge/range-overlap-conflict-sarif.test
M clang/test/Analysis/Scalable/ssaf-src-edit-merge/sarif-out-parent-dir-missing.test
M clang/test/Analysis/Scalable/ssaf-src-edit-merge/single-input-internal-conflict.test
M clang/test/Analysis/Scalable/ssaf-src-edit-merge/single-input.test
M clang/test/Analysis/Scalable/ssaf-src-edit-merge/three-input-all-conflict.test
M clang/test/Analysis/Scalable/ssaf-src-edit-merge/three-input-conflict-sarif.test
M clang/test/Analysis/Scalable/ssaf-src-edit-merge/two-conflicts-different-offsets-sarif.test
M clang/test/Analysis/Scalable/ssaf-src-edit-merge/two-input-conflict-sarif.test
M clang/test/Analysis/Scalable/ssaf-src-edit-merge/two-input-conflict.test
M clang/test/CIR/IR/enum-attrs.cir
M clang/test/CIR/Lowering/call-llvm-intrinsic.cir
A clang/test/ClangScanDeps/modules-context-hash-case-sensitive-vfs-paths.c
M clang/test/ClangScanDeps/modules-context-hash-module-map-path.c
R clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_len.c
M clang/test/CodeGen/AArch64/sve/len.c
M clang/test/CodeGen/RISCV/rvp-intrinsics.c
M clang/test/CodeGen/align-loops.c
M clang/test/CodeGen/thread-model.c
M clang/test/CodeGenCXX/static-init-wasm.cpp
A clang/test/CodeGenHLSL/builtins/WaveReadLaneFirst.hlsl
A clang/test/Driver/flifetime-safety-c.c
A clang/test/Interpreter/HIP/hip-environment.hip
A clang/test/Interpreter/HIP/lit.local.cfg
A clang/test/Modules/implicit-module-map-path-case-sensitive.c
A clang/test/OpenMP/for_loop_bitint_messages.c
M clang/test/Preprocessor/init.c
M clang/test/Sema/LifetimeSafety/annotation-suggestions-fixits.c
M clang/test/Sema/LifetimeSafety/safety-c.c
A clang/test/SemaHLSL/BuiltIns/WaveReadLaneFirst-errors.hlsl
M clang/test/SemaHLSL/WaveBuiltinAvailability.hlsl
M clang/test/lit.cfg.py
M clang/tools/clang-repl/ClangRepl.cpp
M clang/unittests/Lex/LexerTest.cpp
M compiler-rt/include/profile/instr_prof_interface.h
M compiler-rt/lib/profile/InstrProfiling.h
M compiler-rt/test/profile/instrprof-api.c
M flang/lib/Semantics/check-omp-structure.cpp
M flang/lib/Semantics/check-omp-structure.h
M flang/lib/Semantics/check-omp-syntax.cpp
M flang/lib/Semantics/check-omp-variant.cpp
M libc/src/__support/FPUtil/FEnvImpl.h
M libc/src/__support/math/bf16sub.h
M libc/src/__support/math/bf16subf.h
M libc/src/__support/math/bf16subf128.h
M libc/src/__support/math/lgammaf.h
M libc/test/shared/shared_math_constexpr_test.cpp
M libcxx/test/benchmarks/containers/string.bench.cpp
M libcxx/utils/ci/lnt/README.md
M libcxx/utils/ci/lnt/machines.json
M libcxx/utils/ci/lnt/run-benchmarks
M libcxx/utils/ci/run-buildbot
M lld/test/Unit/lit.cfg.py
M lld/unittests/AsLibELF/CMakeLists.txt
M lld/unittests/AsLibELF/OutputStream.cpp
M lld/unittests/AsLibELF/ROCm.cpp
M lldb/include/lldb/Target/DynamicRegisterInfo.h
M lldb/packages/Python/lldbsuite/test/tools/lldb_dap/session_helpers.py
M lldb/source/Target/DynamicRegisterInfo.cpp
M lldb/test/API/python_api/value/TestValueAPI.py
M lldb/tools/lldb-dap/Handler/ThreadsRequestHandler.cpp
M llvm/docs/LangRef.md
M llvm/docs/ReleaseNotes.md
M llvm/include/llvm-c/Core.h
M llvm/include/llvm/Analysis/InstSimplifyFolder.h
M llvm/include/llvm/Analysis/TargetFolder.h
M llvm/include/llvm/Analysis/TargetTransformInfo.h
M llvm/include/llvm/AsmParser/LLParser.h
M llvm/include/llvm/AsmParser/LLToken.h
M llvm/include/llvm/Bitcode/LLVMBitCodes.h
M llvm/include/llvm/CodeGen/BasicTTIImpl.h
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/include/llvm/IR/ConstantFolder.h
M llvm/include/llvm/IR/IRBuilder.h
M llvm/include/llvm/IR/IRBuilderFolder.h
M llvm/include/llvm/IR/InstVisitor.h
M llvm/include/llvm/IR/Instruction.def
M llvm/include/llvm/IR/Instructions.h
M llvm/include/llvm/IR/IntrinsicsDirectX.td
M llvm/include/llvm/IR/IntrinsicsRISCV.td
M llvm/include/llvm/IR/IntrinsicsSPIRV.td
M llvm/include/llvm/IR/NoFolder.h
M llvm/include/llvm/Support/AArch64MemoryHints.h
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/Passes/LoadStoreVec.h
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/VecUtils.h
M llvm/lib/AsmParser/LLLexer.cpp
M llvm/lib/AsmParser/LLParser.cpp
M llvm/lib/Bitcode/Reader/BitcodeReader.cpp
M llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
M llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/lib/CodeGen/TargetLoweringBase.cpp
M llvm/lib/IR/AsmWriter.cpp
M llvm/lib/IR/Core.cpp
M llvm/lib/IR/Instruction.cpp
M llvm/lib/IR/Instructions.cpp
M llvm/lib/IR/RuntimeLibcalls.cpp
M llvm/lib/IR/Verifier.cpp
M llvm/lib/MC/GOFFObjectWriter.cpp
M llvm/lib/MC/WasmObjectWriter.cpp
M llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64PTrueCoalescing.cpp
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPU.h
M llvm/lib/Target/AMDGPU/AMDGPUMachineFunctionInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/CMakeLists.txt
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp
A llvm/lib/Target/AMDGPU/SIPostRA16BitMovFolding.cpp
M llvm/lib/Target/ARM/ARMISelLowering.cpp
M llvm/lib/Target/DirectX/DXIL.td
M llvm/lib/Target/DirectX/DXILOpBuilder.cpp
M llvm/lib/Target/DirectX/DXILShaderFlags.cpp
M llvm/lib/Target/Mips/MipsISelLowering.cpp
M llvm/lib/Target/Mips/MipsSubtarget.cpp
M llvm/lib/Target/Mips/MipsSubtarget.h
M llvm/lib/Target/RISCV/RISCVExpandPseudoPostRA.cpp
M llvm/lib/Target/RISCV/RISCVExpandPseudoPreEmit.cpp
M llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoP.td
M llvm/lib/Target/RISCV/RISCVLoadStoreOptimizer.cpp
M llvm/lib/Target/RISCV/RISCVProcessors.td
M llvm/lib/Target/RISCV/RISCVSubtarget.h
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/lib/Target/RISCV/RISCVZilsdOptimizer.cpp
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
M llvm/lib/Target/SystemZ/SystemZFrameLowering.cpp
M llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyCoalesceFeaturesAndStripAtomics.cpp
M llvm/lib/TargetParser/AArch64TargetParser.cpp
M llvm/lib/TargetParser/Triple.cpp
M llvm/lib/Transforms/Utils/SimplifyCFG.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPCompatibilityAnalysis.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPCostAnalysis.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPUtils.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPUtils.h
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/Passes/LoadStoreVec.cpp
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/VecUtils.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanHelpers.h
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanValue.h
M llvm/test/Analysis/CostModel/AArch64/masked_ldst.ll
M llvm/test/Analysis/CostModel/AArch64/sve-arith.ll
M llvm/test/Analysis/CostModel/AArch64/sve-ldst.ll
M llvm/test/Analysis/CostModel/RISCV/vp-intrinsics.ll
M llvm/test/Analysis/IR2Vec/Inputs/reference_default_vocab_print.txt
M llvm/test/Analysis/IR2Vec/Inputs/reference_wtd1_vocab_print.txt
M llvm/test/Analysis/IR2Vec/Inputs/reference_wtd2_vocab_print.txt
A llvm/test/Assembler/bitinsert-bitextract-invalid.ll
A llvm/test/Assembler/bitinsert-bitextract.ll
M llvm/test/Bitcode/compatibility.ll
A llvm/test/CodeGen/AArch64/bitinsert-bitextract-common-offsets.ll
A llvm/test/CodeGen/AArch64/bitinsert-bitextract-fp.ll
A llvm/test/CodeGen/AArch64/bitinsert-bitextract.ll
M llvm/test/CodeGen/AArch64/insert-subvector-res-legalization.ll
M llvm/test/CodeGen/AArch64/llvm-ir-to-intrinsic.ll
M llvm/test/CodeGen/AArch64/masked-srem-scalable.ll
M llvm/test/CodeGen/AArch64/masked-urem-scalable.ll
M llvm/test/CodeGen/AArch64/sve-bf16-combines.ll
M llvm/test/CodeGen/AArch64/sve-bf16-int-converts.ll
M llvm/test/CodeGen/AArch64/sve-bitcast.ll
M llvm/test/CodeGen/AArch64/sve-fpext-load.ll
M llvm/test/CodeGen/AArch64/sve-int-arith.ll
M llvm/test/CodeGen/AArch64/sve-ld1-addressing-mode-reg-imm.ll
M llvm/test/CodeGen/AArch64/sve-load-store-legalisation.ll
M llvm/test/CodeGen/AArch64/sve-lsrchain.ll
M llvm/test/CodeGen/AArch64/sve-partial-reduce-dot-product.ll
M llvm/test/CodeGen/AArch64/sve-partial-reduce-wide-add.ll
M llvm/test/CodeGen/AArch64/sve-pred-selectop2.ll
M llvm/test/CodeGen/AArch64/sve-shift-trunc-combine.ll
M llvm/test/CodeGen/AArch64/sve-st1-addressing-mode-reg-imm.ll
M llvm/test/CodeGen/AArch64/vec-combine-compare-to-bitmask.ll
M llvm/test/CodeGen/AArch64/vector-absolute-difference.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-phis-no-lane-mask-merging.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-used-outside-loop.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-structurizer.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-i1.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/merge-values-s16-true16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/usubsat.ll
M llvm/test/CodeGen/AMDGPU/add.v2i16.ll
M llvm/test/CodeGen/AMDGPU/add_sub_u64_pseudos.mir
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.32bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.48bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.64bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll
A llvm/test/CodeGen/AMDGPU/bitinsert-bitextract-common-offsets.ll
A llvm/test/CodeGen/AMDGPU/bitinsert-bitextract-fp.ll
A llvm/test/CodeGen/AMDGPU/bitinsert-bitextract.ll
M llvm/test/CodeGen/AMDGPU/block-should-not-be-in-alive-blocks.mir
M llvm/test/CodeGen/AMDGPU/branch-folding-implicit-def-subreg.ll
M llvm/test/CodeGen/AMDGPU/collapse-endcf.mir
M llvm/test/CodeGen/AMDGPU/divergent-branch-uniform-condition.ll
M llvm/test/CodeGen/AMDGPU/flat-saddr-load.ll
M llvm/test/CodeGen/AMDGPU/i1-copy-from-loop.ll
M llvm/test/CodeGen/AMDGPU/insert-waitcnts-merge.ll
A llvm/test/CodeGen/AMDGPU/lds-dynamic-direct-and-indirect-use.ll
M llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll
M llvm/test/CodeGen/AMDGPU/llc-pipeline.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.gather4.a16.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.msaa.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.a16.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.g16.encode.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.g16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.waitcnt.out.order.ll
M llvm/test/CodeGen/AMDGPU/loop_break.ll
M llvm/test/CodeGen/AMDGPU/lower-control-flow-live-intervals.mir
M llvm/test/CodeGen/AMDGPU/lower-control-flow-live-variables-update.mir
M llvm/test/CodeGen/AMDGPU/lower-control-flow-other-terminators.mir
M llvm/test/CodeGen/AMDGPU/mad-mix-hi-bf16.ll
M llvm/test/CodeGen/AMDGPU/repeated-divisor.ll
M llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll
M llvm/test/CodeGen/AMDGPU/sgpr-scavenge-fi-stack-id.ll
M llvm/test/CodeGen/AMDGPU/si-lower-control-flow-remove-redundant-block-liveintervals.mir
M llvm/test/CodeGen/AMDGPU/si-lower-control-flow.mir
A llvm/test/CodeGen/AMDGPU/si-post-ra-merge-v-mov-b16.mir
M llvm/test/CodeGen/AMDGPU/sub.v2i16.ll
M llvm/test/CodeGen/AMDGPU/transform-block-with-return-to-epilog.ll
M llvm/test/CodeGen/AMDGPU/v_swap_b16.ll
M llvm/test/CodeGen/AMDGPU/vector_shuffle.packed.ll
A llvm/test/CodeGen/ARM/bitinsert-bitextract-common-offsets.ll
A llvm/test/CodeGen/ARM/bitinsert-bitextract-fp.ll
A llvm/test/CodeGen/ARM/bitinsert-bitextract.ll
M llvm/test/CodeGen/DirectX/LoadInput.ll
A llvm/test/CodeGen/DirectX/LongVector/wave-readlane-first.ll
M llvm/test/CodeGen/DirectX/ShaderFlags/wave-ops.ll
M llvm/test/CodeGen/DirectX/StoreOutput.ll
A llvm/test/CodeGen/DirectX/WaveReadLaneFirst.ll
A llvm/test/CodeGen/DirectX/WaveReadLaneFirst_mat.ll
M llvm/test/CodeGen/LoongArch/pr177863.ll
M llvm/test/CodeGen/Mips/extins.ll
A llvm/test/CodeGen/PowerPC/bitinsert-bitextract-common-offsets.ll
A llvm/test/CodeGen/PowerPC/bitinsert-bitextract-fp.ll
A llvm/test/CodeGen/PowerPC/bitinsert-bitextract.ll
A llvm/test/CodeGen/RISCV/bitinsert-bitextract-common-offsets.ll
A llvm/test/CodeGen/RISCV/bitinsert-bitextract-fp.ll
A llvm/test/CodeGen/RISCV/bitinsert-bitextract.ll
M llvm/test/CodeGen/RISCV/rvp-simd-32.ll
M llvm/test/CodeGen/RISCV/rvp-simd-64.ll
A llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_long_vector/wave-readlane-first.ll
A llvm/test/CodeGen/SPIRV/hlsl-intrinsics/WaveReadLaneFirst.ll
A llvm/test/CodeGen/SPIRV/hlsl-intrinsics/WaveReadLaneFirst_mat.ll
M llvm/test/CodeGen/SystemZ/atomicrmw-fadd-04.ll
M llvm/test/CodeGen/SystemZ/cmpxchg-01.ll
M llvm/test/CodeGen/SystemZ/cmpxchg-02.ll
A llvm/test/CodeGen/SystemZ/dead-cc-defs.ll
M llvm/test/CodeGen/SystemZ/zos-section-1.ll
M llvm/test/CodeGen/SystemZ/zos-section-2.ll
M llvm/test/CodeGen/SystemZ/zos-symbol-2.ll
R llvm/test/CodeGen/WebAssembly/coalesce-features-thread-model.ll
A llvm/test/CodeGen/X86/GlobalISel/bitinsert-bitextract.ll
A llvm/test/CodeGen/X86/bitinsert-bitextract-common-offsets.ll
A llvm/test/CodeGen/X86/bitinsert-bitextract-fp.ll
A llvm/test/CodeGen/X86/bitinsert-bitextract.ll
A llvm/test/CodeGen/X86/vec_setcc-3.ll
M llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-vmax.ll
M llvm/test/MC/WebAssembly/reloc-pic64.s
M llvm/test/Transforms/LoopStrengthReduce/AArch64/vscale-fixups.ll
M llvm/test/Transforms/LoopVectorize/AArch64/early_exit_costs.ll
M llvm/test/Transforms/LoopVectorize/AArch64/force-scalable-vectorization-always.ll
M llvm/test/Transforms/LoopVectorize/AArch64/invalid-costs.ll
M llvm/test/Transforms/LoopVectorize/AArch64/scalable-alloca.ll
M llvm/test/Transforms/LoopVectorize/AArch64/scalable-call.ll
M llvm/test/Transforms/LoopVectorize/AArch64/scalable-vectorization-cost-tuning.ll
M llvm/test/Transforms/LoopVectorize/AArch64/simple_early_exit.ll
M llvm/test/Transforms/LoopVectorize/AArch64/single-early-exit-interleave.ll
M llvm/test/Transforms/LoopVectorize/RISCV/early-exit-live-out.ll
M llvm/test/Transforms/LoopVectorize/RISCV/sink-to-early-exit.ll
M llvm/test/Transforms/LoopVectorize/VPlan/execution-frequencies-match-bfi.ll
M llvm/test/Transforms/LoopVectorize/VPlan/uncountable-early-exit-vplan.ll
M llvm/test/Transforms/LoopVectorize/X86/predicated-instruction-cost.ll
M llvm/test/Transforms/LoopVectorize/dereferenceable-info-from-assumption-constant-size.ll
M llvm/test/Transforms/LoopVectorize/early-exit-calls.ll
M llvm/test/Transforms/LoopVectorize/early-exit-live-out-extract-lane.ll
M llvm/test/Transforms/LoopVectorize/early-exit-load-live-out.ll
M llvm/test/Transforms/LoopVectorize/early-exit-unary-ops.ll
M llvm/test/Transforms/LoopVectorize/multiple-early-exits.ll
M llvm/test/Transforms/LoopVectorize/predicated-early-exits-interleave.ll
M llvm/test/Transforms/LoopVectorize/predicated-multiple-exits.ll
M llvm/test/Transforms/LoopVectorize/predicated-single-exit.ll
M llvm/test/Transforms/LoopVectorize/replicate-region-branch-weights.ll
M llvm/test/Transforms/LoopVectorize/single-early-exit-cond-poison.ll
M llvm/test/Transforms/LoopVectorize/single-early-exit-deref-assumptions.ll
M llvm/test/Transforms/LoopVectorize/single-early-exit-interleave-only.ll
M llvm/test/Transforms/LoopVectorize/single-early-exit-interleave.ll
M llvm/test/Transforms/LoopVectorize/single_early_exit.ll
M llvm/test/Transforms/LoopVectorize/single_early_exit_live_outs.ll
M llvm/test/Transforms/LoopVectorize/sink-to-early-exit.ll
M llvm/test/Transforms/LoopVectorize/vector-loop-backedge-elimination-early-exit.ll
M llvm/test/Transforms/LoopVectorize/vector-loop-backedge-elimination-predicated-early-exit.ll
R llvm/test/Transforms/PGOProfile/Inputs/indirect_call.proftext
M llvm/test/Transforms/PGOProfile/indirect_call_annotation.ll
A llvm/test/Transforms/SLPVectorizer/RISCV/trimmed-node-matching-gather.ll
A llvm/test/Transforms/SimplifyCFG/fold-branch-to-common-dest-call-debugloc.ll
A llvm/test/Transforms/Util/DeclareRuntimeLibcalls/divmod.ll
A llvm/test/Verifier/bitextract-bitinsert-invalid-verifier.ll
A llvm/test/tools/llubi/main_declaration.ll
M llvm/test/tools/llvm-ir2vec/entities.ll
M llvm/test/tools/llvm-ir2vec/triplets.ll
M llvm/test/tools/llvm-objdump/MachO/AArch64/macho-arm64-subtypes.test
M llvm/test/tools/llvm-objdump/MachO/universal-arm64.test
M llvm/tools/llubi/llubi.cpp
M llvm/tools/llvm-c-test/echo.cpp
M llvm/unittests/Analysis/IR2VecTest.cpp
M llvm/utils/gn/secondary/clang/tools/driver/BUILD.gn
M llvm/utils/gn/secondary/lld/unittests/AsLibELF/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/Target/AMDGPU/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/DebugInfo/LogicalView/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/DebugInfo/PDB/BUILD.gn
M mlir/include/mlir-c/Rewrite.h
M mlir/include/mlir/Dialect/Vector/Transforms/VectorTransforms.h
M mlir/include/mlir/IR/BuiltinDialect.td
M mlir/include/mlir/IR/BuiltinOps.td
M mlir/lib/CAPI/Transforms/Rewrite.cpp
M mlir/lib/Dialect/Vector/Transforms/VectorMaskElimination.cpp
M mlir/test/CAPI/CMakeLists.txt
M mlir/test/CAPI/rewrite.c
M mlir/test/Dialect/Vector/eliminate-masks.mlir
M mlir/test/IR/module-op.mlir
A mlir/test/Integration/Dialect/XeGPU/WG/simple_gemm_bf16.mlir
R mlir/test/Integration/Dialect/XeGPU/WG/simple_mxfp_gemm.mlir
A mlir/test/Integration/Dialect/XeGPU/WG/simple_mxfp_gemm_F4.mlir
A mlir/test/Integration/Dialect/XeGPU/WG/simple_mxfp_gemm_F8.mlir
M mlir/test/Integration/Dialect/XeGPU/WG/simple_mxfp_gemm_dequantizeB_F4.mlir
A mlir/test/Integration/Dialect/XeGPU/WG/simple_mxfp_gemm_dequantizeB_F8.mlir
M mlir/test/Integration/Dialect/XeGPU/WG/simple_mxfp_gemm_quantizeA_F4.mlir
A mlir/test/Integration/Dialect/XeGPU/WG/simple_mxfp_gemm_quantizeA_F8.mlir
M mlir/test/Transforms/sccp-callgraph.mlir
M mlir/test/Transforms/test-symbol-dce.mlir
M mlir/test/lib/Dialect/Vector/TestVectorTransforms.cpp
M mlir/test/python/dialects/ml_program.py
M orc-rt/include/orc-rt/bedrock/BootstrapInfo.h
M orc-rt/include/orc-rt/support/move_only_function.h
M orc-rt/lib/bedrock/BootstrapInfo.cpp
M orc-rt/test/unit/support/move_only_function-test.cpp
M polly/lib/Analysis/ScopBuilder.cpp
M polly/test/ScopInfo/issue190128.ll
M polly/test/ScopInfo/simple_loop_unsigned.ll
A polly/test/ScopInfo/user-assumption-cached-precondition.ll
A polly/test/ScopInfo/zext-loop-bound-unbounded.ll
M utils/bazel/llvm-project-overlay/lldb/BUILD.bazel
Log Message:
-----------
Rebase, address comments, improvements
Created using spr 1.3.7
Compare: https://github.com/llvm/llvm-project/compare/4cbd65ab18f2...4462816180eb
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