[all-commits] [llvm/llvm-project] 07aec2: [AMDGPU] merge 16bit mov pairs in post-RA peephole...

[Guo Chen via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 07aec21c88f48907b5da1d42f4522e106d30a9f1
      https://github.com/llvm/llvm-project/commit/07aec21c88f48907b5da1d42f4522e106d30a9f1
  Author: Guo Chen <guochen2 at amd.com>
  Date:   2026-09-25 (Fri, 25 Sep 2026)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPU.h
    M llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
    M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
    M llvm/lib/Target/AMDGPU/CMakeLists.txt
    A llvm/lib/Target/AMDGPU/SIPostRA16BitMovFolding.cpp
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/merge-values-s16-true16.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/usubsat.ll
    M llvm/test/CodeGen/AMDGPU/add.v2i16.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.32bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.48bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.64bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll
    M llvm/test/CodeGen/AMDGPU/flat-saddr-load.ll
    M llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll
    M llvm/test/CodeGen/AMDGPU/llc-pipeline.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.gather4.a16.dim.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.msaa.load.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.a16.dim.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.g16.encode.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.g16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.waitcnt.out.order.ll
    M llvm/test/CodeGen/AMDGPU/mad-mix-hi-bf16.ll
    M llvm/test/CodeGen/AMDGPU/repeated-divisor.ll
    M llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll
    A llvm/test/CodeGen/AMDGPU/si-post-ra-merge-v-mov-b16.mir
    M llvm/test/CodeGen/AMDGPU/sub.v2i16.ll
    M llvm/test/CodeGen/AMDGPU/v_swap_b16.ll
    M llvm/test/CodeGen/AMDGPU/vector_shuffle.packed.ll

  Log Message:
  -----------
  [AMDGPU] merge 16bit mov pairs in post-RA peephole  (#208625)

Address https://github.com/llvm/llvm-project/issues/207011. Add 5
patterns to merge 16bit mov pairs.

Since we hoist instruction which might cross the waitcnt boundary,
insert a new pass before waitcnt for this transformation

Co-Authored-By: Claude



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