[all-commits] [llvm/llvm-project] 378ceb: [RISCV][P-Ext] Add builtins and IR intrinsics for ...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 378ceb307bbc729bb918601a28c468df419b4d34
      https://github.com/llvm/llvm-project/commit/378ceb307bbc729bb918601a28c468df419b4d34
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2026-09-25 (Fri, 25 Sep 2026)

  Changed paths:
    M clang/include/clang/Basic/BuiltinsRISCV.td
    M clang/lib/CodeGen/TargetBuiltins/RISCV.cpp
    M clang/lib/Headers/riscv_packed_simd.h
    M clang/test/CodeGen/RISCV/rvp-intrinsics.c
    M llvm/include/llvm/IR/IntrinsicsRISCV.td
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfoP.td
    M llvm/test/CodeGen/RISCV/rvp-simd-32.ll
    M llvm/test/CodeGen/RISCV/rvp-simd-64.ll

  Log Message:
  -----------
  [RISCV][P-Ext] Add builtins and IR intrinsics for packed shifts. (#225968)

The packed shift instructions use 5-bit shift amounts regardless of
element width. The C intrinsic should match this which means we can't
use C shift operators to implement them.

Rename RISCVISD::PSHL to RISCVISD::PSLL.



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