[all-commits] [llvm/llvm-project] 675c1c: [LLVM][CodeGen] Enable the AArch64PTrueCoalescing ...

[Paul Walker via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 675c1cfa5d925232db882942674a40de41654bc5
      https://github.com/llvm/llvm-project/commit/675c1cfa5d925232db882942674a40de41654bc5
  Author: Paul Walker <paul.walker at arm.com>
  Date:   2026-09-25 (Fri, 25 Sep 2026)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64PTrueCoalescing.cpp
    M llvm/test/CodeGen/AArch64/insert-subvector-res-legalization.ll
    M llvm/test/CodeGen/AArch64/llvm-ir-to-intrinsic.ll
    M llvm/test/CodeGen/AArch64/masked-srem-scalable.ll
    M llvm/test/CodeGen/AArch64/masked-urem-scalable.ll
    M llvm/test/CodeGen/AArch64/sve-bf16-combines.ll
    M llvm/test/CodeGen/AArch64/sve-bf16-int-converts.ll
    M llvm/test/CodeGen/AArch64/sve-bitcast.ll
    M llvm/test/CodeGen/AArch64/sve-fpext-load.ll
    M llvm/test/CodeGen/AArch64/sve-ld1-addressing-mode-reg-imm.ll
    M llvm/test/CodeGen/AArch64/sve-load-store-legalisation.ll
    M llvm/test/CodeGen/AArch64/sve-lsrchain.ll
    M llvm/test/CodeGen/AArch64/sve-partial-reduce-dot-product.ll
    M llvm/test/CodeGen/AArch64/sve-partial-reduce-wide-add.ll
    M llvm/test/CodeGen/AArch64/sve-pred-selectop2.ll
    M llvm/test/CodeGen/AArch64/sve-shift-trunc-combine.ll
    M llvm/test/CodeGen/AArch64/sve-st1-addressing-mode-reg-imm.ll
    M llvm/test/CodeGen/AArch64/vec-combine-compare-to-bitmask.ll
    M llvm/test/CodeGen/AArch64/vector-absolute-difference.ll
    M llvm/test/Transforms/LoopStrengthReduce/AArch64/vscale-fixups.ll

  Log Message:
  -----------
  [LLVM][CodeGen] Enable the AArch64PTrueCoalescing pass. (#225830)

Fixes https://github.com/llvm/llvm-project/issues/137040



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