[all-commits] [llvm/llvm-project] 389781: [AArch64][CostModel] Consider some nxv1 operations...

[Gaëtan Bossu via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 3897817145ffa3204e2593cb0b26c535724221c2
      https://github.com/llvm/llvm-project/commit/3897817145ffa3204e2593cb0b26c535724221c2
  Author: Gaëtan Bossu <gaetan.bossu at arm.com>
  Date:   2026-09-25 (Fri, 25 Sep 2026)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
    M llvm/test/Analysis/CostModel/AArch64/masked_ldst.ll
    M llvm/test/Analysis/CostModel/AArch64/sve-arith.ll
    M llvm/test/Analysis/CostModel/AArch64/sve-ldst.ll
    M llvm/test/CodeGen/AArch64/sve-int-arith.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/force-scalable-vectorization-always.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/invalid-costs.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/scalable-alloca.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/scalable-call.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/scalable-vectorization-cost-tuning.ll

  Log Message:
  -----------
  [AArch64][CostModel] Consider some nxv1 operations as legal (#214471)

This is allowing some operations on vscale x 1 types, namely:
 - load/store
 - masked load/store
 - arithmetic instructions like add/sub/mul

For those, there is already codegen coverage. See e.g.
 - llvm/test/CodeGen/AArch64/sve-int-arith.ll
 - llvm/test/CodeGen/AArch64/sve-load-store-legalisation.ll
 - llvm/test/CodeGen/AArch64/sve-masked-gather.ll
 - llvm/test/CodeGen/AArch64/sve-masked-scatter.ll

These types are relevant for enabling REVEC in LoopVectorizer. For
AArch64, the main target there is turning NEON vector sizes into SVE
vector size, i.e. using VF = "vscale x 1". For loops with mixed vector
and scalar types, we'll want to allow vectorising scalar types with such
a VF.



To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications