[all-commits] [llvm/llvm-project] 52cb4d: [AArch64][CostModel] Consider some nxv1 operations...

[Gaëtan Bossu via All-commits]

  Branch: refs/heads/users/gbossu/gbossu.nxv1.costs.2
  Home:   https://github.com/llvm/llvm-project
  Commit: 52cb4d978cb3e6ac17e8d3a6034567b3274a9618
      https://github.com/llvm/llvm-project/commit/52cb4d978cb3e6ac17e8d3a6034567b3274a9618
  Author: Gaëtan Bossu <gaetan.bossu at arm.com>
  Date:   2026-09-25 (Fri, 25 Sep 2026)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
    M llvm/test/Analysis/CostModel/AArch64/masked_ldst.ll
    M llvm/test/Analysis/CostModel/AArch64/sve-arith.ll
    M llvm/test/Analysis/CostModel/AArch64/sve-ldst.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/force-scalable-vectorization-always.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/invalid-costs.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/scalable-alloca.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/scalable-call.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/scalable-vectorization-cost-tuning.ll

  Log Message:
  -----------
  [AArch64][CostModel] Consider some nxv1 operations as legal

This is allowing some operations on vscale x 1 types, namely:
 - load/store
 - masked load/store
 - arithmetic instructions like add/sub/mul

For those, there is already codegen coverage. See e.g.
 - llvm/test/CodeGen/AArch64/sve-int-arith.ll
 - llvm/test/CodeGen/AArch64/sve-load-store-legalisation.ll
 - llvm/test/CodeGen/AArch64/sve-masked-gather.ll
 - llvm/test/CodeGen/AArch64/sve-masked-scatter.ll


  Commit: 0b8d349563d1138fa866126d352bfe124d0964e1
      https://github.com/llvm/llvm-project/commit/0b8d349563d1138fa866126d352bfe124d0964e1
  Author: Gaëtan Bossu <gaetan.bossu at arm.com>
  Date:   2026-09-25 (Fri, 25 Sep 2026)

  Changed paths:
    M llvm/test/Analysis/CostModel/AArch64/masked_ldst.ll

  Log Message:
  -----------
  Avoid new undef in IR


  Commit: 6fda624311af0cc32d95982560ed89a56545aca7
      https://github.com/llvm/llvm-project/commit/6fda624311af0cc32d95982560ed89a56545aca7
  Author: Gaëtan Bossu <gaetan.bossu at arm.com>
  Date:   2026-09-25 (Fri, 25 Sep 2026)

  Changed paths:
    M llvm/test/CodeGen/AArch64/sve-int-arith.ll

  Log Message:
  -----------
  Add explicit codegen tests for nxv1 mul and sub


  Commit: 057ffe9cf57592ce451085013bae7f83c522e813
      https://github.com/llvm/llvm-project/commit/057ffe9cf57592ce451085013bae7f83c522e813
  Author: Gaëtan Bossu <gaetan.bossu at arm.com>
  Date:   2026-09-25 (Fri, 25 Sep 2026)

  Changed paths:
    M llvm/test/CodeGen/AArch64/sve-int-arith.ll

  Log Message:
  -----------
  Avoid undefined ABI for add as well


  Commit: 6e04b95cfe18038ff20256c07e958978be270827
      https://github.com/llvm/llvm-project/commit/6e04b95cfe18038ff20256c07e958978be270827
  Author: Gaëtan Bossu <gaetan.bossu at arm.com>
  Date:   2026-09-25 (Fri, 25 Sep 2026)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp

  Log Message:
  -----------
  Check for full register predicate loads and stores first


Compare: https://github.com/llvm/llvm-project/compare/9ab3f84f3838...6e04b95cfe18

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