[all-commits] [llvm/llvm-project] a6fda0: [NFC] Moved getBitVecRegAntiHints from MachineRegi...

[Syadus Sefat via All-commits]

  Branch: refs/heads/users/mssefat/anti-hints-pr2-mir-serialize
  Home:   https://github.com/llvm/llvm-project
  Commit: a6fda0ada4c8b7d8a23c70d810696a3bf2655a2b
      https://github.com/llvm/llvm-project/commit/a6fda0ada4c8b7d8a23c70d810696a3bf2655a2b
  Author: mssefat <syadus.sefat at gmail.com>
  Date:   2026-09-24 (Thu, 24 Sep 2026)

  Changed paths:
    M llvm/include/llvm/CodeGen/MachineRegisterInfo.h
    M llvm/lib/CodeGen/AllocationOrder.cpp
    M llvm/lib/CodeGen/MachineRegisterInfo.cpp

  Log Message:
  -----------
  [NFC] Moved getBitVecRegAntiHints from MachineRegisterInfo to AllocationOrder


  Commit: 1b237056b463f2ec7c14dde96a4a8bda282c1046
      https://github.com/llvm/llvm-project/commit/1b237056b463f2ec7c14dde96a4a8bda282c1046
  Author: mssefat <syadus.sefat at gmail.com>
  Date:   2026-09-24 (Thu, 24 Sep 2026)

  Changed paths:
    M llvm/include/llvm/CodeGen/MachineRegisterInfo.h
    M llvm/lib/CodeGen/AllocationOrder.cpp
    M llvm/lib/CodeGen/MachineRegisterInfo.cpp

  Log Message:
  -----------
  Merge branch 'users/mssefat/anti-hints-pr1-infra' into users/mssefat/anti-hints-pr2-mir-serialize


Compare: https://github.com/llvm/llvm-project/compare/0e7db669bf3c...1b237056b463

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