[all-commits] [llvm/llvm-project] 6702fa: [NVPTX] Support 32-bit size operand for st.bulk (#...

[robertvirany via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 6702faa9c52cedeaad7d8f8fbc82be44cbc8f637
      https://github.com/llvm/llvm-project/commit/6702faa9c52cedeaad7d8f8fbc82be44cbc8f637
  Author: robertvirany <robertvirany at gmail.com>
  Date:   2026-09-24 (Thu, 24 Sep 2026)

  Changed paths:
    M llvm/docs/NVPTXUsage.md
    M llvm/include/llvm/IR/IntrinsicsNVVM.td
    M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
    M llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
    M llvm/test/CodeGen/NVPTX/st_bulk.ll
    A llvm/test/CodeGen/NVPTX/st_bulk_i32.ll
    M mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
    M mlir/lib/Target/LLVMIR/Dialect/NVVM/NVVMToLLVMIRTranslation.cpp
    M mlir/test/Dialect/LLVMIR/nvvm.mlir
    M mlir/test/Target/LLVMIR/nvvmir-invalid.mlir
    M mlir/test/Target/LLVMIR/nvvmir.mlir

  Log Message:
  -----------
  [NVPTX] Support 32-bit size operand for st.bulk (#217703)

PTX ISA 9.0 extends the `st.bulk` instruction to accept a 32-bit `size`
operand.

Add `i32` variants of the generic and `.shared::cta` NVVM intrinsics and
select them to `st.bulk` instructions using 32-bit registers. The new
patterns require PTX ISA 9.0 and `sm_100`.

The existing intrinsics continue to represent the original 64-bit forms.

Add code-generation coverage for both the default and short-pointer
ABIs.



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