[all-commits] [llvm/llvm-project] e637d7: [RISCV][TableGen] Return instruction size from isC...

[Sudharsan Veeravalli via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: e637d7d130f1be9ff06128db3007c69ca00bbaf5
      https://github.com/llvm/llvm-project/commit/e637d7d130f1be9ff06128db3007c69ca00bbaf5
  Author: Sudharsan Veeravalli <svs at qti.qualcomm.com>
  Date:   2026-09-24 (Thu, 24 Sep 2026)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
    M llvm/test/TableGen/AsmPredicateCombiningRISCV.td
    M llvm/test/TableGen/CompressInstEmitter/suboperands.td
    M llvm/test/TableGen/RegClassByHwModeCompressPat.td
    M llvm/unittests/Target/RISCV/RISCVInstrInfoTest.cpp
    M llvm/utils/TableGen/CompressInstEmitter.cpp

  Log Message:
  -----------
  [RISCV][TableGen] Return instruction size from isCompressibleInst (#225660)

Not all compress patterns compress to a 2 byte instruction. There are a
few `Xqci` instructions that compress from a 6 byte instruction to a 4
byte instruction. Having `isCompressibleInst` optionally return the size
of the compressed instruction will help us better estimate instruction
sizes.

Assisted by gpt-5.6-luna



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