[all-commits] [llvm/llvm-project] 33712b: [TableGen] Introduce register sequences

Thu Sep 24 03:08:58 PDT 2026

  Branch: refs/heads/users/kosarev/register-sequences
  Home:   https://github.com/llvm/llvm-project
  Commit: 33712b0116bd664135d87f7336701fbf582550fd
      https://github.com/llvm/llvm-project/commit/33712b0116bd664135d87f7336701fbf582550fd
  Author: Ivan Kosarev <ivan.kosarev at amd.com>
  Date:   2026-09-24 (Thu, 24 Sep 2026)

  Changed paths:
    M llvm/include/llvm/Target/Target.td
    M llvm/lib/Target/AMDGPU/AMDGPUArgumentUsageInfo.cpp
    M llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
    M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
    M llvm/lib/Target/AMDGPU/AMDGPUWaitSGPRHazards.cpp
    M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
    M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
    M llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
    M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
    M llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
    M llvm/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp
    M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
    M llvm/lib/Target/AMDGPU/SIRegisterInfo.td
    M llvm/test/Analysis/DotMachineCFG/AMDGPU/functions.mir
    M llvm/test/Analysis/DotMachineCFG/AMDGPU/irreducible.mir
    M llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/always-uniform-gmir.mir
    M llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/atomics-gmir.mir
    M llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/hidden-diverge-gmir.mir
    M llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/hidden-loop-diverge.mir
    M llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/temporal-divergence.mir
    M llvm/test/Analysis/UniformityAnalysis/AMDGPU/deprecated/hidden-diverge.mir
    M llvm/test/Analysis/UniformityAnalysis/AMDGPU/deprecated/irreducible-1.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-trunc.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-unmerge-values.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw-fmin-fmax.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-binop-s64-with-s32-mask.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-mul-post-legalize.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-mul-pre-legalize.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-or-s64-s32.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-imm-chain-illegal-types.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/dereferenceable-declaration.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/divergent-control-flow.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/dropped_debug_info_assert.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/frem.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/image-waterfall-loop-O0.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/implicit-kernarg-backend-usage-global-isel.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.class.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fract.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rcp.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rsq.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgpu-atomic-cmpxchg-global.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-and.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-anyext.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ashr.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-bitreverse.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-build-vector.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-concat-vectors.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-copy.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ctlz-zero-poison.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ctpop.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-cttz-zero-poison.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-extract-vector-elt.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fabs.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fadd.s64.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fceil.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fconstant.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ffloor.s64.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum-ieee.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum-ieee.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmul.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fneg.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fract.f64.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-icmp.s64.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-insert-vector-elt.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-intrinsic-trunc.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-inttoptr.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-constant.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-global-saddr.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-local.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-private.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-smrd.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-lshr.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-merge-values.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-or.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-phi.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ptr-add.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ptrmask.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ptrtoint.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-returnaddress.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-select.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sext-inreg.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sext.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-shl.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-smax-64.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-smin-64.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-local.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-private.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-trunc.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-trunc.v2s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-umax-64.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-umin-64.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-unmerge-values.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-xor.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-zext.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgcn-cs-chain.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_kernel-system-sgprs.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_kernel.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-assert-align.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-abi-attribute-hints.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-implicit-args.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-non-fixed.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-return-values.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-sret.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-constant-fold-vector-op.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-fence.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-indirect-call.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-inline-asm.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-sibling-call.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-tail-call.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/known-bits-sbfe.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/lds-zero-initializer.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-addrspacecast.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomic-cmpxchg.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-add.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-and.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-fadd-global.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-max.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-min.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-nand.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-or.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-sub.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-umax.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-umin.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-xchg-flat.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-xchg.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-xor.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-brcond.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-insert-vector-elt.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.s.buffer.load.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-phi.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-rotl-rotr.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.atomic.dim.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/localizer-wrong-insert-point.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/mul-known-bits.i64.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/no-cse-nonlocal-convergent-instrs.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-fmed3-minmax-const.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-smed3.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-umed3.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-s-buffer-load.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.class.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.else.64.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.mfma.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.buffer.load.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-ffbh-u32.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-ffbl-b32.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-and.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-assert-align.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-assert-sext.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-assert-zext.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomic-cmpxchg.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-add-sub.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-add.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-and.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-fadd.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-max.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-min.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-or.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-sub.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-umax.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-umin.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-xchg.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-xor.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-bitreverse.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-call.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-copy.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ctlz-zero-poison.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ctpop.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-cttz-zero-poison.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-extract-vector-elt.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fabs.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fcanonicalize.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fneg.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptrunc.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-icmp.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-implicit-def.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-insert-vector-elt.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-inttoptr.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-load.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mul.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-or.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi-s1.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-pseudo-scalar-transcendental.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptr-add.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptrmask.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptrtoint.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-salu-float.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sbfx.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-select.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sext-inreg.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sextload.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-split-scalar-load-metadata.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sub.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-trunc.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ubfx.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uniform-load-noclobber.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-unmerge-values.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-waterfall-agpr.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-waterfall-call.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-widen-scalar-loads.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-xor.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-zextload.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/select-merge-values-build-vector-s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.96.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i64.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/unmerge-sgpr-s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i64.ll
    M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/spill-vreg-many-lanes.mir
    M llvm/test/CodeGen/AMDGPU/SRSRC-GIT-clobber-check.mir
    M llvm/test/CodeGen/AMDGPU/accvgpr-copy.mir
    M llvm/test/CodeGen/AMDGPU/accvgpr-spill-scc-clobber.mir
    M llvm/test/CodeGen/AMDGPU/add.ll
    M llvm/test/CodeGen/AMDGPU/add_i1.ll
    M llvm/test/CodeGen/AMDGPU/agpr-copy-reuse-writes.mir
    M llvm/test/CodeGen/AMDGPU/agpr-copy-sgpr-no-vgprs.mir
    M llvm/test/CodeGen/AMDGPU/agpr-to-agpr-copy.mir
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.160bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.192bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.224bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.288bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.352bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.384bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.448bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.576bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.640bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.64bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.704bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.768bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgpu-snop-padding.mir
    M llvm/test/CodeGen/AMDGPU/artificial-terminators.mir
    M llvm/test/CodeGen/AMDGPU/attributor-flatscratchinit-globalisel.ll
    M llvm/test/CodeGen/AMDGPU/av-spill-expansion-with-machine-cp.mir
    M llvm/test/CodeGen/AMDGPU/av_spill_cross_bb_usage.mir
    M llvm/test/CodeGen/AMDGPU/bad-agpr-vgpr-regalloc-priority.mir
    M llvm/test/CodeGen/AMDGPU/bb-prolog-spill-during-regalloc.ll
    M llvm/test/CodeGen/AMDGPU/block-should-not-be-in-alive-blocks.mir
    M llvm/test/CodeGen/AMDGPU/branch-folder-requires-no-phis.mir
    M llvm/test/CodeGen/AMDGPU/branch-folding-implicit-def-subreg.ll
    M llvm/test/CodeGen/AMDGPU/branch-relax-indirect-branch.mir
    M llvm/test/CodeGen/AMDGPU/branch-relax-no-terminators.mir
    M llvm/test/CodeGen/AMDGPU/branch-relaxation-debug-info.mir
    M llvm/test/CodeGen/AMDGPU/branch-relaxation-inst-size-gfx1250.mir
    M llvm/test/CodeGen/AMDGPU/break-smem-soft-clauses.mir
    M llvm/test/CodeGen/AMDGPU/break-vmem-soft-clauses.mir
    M llvm/test/CodeGen/AMDGPU/buffer-store-dwordx4-vpk-mul-war-hazard-gfx942.mir
    M llvm/test/CodeGen/AMDGPU/bug-pk-f32-imm-fold.mir
    M llvm/test/CodeGen/AMDGPU/bug-undef-spilled-agpr.mir
    M llvm/test/CodeGen/AMDGPU/build_vector.gfx11plus.ll
    M llvm/test/CodeGen/AMDGPU/call-argument-types.ll
    M llvm/test/CodeGen/AMDGPU/call-c-function.ll
    M llvm/test/CodeGen/AMDGPU/call-defs-mode-register.ll
    M llvm/test/CodeGen/AMDGPU/call-waw-waitcnt.mir
    M llvm/test/CodeGen/AMDGPU/carryout-selection.ll
    M llvm/test/CodeGen/AMDGPU/clamp-omod-special-case.mir
    M llvm/test/CodeGen/AMDGPU/coalesce-copy-to-agpr-to-av-registers.mir
    M llvm/test/CodeGen/AMDGPU/coalesce-into-dead-subreg-copies.mir
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    M llvm/test/CodeGen/AMDGPU/phys-partial-liveness.mir
    M llvm/test/CodeGen/AMDGPU/post-ra-sched-kill-bundle-use-inst.mir
    M llvm/test/CodeGen/AMDGPU/postra-bundle-memops.mir
    M llvm/test/CodeGen/AMDGPU/postra-bundle-vimage-vsample-gfx12.mir
    M llvm/test/CodeGen/AMDGPU/postra-machine-sink-livein-subrange.mir
    M llvm/test/CodeGen/AMDGPU/postra-machine-sink.mir
    M llvm/test/CodeGen/AMDGPU/postra-sink-update-dependency.mir
    M llvm/test/CodeGen/AMDGPU/power-sched-no-instr-sunit.mir
    M llvm/test/CodeGen/AMDGPU/pr51516.mir
    M llvm/test/CodeGen/AMDGPU/preserve-only-inactive-lane.mir
    M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm-gfx10.mir
    M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm-gfx12.mir
    M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm-gfx90a.mir
    M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.mir
    M llvm/test/CodeGen/AMDGPU/ptradd-sdag-optimizations.ll
    M llvm/test/CodeGen/AMDGPU/ran-out-of-sgprs-allocation-failure.mir
    M llvm/test/CodeGen/AMDGPU/readlane_exec0.mir
    M llvm/test/CodeGen/AMDGPU/reduce-saveexec.mir
    M llvm/test/CodeGen/AMDGPU/reg-coalescer-subreg-liveness.mir
    M llvm/test/CodeGen/AMDGPU/regalloc-fail-unsatisfiable-overlapping-tuple-hints.mir
    M llvm/test/CodeGen/AMDGPU/regalloc-failure-overlapping-insert-assert.mir
    M llvm/test/CodeGen/AMDGPU/regalloc-fast-dont-drop-subreg-index-issue61134.mir
    M llvm/test/CodeGen/AMDGPU/regalloc-hoist-spill-live-range-upd.mir
    M llvm/test/CodeGen/AMDGPU/regalloc-introduces-copy-sgpr-to-agpr.mir
    M llvm/test/CodeGen/AMDGPU/regalloc-sgpr128-partial-def.mir
    M llvm/test/CodeGen/AMDGPU/regalloc-undef-copy-fold.mir
    M llvm/test/CodeGen/AMDGPU/regcoalesce-dbg.mir
    M llvm/test/CodeGen/AMDGPU/register-killed-error-after-alloc-failure0.mir
    M llvm/test/CodeGen/AMDGPU/regpressure_printer.mir
    M llvm/test/CodeGen/AMDGPU/release-vgprs-gfx12-dvgpr.mir
    M llvm/test/CodeGen/AMDGPU/release-vgprs-gfx12.mir
    M llvm/test/CodeGen/AMDGPU/release-vgprs.mir
    M llvm/test/CodeGen/AMDGPU/rem_i128.ll
    M llvm/test/CodeGen/AMDGPU/remaining-virtual-register-operands.mir
    M llvm/test/CodeGen/AMDGPU/remat-dead-subreg.mir
    M llvm/test/CodeGen/AMDGPU/remat-smrd.mir
    M llvm/test/CodeGen/AMDGPU/remat-sop.mir
    M llvm/test/CodeGen/AMDGPU/remat-through-copy.mir
    M llvm/test/CodeGen/AMDGPU/remat-vop.mir
    M llvm/test/CodeGen/AMDGPU/remove-not-short-exec-branch-on-unconditional-jump.mir
    M llvm/test/CodeGen/AMDGPU/remove-register-flags.mir
    M llvm/test/CodeGen/AMDGPU/rename-independent-subregs-mac-operands.mir
    M llvm/test/CodeGen/AMDGPU/resource-usage-crash-unhandled-reg.mir
    M llvm/test/CodeGen/AMDGPU/return-with-successors.mir
    M llvm/test/CodeGen/AMDGPU/rewrite-mfma-form-spill-cost-reset.ll
    M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-spill-joint-dom-mir.mir
    M llvm/test/CodeGen/AMDGPU/s_or_saveexec_xor_combine.mir
    M llvm/test/CodeGen/AMDGPU/same-slot-agpr-sgpr.mir
    M llvm/test/CodeGen/AMDGPU/scalar-store-cache-flush.mir
    M llvm/test/CodeGen/AMDGPU/scalar_to_vector.gfx11plus.ll
    M llvm/test/CodeGen/AMDGPU/sched-assert-dead-def-subreg-use-other-subreg.mir
    M llvm/test/CodeGen/AMDGPU/sched-barrier-post-RA.mir
    M llvm/test/CodeGen/AMDGPU/sched-crash-dbg-value.mir
    M llvm/test/CodeGen/AMDGPU/sched-handleMoveUp-dead-def-join.mir
    M llvm/test/CodeGen/AMDGPU/sched-handleMoveUp-subreg-def-across-subreg-def.mir
    M llvm/test/CodeGen/AMDGPU/sched-image-sample-post-RA.mir
    M llvm/test/CodeGen/AMDGPU/sched_mfma_rewrite_copies.mir
    M llvm/test/CodeGen/AMDGPU/sched_mfma_rewrite_cost.mir
    M llvm/test/CodeGen/AMDGPU/sched_mfma_rewrite_diff_types.mir
    M llvm/test/CodeGen/AMDGPU/schedmodel-dummywrite.mir
    M llvm/test/CodeGen/AMDGPU/schedule-barrier-latency-gfx9.mir
    M llvm/test/CodeGen/AMDGPU/schedule-ilp.mir
    M llvm/test/CodeGen/AMDGPU/schedule-pending-queue.mir
    M llvm/test/CodeGen/AMDGPU/schedule-regpressure-ilp-metric-spills.mir
    M llvm/test/CodeGen/AMDGPU/schedule-regpressure-no-unclustered-regions.mir
    M llvm/test/CodeGen/AMDGPU/schedule-regpressure.mir
    M llvm/test/CodeGen/AMDGPU/scheduler-handle-move-bundle.mir
    M llvm/test/CodeGen/AMDGPU/sdwa-gfx9.mir
    M llvm/test/CodeGen/AMDGPU/sdwa-ops.mir
    M llvm/test/CodeGen/AMDGPU/sdwa-peephole-cndmask-wave32.mir
    M llvm/test/CodeGen/AMDGPU/sdwa-peephole-instr-combine-sel.mir
    M llvm/test/CodeGen/AMDGPU/sdwa-peephole-instr-gfx10.mir
    M llvm/test/CodeGen/AMDGPU/sdwa-peephole-instr.mir
    M llvm/test/CodeGen/AMDGPU/sdwa-preserve.mir
    M llvm/test/CodeGen/AMDGPU/sdwa-scalar-ops.mir
    M llvm/test/CodeGen/AMDGPU/sdwa-vop2-64bit.mir
    M llvm/test/CodeGen/AMDGPU/sgpr-control-flow.ll
    M llvm/test/CodeGen/AMDGPU/sgpr-phys-copy.mir
    M llvm/test/CodeGen/AMDGPU/sgpr-scavenge-fi-stack-id.ll
    M llvm/test/CodeGen/AMDGPU/sgpr-spill-dead-frame-in-dbg-value.mir
    M llvm/test/CodeGen/AMDGPU/sgpr-spill-fi-skip-processing-stack-arg-dbg-value-list.mir
    M llvm/test/CodeGen/AMDGPU/sgpr-spill-fi-skip-processing-stack-arg-dbg-value.mir
    M llvm/test/CodeGen/AMDGPU/sgpr-spill-overlap-wwm-reserve.mir
    M llvm/test/CodeGen/AMDGPU/sgpr-spill-partially-undef.mir
    M llvm/test/CodeGen/AMDGPU/sgpr-spill-to-vmem-scc-clobber-reserved-exec-copy.mir
    M llvm/test/CodeGen/AMDGPU/sgpr-spill-to-vmem-scc-clobber-unhandled.mir
    M llvm/test/CodeGen/AMDGPU/sgpr-spill-to-vmem-scc-clobber.mir
    M llvm/test/CodeGen/AMDGPU/sgpr-spill-vmem-large-frame.mir
    M llvm/test/CodeGen/AMDGPU/sgpr-spill-wrong-stack-id.mir
    M llvm/test/CodeGen/AMDGPU/sgpr-spill.mir
    M llvm/test/CodeGen/AMDGPU/shrink-dead-vcc-def.mir
    M llvm/test/CodeGen/AMDGPU/shrink-vop3-carry-out.mir
    M llvm/test/CodeGen/AMDGPU/si-annotate-nested-control-flows.ll
    M llvm/test/CodeGen/AMDGPU/si-fold-aligned-vgprs.mir
    M llvm/test/CodeGen/AMDGPU/si-fold-copy-kills.mir
    M llvm/test/CodeGen/AMDGPU/si-fold-operands-agpr-copy-reg-sequence.mir
    M llvm/test/CodeGen/AMDGPU/si-fold-operands-subreg-imm.mir
    M llvm/test/CodeGen/AMDGPU/si-insert-hard-clauses-no-nesting.mir
    M llvm/test/CodeGen/AMDGPU/si-lower-control-flow-preserve-dom-tree.mir
    M llvm/test/CodeGen/AMDGPU/si-lower-control-flow.mir
    M llvm/test/CodeGen/AMDGPU/si-lower-i1-copies.mir
    M llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills-cycle-header.ll
    M llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills-cycle-header.mir
    M llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills-initial-insert-in-body.mir
    M llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills-initial-insert-in-latch.mir
    M llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills-multi-entry-cycle.mir
    M llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills-vgpr-lanes-usage.mir
    M llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills.mir
    M llvm/test/CodeGen/AMDGPU/si-lower-wwm-copies.mir
    M llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-regs-preserve-rci.mir
    M llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-regs.mir
    M llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwwmregs-dbg-noreg.mir
    M llvm/test/CodeGen/AMDGPU/sink-after-control-flow-postra.mir
    M llvm/test/CodeGen/AMDGPU/skip-branch-taildup-ret.mir
    M llvm/test/CodeGen/AMDGPU/smem-war-hazard.mir
    M llvm/test/CodeGen/AMDGPU/smfmac_alloc_failure_no_agpr_O0.ll
    M llvm/test/CodeGen/AMDGPU/snippet-copy-bundle-regression.mir
    M llvm/test/CodeGen/AMDGPU/soft-clause-dbg-value.mir
    M llvm/test/CodeGen/AMDGPU/soft-waitcnt-deletion.mir
    M llvm/test/CodeGen/AMDGPU/spill-agpr-partially-undef.mir
    M llvm/test/CodeGen/AMDGPU/spill-agpr.mir
    M llvm/test/CodeGen/AMDGPU/spill-before-exec.mir
    M llvm/test/CodeGen/AMDGPU/spill-empty-live-interval.mir
    M llvm/test/CodeGen/AMDGPU/spill-partial-csr-sgpr-live-ins.mir
    M llvm/test/CodeGen/AMDGPU/spill-reg-tuple-super-reg-use.mir
    M llvm/test/CodeGen/AMDGPU/spill-sgpr-to-virtual-vgpr.mir
    M llvm/test/CodeGen/AMDGPU/spill-sgpr-used-for-exec-copy.mir
    M llvm/test/CodeGen/AMDGPU/spill-special-sgpr.mir
    M llvm/test/CodeGen/AMDGPU/spill-vector-superclass.ll
    M llvm/test/CodeGen/AMDGPU/spill-wait.mir
    M llvm/test/CodeGen/AMDGPU/spill192.mir
    M llvm/test/CodeGen/AMDGPU/spill224.mir
    M llvm/test/CodeGen/AMDGPU/spill288.mir
    M llvm/test/CodeGen/AMDGPU/spill320.mir
    M llvm/test/CodeGen/AMDGPU/spill352.mir
    M llvm/test/CodeGen/AMDGPU/spill384.mir
    M llvm/test/CodeGen/AMDGPU/spill_kill_v16.mir
    M llvm/test/CodeGen/AMDGPU/spillv16.mir
    M llvm/test/CodeGen/AMDGPU/split-liverange-overlapping-copies.mir
    M llvm/test/CodeGen/AMDGPU/splitkit-copy-bundle.mir
    M llvm/test/CodeGen/AMDGPU/splitkit-copy-live-lanes.mir
    M llvm/test/CodeGen/AMDGPU/splitkit-do-not-undo-subclass-split-with-remat.mir
    M llvm/test/CodeGen/AMDGPU/splitkit-nolivesubranges.mir
    M llvm/test/CodeGen/AMDGPU/splitkit.mir
    M llvm/test/CodeGen/AMDGPU/sreg-xnull-regclass-bitwidth.mir
    M llvm/test/CodeGen/AMDGPU/srem.ll
    M llvm/test/CodeGen/AMDGPU/stack-realign.ll
    M llvm/test/CodeGen/AMDGPU/stack-slot-color-sgpr-vgpr-spills.mir
    M llvm/test/CodeGen/AMDGPU/stacksave_stackrestore.ll
    M llvm/test/CodeGen/AMDGPU/statepoint-asm-printer.mir
    M llvm/test/CodeGen/AMDGPU/statepoint-insert-waitcnts.mir
    M llvm/test/CodeGen/AMDGPU/store-local.96.ll
    M llvm/test/CodeGen/AMDGPU/stress-regalloc-limits-regalloc.mir
    M llvm/test/CodeGen/AMDGPU/sub_i1.ll
    M llvm/test/CodeGen/AMDGPU/subreg-implicit-def.mir
    M llvm/test/CodeGen/AMDGPU/subreg-split-live-in-error.mir
    M llvm/test/CodeGen/AMDGPU/subvector-test.mir
    M llvm/test/CodeGen/AMDGPU/swdev282079.mir
    M llvm/test/CodeGen/AMDGPU/swdev502267-use-after-free-last-chance-recoloring-alloc-succeeds.mir
    M llvm/test/CodeGen/AMDGPU/swp-amdgpu-pipeline-epilog-phi.mir
    M llvm/test/CodeGen/AMDGPU/swp-amdgpu-pipeline-gen-structure.mir
    M llvm/test/CodeGen/AMDGPU/swp-amdgpu-pipeline-loop-carried-mem.mir
    M llvm/test/CodeGen/AMDGPU/swp-amdgpu-pipeline-unpipeline-compare.mir
    M llvm/test/CodeGen/AMDGPU/tail-call-inreg-arguments.convergencetokens.ll
    M llvm/test/CodeGen/AMDGPU/tail-call-uniform-target-in-vgprs-issue110930.convergencetokens.ll
    M llvm/test/CodeGen/AMDGPU/tied-op-for-wwm-scratch-reg-spill-restore.mir
    M llvm/test/CodeGen/AMDGPU/track-spilled-vgpr-liveness.mir
    M llvm/test/CodeGen/AMDGPU/transform-block-with-return-to-epilog.ll
    M llvm/test/CodeGen/AMDGPU/triton_regression_no_waterfall.mir
    M llvm/test/CodeGen/AMDGPU/triv-disjoint-mem-access-neg-offset.mir
    M llvm/test/CodeGen/AMDGPU/true16-saveexec.mir
    M llvm/test/CodeGen/AMDGPU/tuple-allocation-failure.ll
    M llvm/test/CodeGen/AMDGPU/unallocatable-bundle-regression.mir
    M llvm/test/CodeGen/AMDGPU/undefined-physreg-sgpr-spill.mir
    M llvm/test/CodeGen/AMDGPU/unpack-non-coissue-insts-post-ra-scheduler.mir
    M llvm/test/CodeGen/AMDGPU/use_restore_frame_reg.mir
    M llvm/test/CodeGen/AMDGPU/v-cmp-cse-across-loop.mir
    M llvm/test/CodeGen/AMDGPU/v_mov_b64_expansion.mir
    M llvm/test/CodeGen/AMDGPU/v_swap_b16.mir
    M llvm/test/CodeGen/AMDGPU/v_swap_b32.mir
    M llvm/test/CodeGen/AMDGPU/valu-i1.ll
    M llvm/test/CodeGen/AMDGPU/valu-mask-write-hazard-true16.mir
    M llvm/test/CodeGen/AMDGPU/valu-mask-write-hazard.mir
    M llvm/test/CodeGen/AMDGPU/valu-read-sgpr-hazard-attrs.mir
    M llvm/test/CodeGen/AMDGPU/valu-read-sgpr-hazard.mir
    M llvm/test/CodeGen/AMDGPU/vccz-corrupt-bug-workaround.mir
    M llvm/test/CodeGen/AMDGPU/vcmp-saveexec-to-vcmpx-set-kill.mir
    M llvm/test/CodeGen/AMDGPU/vcmp-saveexec-to-vcmpx-wrong-kill-flags.mir
    M llvm/test/CodeGen/AMDGPU/vcmp-saveexec-to-vcmpx.mir
    M llvm/test/CodeGen/AMDGPU/vcmpx-exec-war-hazard.mir
    M llvm/test/CodeGen/AMDGPU/verify-constant-bus-violations.mir
    M llvm/test/CodeGen/AMDGPU/verify-image.mir
    M llvm/test/CodeGen/AMDGPU/verify-scalar-store.mir
    M llvm/test/CodeGen/AMDGPU/verify-vimage-vsample.mir
    M llvm/test/CodeGen/AMDGPU/vgpr-blocks-funcinfo.mir
    M llvm/test/CodeGen/AMDGPU/vgpr-liverange-ir.ll
    M llvm/test/CodeGen/AMDGPU/vgpr-lowering-gfx1250.mir
    M llvm/test/CodeGen/AMDGPU/vgpr-remat.mir
    M llvm/test/CodeGen/AMDGPU/vgpr-spill-dead-frame-in-dbg-value.mir
    M llvm/test/CodeGen/AMDGPU/vgpr-spill-fi-skip-processing-stack-arg-dbg-value-list.mir
    M llvm/test/CodeGen/AMDGPU/vgpr-spill-fi-skip-processing-stack-arg-dbg-value.mir
    M llvm/test/CodeGen/AMDGPU/vgpr-spill-scc-clobber.mir
    M llvm/test/CodeGen/AMDGPU/vgpr-spill.mir
    M llvm/test/CodeGen/AMDGPU/vgpr_constant64_to_sgpr.mir
    M llvm/test/CodeGen/AMDGPU/vgpr_constant_to_sgpr.ll
    M llvm/test/CodeGen/AMDGPU/virtregrewrite-undef-identity-copy.mir
    M llvm/test/CodeGen/AMDGPU/vmem-to-salu-hazard.mir
    M llvm/test/CodeGen/AMDGPU/vmem-vcc-hazard.mir
    M llvm/test/CodeGen/AMDGPU/vopc-remat.mir
    M llvm/test/CodeGen/AMDGPU/vopd-combine-gfx1250.mir
    M llvm/test/CodeGen/AMDGPU/vopd3-imm-fold.mir
    M llvm/test/CodeGen/AMDGPU/wait-before-stores-with-scope_sys.mir
    M llvm/test/CodeGen/AMDGPU/wait-xcnt-atomic-rmw-optimization.ll
    M llvm/test/CodeGen/AMDGPU/wait-xcnt-drain.mir
    M llvm/test/CodeGen/AMDGPU/wait-xcnt.mir
    M llvm/test/CodeGen/AMDGPU/waitcnt-back-edge-loop.mir
    M llvm/test/CodeGen/AMDGPU/waitcnt-buffer-inv.mir
    M llvm/test/CodeGen/AMDGPU/waitcnt-bvh.mir
    M llvm/test/CodeGen/AMDGPU/waitcnt-func-global-inv.mir
    M llvm/test/CodeGen/AMDGPU/waitcnt-global-inv-wb.mir
    M llvm/test/CodeGen/AMDGPU/waitcnt-loop-ds-prefetch-flushed.mir
    M llvm/test/CodeGen/AMDGPU/waitcnt-loop-ds-store-barrier.mir
    M llvm/test/CodeGen/AMDGPU/waitcnt-loop-irreducible.mir
    M llvm/test/CodeGen/AMDGPU/waitcnt-loop-opt.mir
    M llvm/test/CodeGen/AMDGPU/waitcnt-multiple-funcs.mir
    M llvm/test/CodeGen/AMDGPU/waitcnt-no-redundant.mir
    M llvm/test/CodeGen/AMDGPU/waitcnt-overflow.mir
    M llvm/test/CodeGen/AMDGPU/waitcnt-permute.mir
    M llvm/test/CodeGen/AMDGPU/waitcnt-sample-out-order.mir
    M llvm/test/CodeGen/AMDGPU/waitcnt-sample-waw.mir
    M llvm/test/CodeGen/AMDGPU/waitcnt-vmcnt-loop.mir
    M llvm/test/CodeGen/AMDGPU/waitcnt-vmem-waw.mir
    M llvm/test/CodeGen/AMDGPU/waitcnt-vscnt.mir
    M llvm/test/CodeGen/AMDGPU/waitcnt.mir
    M llvm/test/CodeGen/AMDGPU/waterfall-call-inreg-agpr.mir
    M llvm/test/CodeGen/AMDGPU/waterfall-call-target-av-register-failure.ll
    M llvm/test/CodeGen/AMDGPU/wave32.ll
    M llvm/test/CodeGen/AMDGPU/whole-wave-register-spill.ll
    M llvm/test/CodeGen/AMDGPU/wmma-coexecution-valu-hazards.mir
    M llvm/test/CodeGen/AMDGPU/wqm.ll
    M llvm/test/CodeGen/AMDGPU/wqm.mir
    M llvm/test/CodeGen/AMDGPU/wwm-regalloc-partial-pool.mir
    M llvm/test/CodeGen/AMDGPU/wwm-regalloc-preallocation-guard.mir
    M llvm/test/CodeGen/AMDGPU/wwm-reserved-spill.ll
    M llvm/test/CodeGen/AMDGPU/wwm-reserved.ll
    M llvm/test/CodeGen/AMDGPU/wwm-spill-superclass-pseudo.mir
    M llvm/test/CodeGen/MIR/AMDGPU/empty-custom-regmask.mir
    M llvm/test/CodeGen/MIR/AMDGPU/expected-target-index-name.mir
    M llvm/test/CodeGen/MIR/AMDGPU/invalid-target-index-operand.mir
    M llvm/test/CodeGen/MIR/AMDGPU/long-branch-reg-all-sgpr-used.ll
    M llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-after-pei.ll
    M llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-long-branch-reg-debug.ll
    M llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-long-branch-reg.ll
    M llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-no-ir.mir
    M llvm/test/CodeGen/MIR/AMDGPU/machine-function-info.ll
    M llvm/test/CodeGen/MIR/AMDGPU/mir-canon-multi.mir
    M llvm/test/CodeGen/MIR/AMDGPU/mircanon-memoperands.mir
    M llvm/test/CodeGen/MIR/AMDGPU/parse-order-reserved-regs.mir
    M llvm/test/CodeGen/MIR/AMDGPU/preload-kernarg-invalid-register-class-error.mir
    M llvm/test/CodeGen/MIR/AMDGPU/preload-kernarg-invalid-register-name-error.mir
    M llvm/test/CodeGen/MIR/AMDGPU/preload-kernarg-mfi.ll
    M llvm/test/CodeGen/MIR/AMDGPU/preload-kernarg-stack-type-error.mir
    M llvm/test/CodeGen/MIR/AMDGPU/spill-phys-vgprs.mir
    M llvm/test/CodeGen/MIR/AMDGPU/stack-id-assert.mir
    M llvm/test/CodeGen/MIR/AMDGPU/syncscopes.mir
    M llvm/test/CodeGen/MIR/AMDGPU/target-flags.mir
    M llvm/test/CodeGen/MIR/AMDGPU/target-index-operands.mir
    M llvm/test/CodeGen/MIR/AMDGPU/target-memoperands.mir
    M llvm/test/MC/AMDGPU/buffer-op-lds-operand.s
    M llvm/test/MC/AMDGPU/buffer-op-swz-operand.s
    M llvm/test/MachineVerifier/AMDGPU/fix-illegal-vector-copies.mir
    M llvm/test/MachineVerifier/AMDGPU/hazard-gfx1250-flat-src-hi.mir
    M llvm/test/MachineVerifier/AMDGPU/issue98474-missing-def-liveout-physical-subregister.mir
    M llvm/test/MachineVerifier/AMDGPU/unsupported-subreg-index-aligned-vgpr-check.mir
    M llvm/test/MachineVerifier/AMDGPU/verifier-pseudo-terminators.mir
    A llvm/test/TableGen/RegisterSequence.td
    M llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_isel.ll.expected
    M llvm/test/tools/llvm-reduce/mir/preserve-machine-function-info-amdgpu.mir
    M llvm/test/tools/llvm-reduce/mir/reduce-register-defs.mir
    M llvm/test/tools/llvm-reduce/mir/reduce-register-masks.mir
    M llvm/test/tools/llvm-reduce/mir/reduce-register-uses.mir
    M llvm/unittests/MIR/MachineMetadata.cpp
    M llvm/unittests/Target/AMDGPU/InstSizes.cpp
    M llvm/unittests/Target/AMDGPU/LiveRegUnits.cpp
    M llvm/utils/TableGen/Common/CodeGenRegisters.cpp

  Log Message:
  -----------
  [TableGen] Introduce register sequences

The overwhelming majority of AMDGPU's registers are synthesized
tuples, and all of them are sequences of adjacent registers of
certain widths. We currently have no adequate representation of
them in TableGen: every such tuple is emitted as a descriptor
carrying its own name string and its own sub- and super-register
lists, so the generated register tables run to well over a
hundred megabytes for this one target. The names spell out every
member, so a four-register tuple is SGPR0_SGPR1_SGPR2_SGPR3.

Describing such tuples by their first and last registers alone
would address these issues. What stands in the way is that
TableGen has no notion of one register following another in a
sequence.

This patch adds such a notion using RegisterSequence instances:

  def : RegisterSequence<[R0, R1, R2, R3]>;

Note that it is a relationship between the registers themselves
and not register classes. A register class may order or omit its
members freely without affecting the sequence.

This patch only uses sequences for naming. Where a tuple is made
of registers that follow one another, we name it after the first
and the last of them, so SGPR0_3 instead of
SGPR0_SGPR1_SGPR2_SGPR3. Other tuples keep their longer names.
These names are code identifiers; the assembly names come from
the AsmName field, which we do not touch. The two now agree on
which registers a tuple holds, as SGPR0_3 is the register that
assembles as s[0:3].

We intend to use the same relationship to describe whole blocks
of such tuples at once, so that the registers of a block need no
individual code names, no sub- or super-register lists, no
register units and finally no descriptors of their own. Only the
SGPRs are declared as a sequence here; the other AMDGPU register
pools are to follow.

The bulk of the diff is the resulting test updates, a mechanical
rename of the affected register names.

Targets that declare no sequences are not affected. For AMDGPU,
all the register numbers stay as they were, and the only thing
that changes in the register descriptors is their names.

Assisted-by: Claude

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