[all-commits] [llvm/llvm-project] 4802f8: [RISCV][MC] Allow x0 as the destination of qc.inw ...

[Zeyi Xu via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 4802f8f42c4b079c12994961f1d81c838581b831
      https://github.com/llvm/llvm-project/commit/4802f8f42c4b079c12994961f1d81c838581b831
  Author: Zeyi Xu <zeyi2 at nekoarch.cc>
  Date:   2026-09-24 (Thu, 24 Sep 2026)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
    M llvm/test/MC/RISCV/xqciio-invalid.s
    M llvm/test/MC/RISCV/xqciio-valid.s

  Log Message:
  -----------
  [RISCV][MC] Allow x0 as the destination of qc.inw (#225602)

According to the Xqciio specification, `qc.inw` does not impose any
restriction that excludes `x0` as the destination register. In
`qc.inw.yaml`, `rd` is defined as:

```
- name: rd
  location: 11-7
```

This commit removes the incorrect `x0` restriction for `qc.inw`.

Link:
https://github.com/qualcomm/riscv-unified-db/blob/main/arch_overlay/qc_iu/inst/Xqci/qc.inw.yaml



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