[all-commits] [llvm/llvm-project] 620a9e: [RISCV] Combine two consecutive VSLIDEDOWN_VL node...

[Min-Yih Hsu via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 620a9e9afaae2d51f186fd0f41988e3b326a127c
      https://github.com/llvm/llvm-project/commit/620a9e9afaae2d51f186fd0f41988e3b326a127c
  Author: Min-Yih Hsu <min.hsu at sifive.com>
  Date:   2026-09-23 (Wed, 23 Sep 2026)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
    M llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll

  Log Message:
  -----------
  [RISCV] Combine two consecutive VSLIDEDOWN_VL nodes into one (#225232)

Given this pattern
```
  %down0 = RISCVISD::VSLIDEDOWN_VL undef, %val, %offset0, %mask, %vl0
%down1 = RISCVISD::VSLIDEDOWN_VL undef, %down0, %offset1, %mask, %vl1
```
we can turn it into
```
%down1 = RISCVISD::VSLIDEDOWN_VL undef, %val, %offset2, %mask, %vl1
```
where %offset2 is `%offset0 + %offset1`, if `%vl0 >= %offset1 + %vl1`.



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