[all-commits] [llvm/llvm-project] 7008bd: [AMDGPU] Improved register pressure estimates for ...

[ilia-cher via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 7008bdc020b6906ce9a5ff7c41224157893a7608
      https://github.com/llvm/llvm-project/commit/7008bdc020b6906ce9a5ff7c41224157893a7608
  Author: ilia-cher <30845429+ilia-cher at users.noreply.github.com>
  Date:   2026-09-23 (Wed, 23 Sep 2026)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
    M llvm/lib/Target/AMDGPU/GCNRegPressure.cpp
    M llvm/lib/Target/AMDGPU/GCNRegPressure.h
    M llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
    M llvm/lib/Target/AMDGPU/GCNSchedStrategy.h
    A llvm/test/CodeGen/AMDGPU/lirp.mir

  Log Message:
  -----------
  [AMDGPU] Improved register pressure estimates for rescheduling (#213116)

Currently we use instantaneous register pressure estimates during
scheduling. This simple metric counts the number of registers live at
any given moment; scheduler uses it to determine when we are over the
register budget and should start prioritizing instructions that free
registers.

Unfortunately, this metric can sometimes be overly optimistic: for
example, it does not account for register redefinitions (common for
loop-carried vregs), and can underestimate the true register pressure.
This can often result in unnecessary spills and loss of performance in
production kernels.

To fix this, we introduce a stage that selectively reschedules certain
regions: it uses a lightweight, greedy, non-splitting register
allocation simulation to detect when the instantaneous estimate might be
wrong and a region should be rescheduled with tighter register limits.

Test plan:
```
ninja -C build
build/bin/llvm-lit -v llvm/test/CodeGen/AMDGPU/lirp.mir
+ perf testing on a corpus of kernels
```



To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications