[all-commits] [llvm/llvm-project] decb0e: [TableGen] Handle the non-`CoveredBySubRegs` case ...

[Igor Wodiany via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: decb0ee138505e73d0eced11a36ec4fee6c0a1ce
      https://github.com/llvm/llvm-project/commit/decb0ee138505e73d0eced11a36ec4fee6c0a1ce
  Author: Igor Wodiany <igor.wodiany at amd.com>
  Date:   2026-09-23 (Wed, 23 Sep 2026)

  Changed paths:
    A llvm/test/TableGen/RegisterInfoEmitter-noncovered-subreg-lanemask.td
    M llvm/utils/TableGen/Common/CodeGenRegisters.cpp

  Log Message:
  -----------
  [TableGen] Handle the non-`CoveredBySubRegs` case in `computeRegUnitLaneMasks` (#223653)

Currently `computeRegUnitLaneMasks` ignores non-leaf subregisters as
"their lane masks are fully covered by the leaf subregisters". However
this only holds when `CoveredBySubRegs` is set to true. Otherwise it
causes subregisters with `CoveredBySubRegs` set to false to have missing
lanes.

For example removing `hi16` from SGPR in AMDGPU causes `sub1` to have a
lane mask of `0x8`, which is equal to `sub1_lo16`, whereas the correct
mask should be `0xC` as although `hi16` is not addressable `sub1` covers
both halves.

This patch adds a logic that identifies unclaimed lanes and backfills
them into appropriate subregister units.

Assisted-by: Claude Code



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