[all-commits] [llvm/llvm-project] bbde24: Address comments and restore newline

[Gaëtan Bossu via All-commits]

  Branch: refs/heads/users/gbossu/lv.revec.poc.1
  Home:   https://github.com/llvm/llvm-project
  Commit: bbde247c06fc2bb67ba8cdb0035383ad275e9d4d
      https://github.com/llvm/llvm-project/commit/bbde247c06fc2bb67ba8cdb0035383ad275e9d4d
  Author: Gaëtan Bossu <gaetan.bossu at arm.com>
  Date:   2026-09-23 (Wed, 23 Sep 2026)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
    M llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
    M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    A llvm/test/Verifier/vector-repeat-intrinsic-valid.ll
    R llvm/test/Verifier/vector-repeat-intrinsic.ll
    M llvm/unittests/CodeGen/SelectionDAGNodeConstructionTest.cpp

  Log Message:
  -----------
  Address comments and restore newline


  Commit: c6155a564f6fed2c7101395dfb6e365065ea2683
      https://github.com/llvm/llvm-project/commit/c6155a564f6fed2c7101395dfb6e365065ea2683
  Author: Gaëtan Bossu <gaetan.bossu at arm.com>
  Date:   2026-09-23 (Wed, 23 Sep 2026)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/test/CodeGen/AArch64/sve-vector-repeat.ll

  Log Message:
  -----------
  Change lowering for 64b vector_repeats

This avoids VECTOR_CONCAT and directly exposes a d -> z.d splat


Compare: https://github.com/llvm/llvm-project/compare/dbe0aa604e60...c6155a564f6f

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