[all-commits] [llvm/llvm-project] 243739: [lld] Don't drop RELR relocations for late-added G...

[Eli Friedman via All-commits]

  Branch: refs/heads/release/23.x
  Home:   https://github.com/llvm/llvm-project
  Commit: 243739128971eb198126960e038b042bf3abf2bc
      https://github.com/llvm/llvm-project/commit/243739128971eb198126960e038b042bf3abf2bc
  Author: Arthur Eubanks <aeubanks at google.com>
  Date:   2026-09-23 (Wed, 23 Sep 2026)

  Changed paths:
    M lld/ELF/Relocations.cpp
    M lld/ELF/SyntheticSections.h
    A lld/test/ELF/x86-64-gotpc-relax-too-far-relr.s

  Log Message:
  -----------
  [lld] Don't drop RELR relocations for late-added GOT entries (#211911)

In #208959 we started dropping RELR relocations for late-added GOT
entries when reverting x86-64 GOTPCRELX relaxations in
X86_64::relaxOnce.

There is a separate unrelaxation bug where if the object files didn't
have any relocations of a certain type, we'd prune .relr.dyn (or even
.rela.dyn). Will be addressed separately.

Assisted-by: Gemini
(cherry picked from commit 5565740f2367093b89481ba7371adf820971977d)


  Commit: 615ef6c76842c0046e94523b2042d3cfb2f8e803
      https://github.com/llvm/llvm-project/commit/615ef6c76842c0046e94523b2042d3cfb2f8e803
  Author: Tom Stellard <tstellar at redhat.com>
  Date:   2026-09-23 (Wed, 23 Sep 2026)

  Changed paths:
    M llvm/utils/release/github-upload-release.py

  Log Message:
  -----------
  github-upload-release: Create draft releases (#209876)

https://discourse.llvm.org/t/rfc-enabling-immutable-releases-v2/91180
(cherry picked from commit acd9cda52648d3acd68096697eba217226875930)


  Commit: 557e1d658863199dfa784f63c9454eaab9bd8aaf
      https://github.com/llvm/llvm-project/commit/557e1d658863199dfa784f63c9454eaab9bd8aaf
  Author: Paweł Bylica <pawel at hepcolgum.band>
  Date:   2026-09-23 (Wed, 23 Sep 2026)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    M llvm/test/CodeGen/AArch64/cgp-usubo.ll
    M llvm/test/CodeGen/X86/subcarry.ll

  Log Message:
  -----------
  [DAGCombiner] Require a 0/1 carry-in when rebuilding a borrow chain (#223396)

combineOrOfSetCCToUSUBOCarry (aae871ba1224) rewrites

  carry_out = (A <u B) | ((A == B) & carry_in)

to USUBO_CARRY(A, B, carry_in), accepting any value as carry_in.

USUBO_CARRY's third operand is specified as "1 if and only if there is
an incoming carry/borrow", so 0 and 1 are its only meaningful values.
Unlike SADDO_CARRY/SSUBO_CARRY it does not fall back to
getBooleanContents for wider types. The matched `and` is bitwise against
a 0/1 setcc, so only bit 0 of carry_in reaches carry_out and nothing
else constrains it; a carry_in with any other bit set is outside the
operand's contract and miscompiles.

Require carry_in to be known 0/1. Check known bits rather than look for
an `and carry_in, 1`: only bit 0 is demanded inside the `and`, so such a
mask is usually folded away before this combine runs. An i1 carry_in,
which is what a real borrow chain produces, passes trivially.

Fixes #222839.

Assisted-by: Claude Code
(cherry picked from commit 4eba5bce282ded21bb912b22aae4aa91e27818da)


  Commit: 8646466e3a4fcde4fc72ca9ece6945f74790697c
      https://github.com/llvm/llvm-project/commit/8646466e3a4fcde4fc72ca9ece6945f74790697c
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2026-09-23 (Wed, 23 Sep 2026)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

  Log Message:
  -----------
  [DAGCombiner] Restrict combineOrOfSetCCToUSUBOCarry to ZeroOrOneBooleanContent. (#224759)

We need to ensure the carry in matches boolean contents. We are checking
MaskedValueIsZero which is only valid for ZeroOrOneBooleanContent.

We could check ComputeNumSignBits for ZeroOrNegativeOneBooleanContent,
but no in tree target supports USUBO_CARRY and
ZeroOrNegativeOneBooleanContent.

This was an oversight in #223396 due to incorrect documentation for
USUBO_CARRY. I will fix that in a separate patch.

(cherry picked from commit 51d290508d4dd980c3ba03bcc873926c41c6e591)


  Commit: 898bafa6c8559fb5cc573153cf6b4818f87107ea
      https://github.com/llvm/llvm-project/commit/898bafa6c8559fb5cc573153cf6b4818f87107ea
  Author: Eli Friedman <efriedma at qti.qualcomm.com>
  Date:   2026-09-23 (Wed, 23 Sep 2026)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64FastISel.cpp
    M llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
    M llvm/test/CodeGen/AArch64/arm64-windows-calls.ll
    M llvm/test/CodeGen/AArch64/arm64-windows-tailcall.ll

  Log Message:
  -----------
  [AArch64][GISel][FastISel] Fix Windows "sret inreg". (#225190)

5dc8aeb26d2896c65cbea0d3b87f090241444bb6 added a special case to
SelectionDAG ISel for "sret inreg" parameters: they are copied to x0 on
return. There was a review comment suggesting that GISel and FastISel
also needed fixes, but through some mixup the followup never happened.

Fixes #225060

(cherry picked from commit 8890be35705834c5af8e21424d7900639be03180)


Compare: https://github.com/llvm/llvm-project/compare/67f4a076a097...898bafa6c855

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